tcl/target/at91sam9260_ext_RAM_ext_flash.cfg

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   4 jtag_khz 4
   5
   6
   7 ######################################
   8 # Target:    Atmel AT91SAM9260
   9 ######################################
  10
  11 if { [info exists CHIPNAME] } {
  12    set  _CHIPNAME $CHIPNAME
  13 } else {
  14    set  _CHIPNAME at91sam9260
  15 }
  16
  17 if { [info exists ENDIAN] } {
  18    set  _ENDIAN $ENDIAN
  19 } else {
  20    set  _ENDIAN little
  21 }
  22
  23 if { [info exists CPUTAPID ] } {
  24    set _CPUTAPID $CPUTAPID
  25 } else {
  26   # force an error till we get a good number
  27    set _CPUTAPID 0x0792603f
  28 }
  29
  30 reset_config trst_and_srst
  31
  32
  33 jtag_nsrst_delay 200
  34 jtag_ntrst_delay 200
  35
  36
  37 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  38
  39
  40 ######################
  41 # Target configuration
  42 ######################
  43
  44 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
  45 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
  46
  47 $_TARGETNAME invoke-event halted
  48
  49 # Internal sram1 memory
  50 $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
  51
  52 scan_chain
  53 $_TARGETNAME configure -event reset-deassert-post {at91sam_init}
  54
  55
  56 # Flash configuration
  57 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
  58 flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
  59
  60
  61 proc at91sam_init { } {
  62
  63         # at reset chip runs at 32khz
  64         jtag_khz 8
  65         halt
  66         mww 0xfffffd08 0xa5000501         # RSTC_MR : enable user reset
  67         mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
  68
  69         mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
  70         sleep 20                          # wait 20 ms
  71         mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
  72         sleep 10                          # wait 10 ms
  73         mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198,656MHz
  74         sleep 20                          # wait 20 ms
  75         mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler
  76         sleep 10                          # wait 10 ms
  77         mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected
  78         sleep 10                          # wait 10 ms
  79
  80         # Now run at anything fast... ie: 10mhz!
  81         jtag_khz 10000                    # Increase JTAG Speed to 6 MHz
  82         arm7_9 dcc_downloads enable       # Enable faster DCC downloads
  83
  84         mww 0xffffec00 0x0a0a0a0a         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
  85         mww 0xffffec04 0x0b0b0b0b         # SMC_PULSE0
  86         mww 0xffffec08 0x00160016         # SMC_CYCLE0
  87         mww 0xffffec0c 0x00161003         # SMC_MODE0
  88
  89         flash probe 0                     # Identify flash bank 0
  90
  91         mww 0xfffff870 0xffff0000         # PIO_ASR : Select peripheral function for D15..D31
  92         mww 0xfffff804 0xffff0000         # PIO_PDR : Disable PIO function for D15..D31
  93
  94         mww 0xffffef1c 0x2                # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
  95
  96         mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
  97         #mww 0xffffea08 0x85227254         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
  98
  99         mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
 100         mww 0x20000000 0
 101         mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
 102         mww 0x20000000 0
 103         mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
 104         mww 0x20000000 0
 105         mww 0xffffea00 0x4
 106         mww 0x20000000 0
 107         mww 0xffffea00 0x4
 108         mww 0x20000000 0
 109         mww 0xffffea00 0x4
 110         mww 0x20000000 0
 111         mww 0xffffea00 0x4
 112         mww 0x20000000 0
 113         mww 0xffffea00 0x4
 114         mww 0x20000000 0
 115         mww 0xffffea00 0x4
 116         mww 0x20000000 0
 117         mww 0xffffea00 0x4
 118         mww 0x20000000 0
 119         mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
 120         mww 0x20000000 0
 121         mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
 122         mww 0x20000000 0
 123         mww 0xffffea04 0x5d2              # SDRAMC_TR : Set refresh timer count to 15us
 124 }
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