tcl/target/ar71xx.cfg

   1 # Atheros AR71xx MIPS 24Kc SoC.
   2 # tested on PB44 refererence board
   3
   4 adapter_nsrst_delay 100
   5 jtag_ntrst_delay 100
   6
   7 reset_config trst_and_srst
   8
   9 set CHIPNAME ar71xx
  10
  11 jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
  12
  13 set TARGETNAME $CHIPNAME.cpu
  14 target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
  15
  16 $TARGETNAME configure -event reset-halt-post {
  17         #setup PLL to lowest common denominator 300/300/150 setting
  18         mww 0xb8050000 0x000f40a3       ;# reset val + CPU:3 DDR:3 AHB:0
  19         mww 0xb8050000 0x800f40a3       ;# send to PLL
  20
  21         #next command will reset for PLL changes to take effect
  22         mww 0xb8050008 3                ;# set reset_switch and clock_switch (resets SoC)
  23 }
  24
  25 $TARGETNAME configure -event reset-init {
  26         #complete pll initialization
  27         mww 0xb8050000 0x800f0080       ;# set sw_update bit
  28         mww 0xb8050008 0                ;# clear reset_switch bit
  29         mww 0xb8050000 0x800f00e8       ;# clr pwrdwn & bypass
  30         mww 0xb8050008 1                ;# set clock_switch bit
  31         sleep 1                         ;# wait for lock
  32
  33         # Setup DDR config and flash mapping
  34         mww 0xb8000000 0xefbc8cd0       ;# DDR cfg cdl val (rst: 0x5bfc8d0)
  35         mww 0xb8000004 0x8e7156a2       ;# DDR cfg2 cdl val (rst: 0x80d106a8)
  36
  37         mww 0xb8000010 8                ;# force precharge all banks
  38         mww 0xb8000010 1                ;# force EMRS update cycle
  39         mww 0xb800000c 0                ;# clr ext. mode register
  40         mww 0xb8000010 2                ;# force auto refresh all banks
  41         mww 0xb8000010 8                ;# force precharge all banks
  42         mww 0xb8000008 0x31             ;# set DDR mode value CAS=3
  43         mww 0xb8000010 1                ;# force EMRS update cycle
  44         mww 0xb8000014 0x461b           ;# DDR refresh value
  45         mww 0xb8000018 0xffff           ;# DDR Read Data This Cycle value (16bit: 0xffff)
  46         mww 0xb800001c 0x7              ;# delay added to the DQS line (normal = 7)
  47         mww 0xb8000020 0
  48         mww 0xb8000024 0
  49         mww 0xb8000028 0
  50 }
  51
  52 # setup working area somewhere in RAM
  53 $TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
  54
  55 # serial SPI capable flash
  56 # flash bank <driver> <base> <size> <chip_width> <bus_width>
  57