target/stm32: make APCSW cacheable
[openocd.git] / tcl / target / am335x.cfg
1 source [find target/icepick.cfg]
2
3 if { [info exists CHIPNAME] } {
4 set _CHIPNAME $CHIPNAME
5 } else {
6 set _CHIPNAME am335x
7 }
8
9 # set the taps to be enabled by default. this can be overridden
10 # by setting DEFAULT_TAPS in a separate configuration file
11 # or directly on the command line.
12 if { [info exists DEFAULT_TAPS] } {
13 set _DEFAULT_TAPS "$DEFAULT_TAPS"
14 } else {
15 set _DEFAULT_TAPS "$_CHIPNAME.tap"
16 }
17
18 #
19 # Main DAP
20 #
21 if { [info exists DAP_TAPID] } {
22 set _DAP_TAPID $DAP_TAPID
23 } else {
24 set _DAP_TAPID 0x4b6b902f
25 }
26 jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
27 jtag configure $_CHIPNAME.tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0"
28 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
29
30 #
31 # M3 DAP
32 #
33 if { [info exists M3_DAP_TAPID] } {
34 set _M3_DAP_TAPID $M3_DAP_TAPID
35 } else {
36 set _M3_DAP_TAPID 0x4b6b902f
37 }
38 jtag newtap $_CHIPNAME m3_tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
39 jtag configure $_CHIPNAME.m3_tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0"
40 dap create $_CHIPNAME.m3_dap -chain-position $_CHIPNAME.m3_tap
41
42 #
43 # ICEpick-D (JTAG route controller)
44 #
45 if { [info exists JRC_TAPID] } {
46 set _JRC_TAPID $JRC_TAPID
47 } else {
48 set _JRC_TAPID 0x0b94402f
49 }
50 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
51 jtag configure $_CHIPNAME.jrc -event setup {
52 global _DEFAULT_TAPS
53 enable_default_taps $_DEFAULT_TAPS
54 }
55 # some TCK tycles are required to activate the DEBUG power domain
56 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
57
58 #
59 # helper function that enables all taps passed as argument
60 #
61 proc enable_default_taps { taps } {
62 foreach tap $taps {
63 jtag tapenable $tap
64 }
65 }
66
67 #
68 # Cortex-M3 target
69 #
70 set _TARGETNAME_2 $_CHIPNAME.m3
71 target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.m3_dap
72
73 #
74 # Cortex-A8 target
75 #
76 set _TARGETNAME $_CHIPNAME.cpu
77 target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80001000
78
79 # SRAM: 64K at 0x4030.0000; use the first 16K
80 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
81
82
83 # when putting the target into 'reset halt', we need to disable the watchdog as
84 # it would otherwise trigger while we're in JTAG
85 # FIXME: unify with target/am437x.cfg
86 source [find mem_helper.tcl]
87 set WDT1_BASE_ADDR 0x44e35000
88 set WDT1_W_PEND_WSPR [expr $WDT1_BASE_ADDR + 0x0034]
89 set WDT1_WSPR [expr $WDT1_BASE_ADDR + 0x0048]
90 proc disable_watchdog { } {
91 global WDT1_WSPR
92 global WDT1_W_PEND_WSPR
93 global _TARGETNAME
94
95 set curstate [$_TARGETNAME curstate]
96
97 if { [string compare $curstate halted] == 0 } {
98 set WDT_DISABLE_SEQ1 0xaaaa
99 set WDT_DISABLE_SEQ2 0x5555
100
101 mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1
102
103 # Empty body to make sure this executes as fast as possible.
104 # We don't want any delays here otherwise romcode might start
105 # executing and end up changing state of certain IPs.
106 while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
107
108 mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
109 while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
110 }
111 }
112 $_TARGETNAME configure -event reset-end { disable_watchdog }

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