tcl/board/unknown_at91sam9260.cfg

   1 # Thanks to Pieter Conradie for this script!
   2 #
   3 # Unknown vendor board contains:
   4 #
   5 # Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz
   6 #                     OSCSEL configured for internal RC oscillator (22 to 42 kHz)
   7 #
   8 # 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit
   9 # 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks
  10 ##################################################################
  11
  12 # We add to the minimal configuration.
  13 source [find target/at91sam9260.cfg]
  14
  15 $_TARGETNAME configure -event reset-start {
  16         # At reset CPU runs at 22 to 42 kHz.
  17         # JTAG Frequency must be 6 times slower.
  18         jtag_rclk 3
  19         halt
  20         # RSTC_MR : enable user reset, MMU may be enabled... use physical address
  21         mww phys 0xfffffd08 0xa5000501
  22 }
  23
  24
  25 $_TARGETNAME configure -event reset-init {
  26         mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
  27
  28         mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
  29         sleep 20                          # wait 20 ms
  30         mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
  31         sleep 10                          # wait 10 ms
  32         mww 0xfffffc28 0x205dbf09         # CKGR_PLLAR: Set PLLA Register for 192.512MHz
  33         sleep 20                          # wait 20 ms
  34         mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler (divide by 2)
  35         sleep 10                          # wait 10 ms
  36         mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
  37         sleep 10                          # wait 10 ms
  38
  39         # Increase JTAG Speed to 6 MHz if RCLK is not supported
  40         jtag_rclk 6000
  41
  42         arm7_9 dcc_downloads enable       # Enable faster DCC downloads
  43
  44         mww 0xffffec00 0x01020102         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
  45         mww 0xffffec04 0x09070806         # SMC_PULSE0
  46         mww 0xffffec08 0x000d000b         # SMC_CYCLE0
  47         mww 0xffffec0c 0x00001003         # SMC_MODE0
  48
  49         flash probe 0                     # Identify flash bank 0
  50
  51         mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
  52         mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
  53         mww 0xfffff860 0xffff0000         # PIO_PUDR : Disable D15..D31 pull-ups
  54
  55         mww 0xffffef1c 0x00010102         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM
  56                                           #            VDDIOMSEL set for +3V3 memory
  57                                           #            Disable D0..D15 pull-ups
  58
  59         mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
  60
  61         mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
  62         mww 0x20000000 0
  63         mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
  64         mww 0x20000000 0
  65         mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
  66         mww 0x20000000 0
  67         mww 0xffffea00 0x4
  68         mww 0x20000000 0
  69         mww 0xffffea00 0x4
  70         mww 0x20000000 0
  71         mww 0xffffea00 0x4
  72         mww 0x20000000 0
  73         mww 0xffffea00 0x4
  74         mww 0x20000000 0
  75         mww 0xffffea00 0x4
  76         mww 0x20000000 0
  77         mww 0xffffea00 0x4
  78         mww 0x20000000 0
  79         mww 0xffffea00 0x4
  80         mww 0x20000000 0
  81         mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
  82         mww 0x20000000 0
  83         mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
  84         mww 0x20000000 0
  85         mww 0xffffea04 0x2a2              # SDRAMC_TR : Set refresh timer count to 7us
  86 }
  87
  88
  89 #####################
  90 # Flash configuration
  91 #####################
  92
  93 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
  94 flash bank cfi 0x10000000 0x01000000 2 2 0
  95
  96