c317916206003032fb7fcca7bdb59758114bb97a
[openocd.git] / tcl / board / tp-link_wdr4300.cfg
1 source [find target/atheros_ar9344.cfg]
2
3 reset_config trst_only separate
4
5 proc ar9344_40mhz_pll_init {} {
6         # QCA_PLL_SRIF_CPU_DPLL2_REG
7         mww 0xb81161C4 0x13210f00
8         # QCA_PLL_SRIF_CPU_DPLL3_REG
9         mww 0xb81161C8 0x03000000
10         # QCA_PLL_SRIF_DDR_DPLL2_REG
11         mww 0xb8116244 0x13210f00
12         # QCA_PLL_SRIF_DDR_DPLL3_REG
13         mww 0xb8116248 0x03000000
14         # QCA_PLL_SRIF_BB_DPLL_BASE_REG
15         mww 0xb8116188 0x03000000
16
17         # QCA_PLL_CPU_DDR_CLK_CTRL_REG
18         mww 0xb8050008 0x0130001C
19         mww 0xb8050008 0x0130001C
20         mww 0xb8050008 0x0130001C
21
22         # QCA_PLL_CPU_PLL_CFG_REG
23         mww 0xb8050000 0x40021380
24         # QCA_PLL_DDR_PLL_CFG_REG
25         mww 0xb8050004 0x40815800
26         # QCA_PLL_CPU_DDR_CLK_CTRL_REG
27         mww 0xb8050008 0x0130801C
28
29         # QCA_PLL_SRIF_CPU_DPLL2_REG
30         mww 0xb81161C4 0x10810F00
31         mww 0xb81161C0 0x41C00000
32         # QCA_PLL_SRIF_CPU_DPLL2_REG
33         mww 0xb81161C4 0xD0810F00
34         # QCA_PLL_SRIF_CPU_DPLL3_REG
35         mww 0xb81161C8 0x03000000
36         # QCA_PLL_SRIF_CPU_DPLL2_REG
37         mww 0xb81161C4 0xD0800F00
38
39         # QCA_PLL_SRIF_CPU_DPLL3_REG
40         mww 0xb81161C8 0x03000000
41         # QCA_PLL_SRIF_CPU_DPLL3_REG
42         mww 0xb81161C8 0x43000000
43         # QCA_PLL_SRIF_CPU_DPLL3_REG
44         mww 0xb81161C8 0x030003E8
45
46         # QCA_PLL_SRIF_DDR_DPLL2_REG
47         mww 0xb8116244 0x10810F00
48         mww 0xb8116240 0x41680000
49         # QCA_PLL_SRIF_DDR_DPLL2_REG
50         mww 0xb8116244 0xD0810F00
51         # QCA_PLL_SRIF_DDR_DPLL3_REG
52         mww 0xb8116248 0x03000000
53         # QCA_PLL_SRIF_DDR_DPLL2_REG
54         mww 0xb8116244 0xD0800F00
55
56         # QCA_PLL_SRIF_DDR_DPLL3_REG
57         mww 0xb8116248 0x03000000
58         # QCA_PLL_SRIF_DDR_DPLL3_REG
59         mww 0xb8116248 0x43000000
60         # QCA_PLL_SRIF_DDR_DPLL3_REG
61         mww 0xb8116248 0x03000718
62
63         # QCA_PLL_CPU_DDR_CLK_CTRL_REG
64         mww 0xb8050008 0x01308018
65         mww 0xb8050008 0x01308010
66         mww 0xb8050008 0x01308000
67
68         # QCA_PLL_DDR_PLL_DITHER_REG
69         mww 0xb8050044 0x78180200
70         # QCA_PLL_CPU_PLL_DITHER_REG
71         mww 0xb8050048 0x41C00000
72
73 }
74
75 proc ar9344_ddr_init {} {
76         # QCA_DDR_CTRL_CFG_REG
77         mww 0xb8000108 0x40
78         # QCA_DDR_RD_DATA_THIS_CYCLE_REG
79         mww 0xb8000018 0xFF
80         # QCA_DDR_BURST_REG
81         mww 0xb80000C4 0x74444444
82         # QCA_DDR_BURST2_REG
83         mww 0xb80000C8 0x0222
84         # QCA_AHB_MASTER_TOUT_MAX_REG
85         mww 0xb80000CC 0xFFFFF
86
87         # QCA_DDR_CFG_REG
88         mww 0xb8000000 0xC7D48CD0
89         # QCA_DDR_CFG2_REG
90         mww 0xb8000004 0x9DD0E6A8
91
92         # QCA_DDR_DDR2_CFG_REG
93         mww 0xb80000B8 0x0E59
94         # QCA_DDR_CFG2_REG
95         mww 0xb8000004 0x9DD0E6A8
96
97         # QCA_DDR_CTRL_REG
98         mww 0xb8000010 0x08
99         mww 0xb8000010 0x08
100         mww 0xb8000010 0x10
101         mww 0xb8000010 0x20
102         # QCA_DDR_EMR_REG
103         mww 0xb800000C 0x02
104         # QCA_DDR_CTRL_REG
105         mww 0xb8000010 0x02
106
107         # QCA_DDR_MR_REG
108         mww 0xb8000008 0x0133
109         # QCA_DDR_CTRL_REG
110         mww 0xb8000010 0x1
111         mww 0xb8000010 0x8
112         mww 0xb8000010 0x8
113         mww 0xb8000010 0x4
114         mww 0xb8000010 0x4
115
116         # QCA_DDR_MR_REG
117         mww 0xb8000008 0x33
118         # QCA_DDR_CTRL_REG
119         mww 0xb8000010 0x1
120
121         # QCA_DDR_EMR_REG
122         mww 0xb800000C 0x0382
123         # QCA_DDR_CTRL_REG
124         mww 0xb8000010 0x2
125         # QCA_DDR_EMR_REG
126         mww 0xb800000C 0x0402
127         # QCA_DDR_CTRL_REG
128         mww 0xb8000010 0x2
129
130         # QCA_DDR_REFRESH_REG
131         mww 0xb8000014 0x4270
132
133         # QCA_DDR_TAP_CTRL_0_REG
134         mww 0xb800001C 0x0e
135         # QCA_DDR_TAP_CTRL_1_REG
136         mww 0xb8000020 0x0e
137         # QCA_DDR_TAP_CTRL_2_REG
138         mww 0xb8000024 0x0e
139         # QCA_DDR_TAP_CTRL_3_REG
140         mww 0xb8000028 0x0e
141 }
142
143 $_TARGETNAME configure -event reset-init {
144
145         # mww 0xb806001c 0x1000000
146         ar9344_40mhz_pll_init
147         sleep 100
148
149         # flash remap
150         # SPI_CONTROL_ADDR
151         mww 0xbF000004 0x43
152
153         ar9344_ddr_init
154         sleep 100
155 }
156
157 set ram_boot_address 0xa0000000
158 $_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000
159
160 flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0