tcl/board/topasa900.cfg

   1 # Thanks to Pieter Conradie for this script!
   2 # Target:    Toshiba TOPAS900 -- TMPA900 Starterkit
   3 ######################################
   4
   5 # We add to the minimal configuration.
   6 source [find target/tmpa900.cfg]
   7
   8 ######################
   9 # Target configuration
  10 ######################
  11
  12 #$_TARGETNAME configure -event gdb-attach { reset init }
  13 $_TARGETNAME configure -event reset-init { topasa900_init }
  14
  15 proc topasa900_init { } {
  16 # Init PLL
  17 # my settings
  18         mww 0xf005000c 0x00000007
  19         mww 0xf0050010 0x00000065
  20         mww 0xf005000c 0x000000a7
  21         sleep 10
  22         mdw 0xf0050008
  23         mww 0xf0050008 0x00000002
  24         mww 0xf0050004 0x00000000
  25 # NEW: set CLKCR5
  26         mww 0xf0050054 0x00000040
  27 #
  28 # bplan settings
  29 #       mww 0xf0050004 0x00000000
  30 #       mww 0xf005000c 0x000000a7
  31 #       sleep 10
  32 #       mdw 0xf0050008
  33 #       mww 0xf0050008 0x00000002
  34 #       mww 0xf0050010 0x00000065
  35 #       mww 0xf0050054 0x00000040
  36         sleep 10
  37 # Init SDRAM
  38 #  _PMCDRV          = 0x00000071;
  39 #  //
  40 #  // Initialize SDRAM timing parameter
  41 #  //
  42 #  _DMC_CAS_LATENCY = 0x00000006;
  43 #  _DMC_T_DQSS      = 0x00000000;
  44 #  _DMC_T_MRD       = 0x00000002;
  45 #  _DMC_T_RAS       = 0x00000007;
  46 #
  47 #  _DMC_T_RC        = 0x0000000A;
  48 #  _DMC_T_RCD       = 0x00000013;
  49 #
  50 #  _DMC_T_RFC       = 0x0000010A;
  51 #
  52 #  _DMC_T_RP        = 0x00000013;
  53 #  _DMC_T_RRD       = 0x00000002;
  54 #  _DMC_T_WR        = 0x00000002;
  55 #  _DMC_T_WTR       = 0x00000001;
  56 #  _DMC_T_XP        = 0x0000000A;
  57 #  _DMC_T_XSR       = 0x0000000B;
  58 #  _DMC_T_ESR       = 0x00000014;
  59 #
  60 #  //
  61 #  // Configure SDRAM type parameter
  62 #  _DMC_MEMORY_CFG  = 0x00008011;
  63 #  _DMC_USER_CONFIG = 0x00000011;   // 32 bit memory interface
  64 #
  65 #
  66 #  _DMC_REFRESH_PRD = 0x00000A60;
  67 #  _DMC_CHIP_0_CFG  = 0x000140FC;
  68 #
  69 #  _DMC_DIRECT_CMD  = 0x000C0000;
  70 #  _DMC_DIRECT_CMD  = 0x00000000;
  71 #
  72 #  _DMC_DIRECT_CMD  = 0x00040000;
  73 #  _DMC_DIRECT_CMD  = 0x00040000;
  74 #  _DMC_DIRECT_CMD  = 0x00080031;
  75 #  //
  76 #  // Finally start SDRAM
  77 #  //
  78 #  _DMC_MEMC_CMD    = MEMC_CMD_GO;
  79 #  */
  80
  81         mww 0xf0020260 0x00000071
  82         mww 0xf4300014 0x00000006
  83         mww 0xf4300018 0x00000000
  84         mww 0xf430001C 0x00000002
  85         mww 0xf4300020 0x00000007
  86         mww 0xf4300024 0x0000000A
  87         mww 0xf4300028 0x00000013
  88         mww 0xf430002C 0x0000010A
  89         mww 0xf4300030 0x00000013
  90         mww 0xf4300034 0x00000002
  91         mww 0xf4300038 0x00000002
  92         mww 0xf430003C 0x00000001
  93         mww 0xf4300040 0x0000000A
  94         mww 0xf4300044 0x0000000B
  95         mww 0xf4300048 0x00000014
  96         mww 0xf430000C 0x00008011
  97         mww 0xf4300304 0x00000011
  98         mww 0xf4300010 0x00000A60
  99         mww 0xf4300200 0x000140FC
 100         mww 0xf4300008 0x000C0000
 101         mww 0xf4300008 0x00000000
 102         mww 0xf4300008 0x00040000
 103         mww 0xf4300008 0x00040000
 104         mww 0xf4300008 0x00080031
 105         mww 0xf4300004 0x00000000
 106
 107         sleep 10
 108 #       adapter speed NNNN
 109
 110 # remap off in case of IROM boot
 111         mww 0xf0000004 0x00000001
 112
 113 }
 114
 115 # comment the following out if usinf J-Link, it soes not support DCC
 116 arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
 117
 118
 119 #####################
 120 # Flash configuration
 121 #####################
 122
 123 #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
 124 set _FLASHNAME $_CHIPNAME.flash
 125 flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 $_TARGETNAME