tcl/board/spear310evb20.cfg

   1 # Configuration for the ST SPEAr310 Evaluation board
   2 # EVALSPEAr310 Rev. 2.0
   3 # http://www.st.com/spear
   4 #
   5 # Date:      2010-08-17
   6 # Author:    Antonio Borneo <borneo.antonio@gmail.com>
   7
   8 # The standard board has JTAG SRST not connected.
   9 # This script targets such boards using quirky code to bypass the issue.
  10 #
  11 # Check ST Application Note AN3321 on how to fix SRST on
  12 # the board, then use the script board/spear310evb20_mod.cfg
  13
  14
  15 source [find mem_helper.tcl]
  16 source [find target/spear3xx.cfg]
  17 source [find chip/st/spear/spear310.tcl]
  18 source [find chip/st/spear/spear3xx_ddr.tcl]
  19 source [find chip/st/spear/spear3xx.tcl]
  20
  21 arm7_9 dcc_downloads enable
  22 arm7_9 fast_memory_access enable
  23
  24 # CFI parallel NOR on EMI CS0. 2x 16bit 8M devices = 16Mbyte.
  25 set _FLASHNAME0 $_CHIPNAME.pnor
  26 flash bank $_FLASHNAME0 cfi 0x50000000 0x01000000 2 4 $_TARGETNAME
  27
  28 # Serial NOR on SMI CS0. 8Mbyte.
  29 set _FLASHNAME1 $_CHIPNAME.snor
  30 flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
  31
  32 if { [info exists BOARD_HAS_SRST] } {
  33         # Modified board has SRST on JTAG connector
  34         reset_config trst_and_srst separate srst_gates_jtag \
  35                 trst_push_pull srst_open_drain
  36 } else {
  37         # Standard board has no SRST on JTAG connector
  38         reset_config trst_only separate srst_gates_jtag trst_push_pull
  39         source [find chip/st/spear/quirk_no_srst.tcl]
  40 }
  41
  42 $_TARGETNAME configure -event reset-init { spear310evb20_init }
  43
  44 proc spear310evb20_init {} {
  45         reg pc 0xffff0020       ;# loop forever
  46
  47         sp3xx_clock_default
  48         sp3xx_common_init
  49         sp3xx_ddr_init "mt47h64m16_3_333_cl5_async"
  50         sp310_init
  51         sp310_emi_init
  52 }