tcl/board/olimex_sam9_l9260.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 ################################################################################
   4 # Olimex SAM9-L9260 Development Board
   5 #
   6 # http://www.olimex.com/dev/sam9-L9260.html
   7 #
   8 # Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
   9 #                     PMC configured for external 18.432 MHz crystal
  10 #
  11 # 32-bit SDRAM : 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks
  12 # 8-bit NAND Flash : 1 x Samsung K9F4G08U0M, 512M x 8Bit
  13 # Dataflash : 1 x Atmel AT45DB161D, 16Mbit
  14 #
  15 ################################################################################
  16
  17 source [find target/at91sam9260.cfg]
  18
  19 # NTRST_E jumper is enabled by default, so we don't need to override the reset
  20 # config.
  21 #reset_config srst_only
  22
  23 $_TARGETNAME configure -event reset-start {
  24         # At reset, CPU runs at 32.768 kHz.  JTAG frequency must be 6 times slower if
  25         # RCLK is not supported.
  26         jtag_rclk 5
  27         halt
  28
  29         # RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may
  30         # be enabled... use physical address.
  31         mww phys 0xfffffd08 0xa5000501
  32 }
  33
  34 $_TARGETNAME configure -event reset-init {
  35         mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
  36
  37         ##
  38         # Clock configuration for 99.328 MHz main clock.
  39         ##
  40     echo "Setting up clock"
  41         mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable main oscillator, 512 slow clock startup
  42         sleep 20                  ;# wait 20 ms (need 15.6 ms for startup)
  43         mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator (18.432 MHz)
  44         sleep 10                  ;# wait 10 ms
  45         mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup
  46         sleep 20                  ;# wait 20 ms (need 1.9 ms for startup)
  47         mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2
  48         sleep 10                  ;# wait 10 ms
  49         mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz)
  50
  51         # Increase JTAG speed to 6 MHz if RCLK is not supported.
  52         jtag_rclk 6000
  53
  54         arm7_9 dcc_downloads enable ;# Enable faster DCC downloads.
  55
  56         ##
  57         # SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
  58         ##
  59     echo "Configuring SDRAM"
  60         mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31
  61         mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31
  62
  63         mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
  64
  65         mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips
  66
  67         mww 0xffffea00 0x1        ;# SDRAMC_MR : issue NOP command
  68         mww 0x20000000 0
  69         mww 0xffffea00 0x2        ;# SDRAMC_MR : issue an 'All Banks Precharge' command
  70         mww 0x20000000 0
  71         mww 0xffffea00 0x4        ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' command
  72         mww 0x20000000 0
  73         mww 0xffffea00 0x4
  74         mww 0x20000000 0
  75         mww 0xffffea00 0x4
  76         mww 0x20000000 0
  77         mww 0xffffea00 0x4
  78         mww 0x20000000 0
  79         mww 0xffffea00 0x4
  80         mww 0x20000000 0
  81         mww 0xffffea00 0x4
  82         mww 0x20000000 0
  83         mww 0xffffea00 0x4
  84         mww 0x20000000 0
  85         mww 0xffffea00 0x4
  86         mww 0x20000000 0
  87         mww 0xffffea00 0x3        ;# SDRAMC_MR : issue a 'Load Mode Register' command
  88         mww 0x20000000 0
  89         mww 0xffffea00 0x0        ;# SDRAMC_MR : normal mode
  90         mww 0x20000000 0
  91
  92         mww 0xffffea04 0x2b6      ;# SDRAMC_TR : set refresh timer count to 7 us
  93
  94     ##
  95     # NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit.
  96     ##
  97     echo "Configuring NAND flash"
  98     mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
  99     mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
 100     mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
 101     mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
 102     mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
 103     mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13
 104
 105     mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before
 106
 107     mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
 108     mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
 109     mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle
 110     mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
 111                                #             3 TDF cycles, no optimization
 112
 113     mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
 114     mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
 115
 116     nand probe at91sam9260.flash
 117
 118     ##
 119     # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
 120     ##
 121     echo "Setting up dataflash"
 122     mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),
 123                                #            2(SPI0_SPCK), and 11(SPI0_NPCS1)
 124     mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
 125     mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
 126     mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock
 127
 128     mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
 129     mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
 130     mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected
 131
 132     mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,
 133                                #             250ns delay before SPCK, 250ns b/n tx
 134
 135     mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
 136     mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
 137 }
 138
 139 nand device at91sam9260.flash at91sam9 at91sam9260.cpu 0x40000000 0xffffe800
 140 at91sam9 cle 0 22
 141 at91sam9 ale 0 21
 142 at91sam9 rdy_busy 0 0xfffff800 13
 143 at91sam9 ce 0 0xfffff800 14