tcl/board/olimex_sam9_l9260.cfg

   1 ################################################################################
   2 # Olimex SAM9-L9260 Development Board
   3 #
   4 # http://www.olimex.com/dev/sam9-L9260.html
   5 #
   6 # Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
   7 #                     PMC configured for external 18.432 MHz crystal
   8 #
   9 # 32-bit SDRAM : 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks
  10 # 8-bit NAND Flash : 1 x Samsung K9F4G08U0M, 512M x 8Bit
  11 # Dataflash : 1 x Atmel AT45DB161D, 16Mbit
  12 #
  13 ################################################################################
  14
  15 source [find target/at91sam9260.cfg]
  16
  17 # NTRST_E jumper is enabled by default, so we don't need to override the reset
  18 # config.
  19 #reset_config srst_only
  20
  21 $_TARGETNAME configure -event reset-start {
  22         # At reset, CPU runs at 32.768 kHz.  JTAG frequency must be 6 times slower if
  23         # RCLK is not supported.
  24         jtag_rclk 5
  25         halt
  26
  27         # RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may
  28         # be enabled... use physical address.
  29         mww phys 0xfffffd08 0xa5000501
  30 }
  31
  32 $_TARGETNAME configure -event reset-init {
  33         mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
  34
  35         ##
  36         # Clock configuration for 99.328 MHz main clock.
  37         ##
  38         mww 0xfffffc20 0x00004001 # CKGR_MOR : enable main oscillator, 512 slow clock startup
  39         sleep 20                  # wait 20 ms (need 15.6 ms for startup)
  40         mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator (18.432 MHz)
  41         sleep 10                  # wait 10 ms
  42         mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup
  43         sleep 20                  # wait 20 ms (need 1.9 ms for startup)
  44         mww 0xfffffc30 0x00000101 # PMC_MCKR : no scale on proc clock, master is proc / 2
  45         sleep 10                  # wait 10 ms
  46         mww 0xfffffc30 0x00000102 # PMC_MCKR : switch to PLLA (99.328 MHz)
  47
  48         # Increase JTAG speed to 6 MHz if RCLK is not supported.
  49         jtag_rclk 6000
  50
  51         arm7_9 dcc_downloads enable # Enable faster DCC downloads.
  52
  53         ##
  54         # SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
  55         ##
  56         mww 0xfffff870 0xffff0000 # PIOC_ASR : select peripheral function for D15..D31
  57         mww 0xfffff804 0xffff0000 # PIOC_PDR : disable PIO function for D15..D31
  58
  59         mww 0xffffef1c 0x00010002 # EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
  60
  61         mww 0xffffea08 0x85237259 # SDRAMC_CR : configure SDRAM for Samsung chips
  62
  63         mww 0xffffea00 0x1        # SDRAMC_MR : issue NOP command
  64         mww 0x20000000 0
  65         mww 0xffffea00 0x2        # SDRAMC_MR : issue an 'All Banks Precharge' command
  66         mww 0x20000000 0
  67         mww 0xffffea00 0x4        # SDRAMC_MR : issue 8 x 'Auto-Refresh' command
  68         mww 0x20000000 0
  69         mww 0xffffea00 0x4
  70         mww 0x20000000 0
  71         mww 0xffffea00 0x4
  72         mww 0x20000000 0
  73         mww 0xffffea00 0x4
  74         mww 0x20000000 0
  75         mww 0xffffea00 0x4
  76         mww 0x20000000 0
  77         mww 0xffffea00 0x4
  78         mww 0x20000000 0
  79         mww 0xffffea00 0x4
  80         mww 0x20000000 0
  81         mww 0xffffea00 0x4
  82         mww 0x20000000 0
  83         mww 0xffffea00 0x3        # SDRAMC_MR : issue a 'Load Mode Register' command
  84         mww 0x20000000 0
  85         mww 0xffffea00 0x0        # SDRAMC_MR : normal mode
  86         mww 0x20000000 0
  87
  88         mww 0xffffea04 0x2b6      # SDRAMC_TR : set refresh timer count to 7 us
  89 }