tcl/board/nxp_imx7sabre.cfg

   1 # NXP IMX7SABRE board
   2 # use on-board JTAG header
   3 transport select jtag
   4
   5 # set a safe speed, can be overridden
   6 adapter_khz 1000
   7
   8 # reset configuration has TRST and SRST support
   9 reset_config trst_and_srst srst_push_pull
  10 # need at least 100ms delay after SRST release for JTAG
  11 adapter_nsrst_delay 100
  12
  13 # source the target file
  14 source [find target/imx7.cfg]
  15 # import mrw proc
  16 source [find mem_helper.tcl]
  17
  18 # function to disable the on-chip watchdog
  19 proc imx7_disable_wdog { } {
  20         # echo "disable watchdog power-down counter"
  21         mwh phys 0x30280008 0x00
  22 }
  23
  24 proc imx7_uart_dbgconf { } {
  25         # disable response to debug_req signal for uart1
  26         mww phys 0x308600b4 0x0a60
  27 }
  28
  29 proc check_bits_set_32 { addr mask } {
  30     while { [expr [mrw $addr] & $mask == 0] } { }
  31 }
  32
  33 proc apply_dcd { } {
  34     # echo "apply dcd"
  35
  36     mww phys 0x30340004 0x4F400005
  37     # Clear then set bit30 to ensure exit from DDR retention
  38     mww phys 0x30360388 0x40000000
  39     mww phys 0x30360384 0x40000000
  40
  41     mww phys 0x30391000 0x00000002
  42     mww phys 0x307a0000 0x01040001
  43     mww phys 0x307a01a0 0x80400003
  44     mww phys 0x307a01a4 0x00100020
  45     mww phys 0x307a01a8 0x80100004
  46     mww phys 0x307a0064 0x00400046
  47     mww phys 0x307a0490 0x00000001
  48     mww phys 0x307a00d0 0x00020083
  49     mww phys 0x307a00d4 0x00690000
  50     mww phys 0x307a00dc 0x09300004
  51     mww phys 0x307a00e0 0x04080000
  52     mww phys 0x307a00e4 0x00100004
  53     mww phys 0x307a00f4 0x0000033f
  54     mww phys 0x307a0100 0x09081109
  55     mww phys 0x307a0104 0x0007020d
  56     mww phys 0x307a0108 0x03040407
  57     mww phys 0x307a010c 0x00002006
  58     mww phys 0x307a0110 0x04020205
  59     mww phys 0x307a0114 0x03030202
  60     mww phys 0x307a0120 0x00000803
  61     mww phys 0x307a0180 0x00800020
  62     mww phys 0x307a0184 0x02000100
  63     mww phys 0x307a0190 0x02098204
  64     mww phys 0x307a0194 0x00030303
  65     mww phys 0x307a0200 0x00000016
  66     mww phys 0x307a0204 0x00171717
  67     mww phys 0x307a0214 0x04040404
  68     mww phys 0x307a0218 0x0f040404
  69     mww phys 0x307a0240 0x06000604
  70     mww phys 0x307a0244 0x00000001
  71     mww phys 0x30391000 0x00000000
  72     mww phys 0x30790000 0x17420f40
  73     mww phys 0x30790004 0x10210100
  74     mww phys 0x30790010 0x00060807
  75     mww phys 0x307900b0 0x1010007e
  76     mww phys 0x3079009c 0x00000d6e
  77     mww phys 0x30790020 0x08080808
  78     mww phys 0x30790030 0x08080808
  79     mww phys 0x30790050 0x01000010
  80     mww phys 0x30790050 0x00000010
  81
  82     mww phys 0x307900c0 0x0e407304
  83     mww phys 0x307900c0 0x0e447304
  84     mww phys 0x307900c0 0x0e447306
  85
  86     check_bits_set_32 0x307900c4 0x1
  87
  88     mww phys 0x307900c0 0x0e447304
  89     mww phys 0x307900c0 0x0e407304
  90
  91
  92     mww phys 0x30384130 0x00000000
  93     mww phys 0x30340020 0x00000178
  94     mww phys 0x30384130 0x00000002
  95     mww phys 0x30790018 0x0000000f
  96
  97     check_bits_set_32 0x307a0004 0x1
  98 }
  99
 100 # disable internal reset-assert handling to
 101 # allow reset-init to work
 102 $_TARGETNAME.0 configure -event reset-assert ""
 103 $_TARGETNAME.1 configure -event reset-assert ""
 104 $_TARGETNAME_2 configure -event reset-assert ""
 105
 106 $_TARGETNAME.0 configure -event reset-init {
 107     global _CHIPNAME
 108     imx7_disable_wdog
 109     imx7_uart_dbgconf
 110     apply_dcd
 111     $_CHIPNAME.dap memaccess 0
 112 }
 113
 114 target smp $_TARGETNAME.0 $_TARGETNAME.1