tcl/board/mini6410.cfg

   1 # Target configuration for the Samsung s3c6410 system on chip
   2 # Tested on a tiny6410
   3 # Processor       : ARM1176
   4 # Info : JTAG tap: s3c6410.etb tap/device found: 0x2b900f0f (mfg: 0x787, part: 0xb900, ver: 0x2)
   5 # Info : JTAG tap: s3c6410.cpu tap/device found: 0x07b76f0f (mfg: 0x787, part: 0x7b76, ver: 0x0)
   6
   7 source [find target/samsung_s3c6410.cfg]
   8
   9 proc init_6410 {} {
  10         halt
  11         reg cpsr 0x1D3
  12         arm mcr 15 0 15 2 4 0x70000013
  13
  14         #-----------------------------------------------
  15         # Clock and Timer Setting
  16         #-----------------------------------------------
  17         mww 0x7e004000 0                ;# WATCHDOG     - Disable
  18         mww 0x7E00F120 0x0003           ;# MEM_SYS_CFG  - CS0:8 bit, Mem1:32bit, CS2=NAND
  19         #mww 0x7E00F120 0x1000          ;# MEM_SYS_CFG  - CS0:16bit, Mem1:32bit, CS2=SROMC
  20         #mww 0x7E00F120 0x1002          ;# MEM_SYS_CFG  - CS0:16bit, Mem1:32bit, CS2=OND
  21         mww 0x7E00F900 0x805e           ;# OTHERS       - Change SYNCMUX[6] to “1”
  22         sleep 1000
  23         mww 0x7E00F900 0x80de           ;# OTHERS       - Assert SYNCREQ&VICSYNCEN to “1”(rb1004modify)
  24         sleep 1000                      ;#              - Others[11:8] to 0xF
  25         mww 0x7E00F000 0xffff           ;# APLL_LOCK    - APLL LockTime
  26         mww 0x7E00F004 0xffff           ;# MPLL_LOCK    - MPLL LockTime
  27         mww 0x7E00F020 0x1047310        ;# CLK_DIV0     - ARMCLK:HCLK:PCLK = 1:4:16
  28         mww 0x7E00F00c 0x81900302       ;# APLL_CON     - A:400, P:3, S:2 => 400MHz
  29         mww 0x7E00F010 0x81900303       ;# MPLL_CON     - M:400, P:3, S:3 => 200MHz
  30         mww 0x7E00F01c 0x3              ;# CLK_SRC      - APLL,MPLL Clock Select
  31
  32         #-----------------------------------------------
  33         # DRAM initialization
  34         #-----------------------------------------------
  35         mww 0x7e001004 0x4              ;# P1MEMCCMD    - Enter the config state
  36         mww 0x7e001010 0x30C            ;# P1REFRESH    - Refresh Period register (7800ns), 100MHz
  37 #       mww 0x7e001010 0x40e            ;# P1REFRESH    - Refresh Period register (7800ns), 133MHz
  38         mww 0x7e001014 0x6              ;# P1CASLAT     - CAS Latency = 3
  39         mww 0x7e001018 0x1              ;# P1T_DQSS
  40         mww 0x7e00101c 0x2              ;# P1T_MRD
  41         mww 0x7e001020 0x7              ;# P1T_RAS      - 45 ns
  42         mww 0x7e001024 0xA              ;# P1T_RC       - 67.5 ns
  43         mww 0x7e001028 0xC              ;# P1T_RCD      - 22.5 ns
  44         mww 0x7e00102C 0x10B            ;# P1T_RFC      - 80 ns
  45         mww 0x7e001030 0xC              ;# P1T_RP       - 22.5 ns
  46         mww 0x7e001034 0x3              ;# P1T_RRD      - 15 ns
  47         mww 0x7e001038 0x3              ;# P1T_WR       - 15 ns
  48         mww 0x7e00103C 0x2              ;# P1T_WTR
  49         mww 0x7e001040 0x2              ;# P1T_XP
  50         mww 0x7e001044 0x11             ;# P1T_XSR      - 120 ns
  51         mww 0x7e001048 0x11             ;# P1T_ESR
  52
  53         #-----------------------------------------------
  54         # Memory Configuration Registers
  55         #-----------------------------------------------
  56         mww 0x7e00100C 0x00010012       ;# P1MEMCFG     - 1 CKE, 1Chip, 4burst, Alw, AP[10],ROW/Column bit
  57         mww 0x7e00104C 0x0B41           ;# P1MEMCFG2    - Read delay 1 Cycle, mDDR, 32bit, Sync.
  58         mww 0x7e001200 0x150F0          ;# CHIP_N_CFG   - 0x150F0 for 256M, 0x150F8 for 128M
  59
  60         #-----------------------------------------------
  61         # Memory Direct Commands
  62         #-----------------------------------------------
  63         mww 0x7e001008 0xc0000          ;# Chip0 Direct Command :NOP5
  64         mww 0x7e001008 0x0              ;# Chip0 Direct Command :PreCharge al
  65         mww 0x7e001008 0x40000          ;# Chip0 Direct Command :AutoRefresh
  66         mww 0x7e001008 0x40000          ;# Chip0 Direct Command :AutoRefresh
  67         mww 0x7e001008 0xA0000          ;# EMRS, DS:Full, PASR:Full
  68         mww 0x7e001008 0x80032          ;# MRS, CAS3, BL4
  69         mww 0x7e001004 0x0              ;# Enable DMC1
  70 }
  71
  72 proc install_6410_uboot {} {
  73         # write U-boot magic number
  74         mww 0x50000000 0x24564236
  75         mww 0x50000004 0x20764316
  76         load_image u-boot_nand-ram256.bin 0x50008000 bin
  77         load_image u-boot_nand-ram256.bin 0x57E00000 bin
  78
  79         #Kick in
  80         reg pc 0x57E00000
  81         resume
  82 }
  83
  84 proc init_6410_flash {} {
  85         halt
  86         nand probe 0
  87         nand list
  88 }
  89
  90
  91 adapter speed 1000
  92 adapter srst delay 100
  93 jtag_ntrst_delay 100
  94 reset_config trst_and_srst
  95
  96 gdb_breakpoint_override hard
  97
  98 targets
  99 nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu
 100
 101 init
 102 echo " "
 103 echo " "
 104 echo "-------------------------------------------------------------------"
 105 echo "---- The following mini6410/tiny6410 functions are available:  ----"
 106 echo "----   init_6410 - initialize clock, timer, DRAM               ----"
 107 echo "----   init_6410_flash - initializes NAND flash support        ----"
 108 echo "----   install_6410_uboot - copies u-boot image into RAM and   ----"
 109 echo "----                        runs it                            ----"
 110 echo "-------------------------------------------------------------------"
 111 echo " "
 112 echo " "