tcl/board/imx53loco.cfg

   1 ##################################################################################
   2 # Author: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> #
   3 # Kiwigrid GmbH                                                                  #
   4 ##################################################################################
   5
   6 # The IMX53LOCO (QSB) board has a single IMX53 chip
   7 source [find target/imx53.cfg]
   8 # Helper for common memory read/modify/write procedures
   9 source [find mem_helper.tcl]
  10
  11 echo "iMX53 Loco board lodaded."
  12
  13 # Set reset type
  14 #reset_config srst_only
  15
  16 adapter_khz 3000
  17
  18 # Slow speed to be sure it will work
  19 jtag_rclk 1000
  20 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
  21
  22 #jtag_nsrst_delay 200
  23 #jtag_ntrst_delay 200
  24
  25 $_TARGETNAME configure -event "reset-assert" {
  26         echo "Reseting ...."
  27         #cortex_a dbginit
  28 }
  29
  30 $_TARGETNAME configure -event reset-init { loco_init }
  31
  32 global AIPS1_BASE_ADDR
  33 set AIPS1_BASE_ADDR     0x53F00000
  34 global AIPS2_BASE_ADDR
  35 set AIPS2_BASE_ADDR     0x63F00000
  36
  37 proc loco_init { } {
  38         echo "Reset-init..."
  39         ; # halt the CPU
  40         halt
  41
  42         echo "HW version [format %x [mrw 0x48]]"
  43
  44         dap apsel 1
  45         DCD
  46
  47         ; # ARM errata ID #468414
  48         set tR [arm mrc 15 0 1 0 1]
  49         arm mcr 15 0 1 0 1 [expr $tR | (1<<5)]  ; # enable L1NEON bit
  50
  51         init_l2cc
  52         init_aips
  53         init_clock
  54
  55         dap apsel 0
  56
  57         ; # Force ARM state
  58         ; #reg cpsr 0x000001D3
  59         arm core_state arm
  60
  61         jtag_rclk 3000
  62 #       adapter_khz 3000
  63 }
  64
  65
  66 # L2CC Cache setup/invalidation/disable
  67 proc init_l2cc { } {
  68         ; #/* explicitly disable L2 cache */
  69         ; #mrc 15, 0, r0, c1, c0, 1
  70         set tR [arm mrc 15 0 1 0 1]
  71         ; #bic r0, r0, #0x2
  72         ; #mcr 15, 0, r0, c1, c0, 1
  73         arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
  74
  75         ; #/* reconfigure L2 cache aux control reg */
  76         ; #mov r0, #0xC0                   /* tag RAM */
  77         ; #add r0, r0, #0x4                /* data RAM */
  78         ; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */
  79         ; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */
  80         ; #orr r0, r0, #(1 << 22)          /* disable write allocate */
  81
  82         ; #mcr 15, 1, r0, c9, c0, 2
  83         arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<22)]
  84 }
  85
  86
  87 # AIPS setup - Only setup MPROTx registers.
  88 # The PACR default values are good.
  89 proc init_aips { } {
  90         ; # Set all MPROTx to be non-bufferable, trusted for R/W,
  91         ; # not forced to user-mode.
  92         global AIPS1_BASE_ADDR
  93         global AIPS2_BASE_ADDR
  94         set VAL                 0x77777777
  95
  96 #       dap apsel 1
  97         mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
  98         mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
  99         mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
 100         mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
 101 #       dap apsel 0
 102 }
 103
 104
 105 proc init_clock { } {
 106         global AIPS1_BASE_ADDR
 107         global AIPS2_BASE_ADDR
 108         set CCM_BASE_ADDR       [expr $AIPS1_BASE_ADDR + 0x000D4000]
 109         set CLKCTL_CCSR         0x0C
 110         set CLKCTL_CBCDR        0x14
 111         set CLKCTL_CBCMR        0x18
 112         set PLL1_BASE_ADDR      [expr $AIPS2_BASE_ADDR + 0x00080000]
 113         set PLL2_BASE_ADDR      [expr $AIPS2_BASE_ADDR + 0x00084000]
 114         set PLL3_BASE_ADDR      [expr $AIPS2_BASE_ADDR + 0x00088000]
 115         set PLL4_BASE_ADDR      [expr $AIPS2_BASE_ADDR + 0x0008C000]
 116         set CLKCTL_CSCMR1       0x1C
 117         set CLKCTL_CDHIPR       0x48
 118         set PLATFORM_BASE_ADDR  [expr $AIPS2_BASE_ADDR + 0x000A0000]
 119         set CLKCTL_CSCDR1       0x24
 120         set CLKCTL_CCDR         0x04
 121
 122         ; # Switch ARM to step clock
 123         mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
 124
 125         return
 126         echo "not returned"
 127         setup_pll $PLL1_BASE_ADDR 800
 128         setup_pll $PLL3_BASE_ADDR 400
 129
 130         ; # Switch peripheral to PLL3
 131         mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
 132         mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
 133         while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
 134
 135         setup_pll $PLL2_BASE_ADDR 400
 136
 137         ; # Switch peripheral to PLL2
 138         mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
 139
 140         mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
 141
 142         ; # change uart clk parent to pll2
 143         mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
 144
 145         ; # make sure change is effective
 146         while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
 147
 148         setup_pll $PLL3_BASE_ADDR 216
 149
 150         setup_pll $PLL4_BASE_ADDR 455
 151
 152         ; # Set the platform clock dividers
 153         mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
 154
 155         mww [expr $CCM_BASE_ADDR + 0x10] 0
 156
 157         ; # Switch ARM back to PLL 1.
 158         mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
 159
 160         ; # make uart div=6
 161         mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
 162
 163         ; # Restore the default values in the Gate registers
 164         mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
 165         mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
 166         mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
 167         mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
 168         mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
 169         mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
 170         mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
 171         mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
 172
 173         mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
 174
 175         ; # for cko - for ARM div by 8
 176         mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
 177 }
 178
 179
 180 proc setup_pll { PLL_ADDR CLK } {
 181         set PLL_DP_CTL          0x00
 182         set PLL_DP_CONFIG       0x04
 183         set PLL_DP_OP           0x08
 184         set PLL_DP_HFS_OP       0x1C
 185         set PLL_DP_MFD          0x0C
 186         set PLL_DP_HFS_MFD      0x20
 187         set PLL_DP_MFN          0x10
 188         set PLL_DP_HFS_MFN      0x24
 189
 190         if {$CLK == 1000} {
 191                 set DP_OP       [expr (10 << 4) + ((1 - 1) << 0)]
 192                 set DP_MFD      [expr (12 - 1)]
 193                 set DP_MFN      5
 194         } elseif {$CLK == 850} {
 195                 set DP_OP       [expr (8 << 4) + ((1 - 1)  << 0)]
 196                 set DP_MFD      [expr (48 - 1)]
 197                 set DP_MFN      41
 198         } elseif {$CLK == 800} {
 199                 set DP_OP       [expr (8 << 4) + ((1 - 1)  << 0)]
 200                 set DP_MFD      [expr (3 - 1)]
 201                 set DP_MFN      1
 202         } elseif {$CLK == 700} {
 203                 set DP_OP       [expr (7 << 4) + ((1 - 1)  << 0)]
 204                 set DP_MFD      [expr (24 - 1)]
 205                 set DP_MFN      7
 206         } elseif {$CLK == 600} {
 207                 set DP_OP       [expr (6 << 4) + ((1 - 1)  << 0)]
 208                 set DP_MFD      [expr (4 - 1)]
 209                 set DP_MFN      1
 210         } elseif {$CLK == 665} {
 211                 set DP_OP       [expr (6 << 4) + ((1 - 1)  << 0)]
 212                 set DP_MFD      [expr (96 - 1)]
 213                 set DP_MFN      89
 214         } elseif {$CLK == 532} {
 215                 set DP_OP       [expr (5 << 4) + ((1 - 1)  << 0)]
 216                 set DP_MFD      [expr (24 - 1)]
 217                 set DP_MFN      13
 218         } elseif {$CLK == 455} {
 219                 set DP_OP       [expr (8 << 4) + ((2 - 1)  << 0)]
 220                 set DP_MFD      [expr (48 - 1)]
 221                 set DP_MFN      71
 222         } elseif {$CLK == 400} {
 223                 set DP_OP       [expr (8 << 4) + ((2 - 1)  << 0)]
 224                 set DP_MFD      [expr (3 - 1)]
 225                 set DP_MFN      1
 226         } elseif {$CLK == 216} {
 227                 set DP_OP       [expr (6 << 4) + ((3 - 1)  << 0)]
 228                 set DP_MFD      [expr (4 - 1)]
 229                 set DP_MFN      3
 230         } else {
 231                 error "Error (setup_dll): clock not found!"
 232         }
 233
 234         mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
 235         mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
 236
 237         mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
 238         mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
 239
 240         mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
 241         mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
 242
 243         mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
 244         mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
 245
 246         mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
 247         while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
 248 }
 249
 250
 251 proc CPU_2_BE_32 { L } {
 252         return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)]
 253 }
 254
 255
 256 # Device Configuration Data
 257 proc DCD { } {
 258 #       dap apsel 1
 259         mww 0x53FA8554 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
 260         mww 0x53FA8558 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
 261         mww 0x53FA8560 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
 262         mww 0x53FA8564 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT
 263         mww 0x53FA8568 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
 264         mww 0x53FA8570 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
 265         mww 0x53FA8574 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
 266         mww 0x53FA8578 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
 267         mww 0x53FA857c 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
 268         mww 0x53FA8580 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
 269         mww 0x53FA8584 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
 270         mww 0x53FA8588 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
 271         mww 0x53FA8590 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
 272         mww 0x53FA8594 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
 273         mww 0x53FA86f0 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_ADDDS
 274         mww 0x53FA86f4 0x00000000       ;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
 275         mww 0x53FA86fc 0x00000000       ;# IOMUXC_SW_PAD_CTL_GRP_DDRPKE
 276         mww 0x53FA8714 0x00000000       ;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode
 277         mww 0x53FA8718 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_B0DS
 278         mww 0x53FA871c 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_B1DS
 279         mww 0x53FA8720 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_CTLDS
 280         mww 0x53FA8724 0x04000000       ;# IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL0=
 281         mww 0x53FA8728 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_B2DS
 282         mww 0x53FA872c 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_B3DS
 283
 284         # Initialize DDR2 memory
 285         mww 0x63FD9088 0x35343535       ;# ESDCTL_RDDLCTL
 286         mww 0x63FD9090 0x4d444c44       ;# ESDCTL_WRDLCTL
 287         mww 0x63FD907c 0x01370138       ;# ESDCTL_DGCTRL0
 288         mww 0x63FD9080 0x013b013c       ;# ESDCTL_DGCTRL1
 289         mww 0x63FD9018 0x00011740       ;# ESDCTL_ESDMISC
 290         mww 0x63FD9000 0xc3190000       ;# ESDCTL_ESDCTL
 291         mww 0x63FD900c 0x9f5152e3       ;# ESDCTL_ESDCFG0
 292         mww 0x63FD9010 0xb68e8a63       ;# ESDCTL_ESDCFG1
 293         mww 0x63FD9014 0x01ff00db       ;# ESDCTL_ESDCFG2
 294         mww 0x63FD902c 0x000026d2       ;# ESDCTL_ESDRWD
 295         mww 0x63FD9030 0x009f0e21       ;# ESDCTL_ESDOR
 296         mww 0x63FD9008 0x12273030       ;# ESDCTL_ESDOTC
 297         mww 0x63FD9004 0x0002002d       ;# ESDCTL_ESDPDC
 298         mww 0x63FD901c 0x00008032       ;# ESDCTL_ESDSCR
 299         mww 0x63FD901c 0x00008033       ;# ESDCTL_ESDSCR
 300         mww 0x63FD901c 0x00028031       ;# ESDCTL_ESDSCR
 301         mww 0x63FD901c 0x052080b0       ;# ESDCTL_ESDSCR
 302         mww 0x63FD901c 0x04008040       ;# ESDCTL_ESDSCR
 303         mww 0x63FD901c 0x0000803a       ;# ESDCTL_ESDSCR
 304         mww 0x63FD901c 0x0000803b       ;# ESDCTL_ESDSCR
 305         mww 0x63FD901c 0x00028039       ;# ESDCTL_ESDSCR
 306         mww 0x63FD901c 0x05208138       ;# ESDCTL_ESDSCR
 307         mww 0x63FD901c 0x04008048       ;# ESDCTL_ESDSCR
 308         mww 0x63FD9020 0x00005800       ;# ESDCTL_ESDREF
 309         mww 0x63FD9040 0x04b80003       ;# ESDCTL_ZQHWCTRL
 310         mww 0x63FD9058 0x00022227       ;# ESDCTL_ODTCTRL
 311         mww 0x63FD901C 0x00000000       ;# ESDCTL_ESDSCR
 312 #       dap apsel 0
 313 }
 314
 315 # vim:filetype=tcl