tcl/board/imx35pdk.cfg

   1 # The IMX35PDK eval board has a single IMX35 chip
   2 source [find target/imx35.cfg]
   3 $_TARGETNAME configure -event reset-init { imx35pdk_init }
   4
   5 memwrite burst disable
   6 #arm11 no_increment enable
   7
   8
   9 global TARGETNAME
  10 set TARGETNAME $_TARGETNAME
  11
  12 # rewrite commands of the form below to arm11 mcr...
  13 #       Data.Set c15:0x042f %long 0x40000015
  14 proc setc15 {regs value} {
  15         global TARGETNAME
  16
  17         echo [format "set p15 0x%04x, 0x%08x" $regs $value]
  18
  19         arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
  20 }
  21
  22 proc imx35pdk_init { } {
  23
  24
  25         echo "Target Setup: initialize DRAM controller and peripherals"
  26
  27 #       Data.Set c15:0x01 %long 0x00050078
  28         setc15 0x01 0x00050078
  29
  30         echo "configuring CP15 for enabling the peripheral bus"
  31 #       Data.Set c15:0x042f %long 0x40000015
  32         setc15 0x042f 0x40000015
  33
  34         mww 0x43f00040 0x00000000
  35         mww 0x43f00044 0x00000000
  36         mww 0x43f00048 0x00000000
  37         mww 0x43f0004C 0x00000000
  38         mww 0x43f00050 0x00000000
  39         mww 0x43f00000 0x77777777
  40         mww 0x43f00004 0x77777777
  41         mww 0x53f00040 0x00000000
  42         mww 0x53f00044 0x00000000
  43         mww 0x53f00048 0x00000000
  44         mww 0x53f0004C 0x00000000
  45         mww 0x53f00050 0x00000000
  46         mww 0x53f00000 0x77777777
  47         mww 0x53f00004 0x77777777
  48
  49         # clock setup
  50         mww 0x53F80004 0x00821000 # first need to set IPU_HND_BYP
  51         mww 0x53F80004 0x00821000 #arm clock is 399Mhz and ahb clock is 133Mhz.
  52
  53         #=================================================
  54         # WEIM config
  55         #=================================================
  56         # CS0U
  57         mww 0xB8002000 0x0000CC03
  58         # CS0L
  59         mww 0xB8002004 0xA0330D01
  60         # CS0A
  61         mww 0xB8002008 0x00220800
  62         # CS5U
  63         mww 0xB8002050 0x0000dcf6
  64         # CS5L
  65         mww 0xB8002054 0x444a4541
  66         # CS5A
  67         mww 0xB8002058 0x44443302
  68
  69         # IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
  70         mww 0x43FAC368 0x00000006
  71         mww 0x43FAC36C 0x00000006
  72         mww 0x43FAC370 0x00000006
  73         mww 0x43FAC374 0x00000006
  74         mww 0x43FAC378 0x00000006
  75         mww 0x43FAC37C 0x00000006
  76         mww 0x43FAC380 0x00000006
  77         mww 0x43FAC384 0x00000006
  78         mww 0x43FAC388 0x00000006
  79         mww 0x43FAC38C 0x00000006
  80         mww 0x43FAC390 0x00000006
  81         mww 0x43FAC394 0x00000006
  82         mww 0x43FAC398 0x00000006
  83         mww 0x43FAC39C 0x00000006
  84         mww 0x43FAC3A0 0x00000006
  85         mww 0x43FAC3A4 0x00000006
  86         mww 0x43FAC3A8 0x00000006
  87         mww 0x43FAC3AC 0x00000006
  88         mww 0x43FAC3B0 0x00000006
  89         mww 0x43FAC3B4 0x00000006
  90         mww 0x43FAC3B8 0x00000006
  91         mww 0x43FAC3BC 0x00000006
  92         mww 0x43FAC3C0 0x00000006
  93         mww 0x43FAC3C4 0x00000006
  94         mww 0x43FAC3C8 0x00000006
  95         mww 0x43FAC3CC 0x00000006
  96         mww 0x43FAC3D0 0x00000006
  97         mww 0x43FAC3D4 0x00000006
  98         mww 0x43FAC3D8 0x00000006
  99
 100         # DDR data bus SD 0 through 31
 101         mww 0x43FAC3DC 0x00000082
 102         mww 0x43FAC3E0 0x00000082
 103         mww 0x43FAC3E4 0x00000082
 104         mww 0x43FAC3E8 0x00000082
 105         mww 0x43FAC3EC 0x00000082
 106         mww 0x43FAC3F0 0x00000082
 107         mww 0x43FAC3F4 0x00000082
 108         mww 0x43FAC3F8 0x00000082
 109         mww 0x43FAC3FC 0x00000082
 110         mww 0x43FAC400 0x00000082
 111         mww 0x43FAC404 0x00000082
 112         mww 0x43FAC408 0x00000082
 113         mww 0x43FAC40C 0x00000082
 114         mww 0x43FAC410 0x00000082
 115         mww 0x43FAC414 0x00000082
 116         mww 0x43FAC418 0x00000082
 117         mww 0x43FAC41c 0x00000082
 118         mww 0x43FAC420 0x00000082
 119         mww 0x43FAC424 0x00000082
 120         mww 0x43FAC428 0x00000082
 121         mww 0x43FAC42c 0x00000082
 122         mww 0x43FAC430 0x00000082
 123         mww 0x43FAC434 0x00000082
 124         mww 0x43FAC438 0x00000082
 125         mww 0x43FAC43c 0x00000082
 126         mww 0x43FAC440 0x00000082
 127         mww 0x43FAC444 0x00000082
 128         mww 0x43FAC448 0x00000082
 129         mww 0x43FAC44c 0x00000082
 130         mww 0x43FAC450 0x00000082
 131         mww 0x43FAC454 0x00000082
 132         mww 0x43FAC458 0x00000082
 133
 134         # DQM setup
 135         mww 0x43FAC45c 0x00000082
 136         mww 0x43FAC460 0x00000082
 137         mww 0x43FAC464 0x00000082
 138         mww 0x43FAC468 0x00000082
 139
 140         mww 0x43FAC46c 0x00000006
 141         mww 0x43FAC470 0x00000006
 142         mww 0x43FAC474 0x00000006
 143         mww 0x43FAC478 0x00000006
 144         mww 0x43FAC47c 0x00000006
 145         mww 0x43FAC480 0x00000006       # CSD0
 146         mww 0x43FAC484 0x00000006       # CSD1
 147         mww 0x43FAC488 0x00000006
 148         mww 0x43FAC48c 0x00000006
 149         mww 0x43FAC490 0x00000006
 150         mww 0x43FAC494 0x00000006
 151         mww 0x43FAC498 0x00000006
 152         mww 0x43FAC49c 0x00000006
 153         mww 0x43FAC4A0 0x00000006
 154         mww 0x43FAC4A4 0x00000006       # RAS
 155         mww 0x43FAC4A8 0x00000006       # CAS
 156         mww 0x43FAC4Ac 0x00000006       # SDWE
 157         mww 0x43FAC4B0 0x00000006       # SDCKE0
 158         mww 0x43FAC4B4 0x00000006  # SDCKE1
 159         mww 0x43FAC4B8 0x00000002  # SDCLK
 160
 161         # SDQS0 through SDQS3
 162         mww 0x43FAC4Bc 0x00000082
 163         mww 0x43FAC4C0 0x00000082
 164         mww 0x43FAC4C4 0x00000082
 165         mww 0x43FAC4C8 0x00000082
 166
 167
 168         # *==================================================
 169         #  Initialization script for 32 bit DDR2 on RINGO 3DS
 170         # *==================================================
 171
 172         #--------------------------------------------
 173         # Init CCM
 174         #--------------------------------------------
 175         mww 0x53F80028 0x7D000028
 176
 177         #--------------------------------------------
 178         # Init IOMUX for JTAG
 179         #--------------------------------------------
 180         mww 0x43FAC5EC 0x000000C3
 181         mww 0x43FAC5F0 0x000000C3
 182         mww 0x43FAC5F4 0x000000F3
 183         mww 0x43FAC5F8 0x000000F3
 184         mww 0x43FAC5FC 0x000000F3
 185         mww 0x43FAC600 0x000000F3
 186         mww 0x43FAC604 0x000000F3
 187
 188
 189         # ESD_MISC : enable DDR2
 190         mww 0xB8001010 0x00000304
 191
 192         #--------------------------------------------
 193         # Init 32-bit DDR2 memeory on CSD0
 194         # COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
 195         #--------------------------------------------
 196
 197         # ESD_ESDCFG0 : set timing paramters
 198         mww 0xB8001004 0x007ffC2f
 199
 200         # ESD_ESDCTL0 : select Prechare-All mode
 201         mww 0xB8001000 0x92220000
 202         # DDR2 : Prechare-All
 203         mww 0x80000400 0x12345678
 204
 205         # ESD_ESDCTL0 : select Load-Mode-Register mode
 206         mww 0xB8001000 0xB2220000
 207         # DDR2 : Load reg EMR2
 208         mwb 0x84000000 0xda
 209         # DDR2 : Load reg EMR3
 210         mwb 0x86000000 0xda
 211         # DDR2 : Load reg EMR1 -- enable DLL
 212         mwb 0x82000400 0xda
 213         # DDR2 : Load reg MR -- reset DLL
 214         mwb 0x80000333 0xda
 215
 216         # ESD_ESDCTL0 : select Prechare-All mode
 217         mww 0xB8001000 0x92220000
 218         # DDR2 : Prechare-All
 219         mwb 0x80000400 0x12345678
 220
 221         # ESD_ESDCTL0 : select Manual-Refresh mode
 222         mww 0xB8001000 0xA2220000
 223         # DDR2 : Manual-Refresh 2 times
 224         mww 0x80000000 0x87654321
 225         mww 0x80000000 0x87654321
 226
 227         # ESD_ESDCTL0 : select Load-Mode-Register mode
 228         mww 0xB8001000 0xB2220000
 229         # DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
 230         mwb 0x80000233 0xda
 231         # DDR2 : Load reg EMR1 -- OCD default
 232         mwb 0x82000780 0xda
 233         # DDR2 : Load reg EMR1 -- OCD exit
 234         mwb 0x82000400 0xda     # ODT disabled
 235
 236         # ESD_ESDCTL0 : select normal-operation mode
 237         # DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
 238         # disable PWT & PRCT
 239         # disable Auto-Refresh
 240         mww 0xB8001000 0x82220080
 241
 242         ## ESD_ESDCTL0 : enable Auto-Refresh
 243         mww 0xB8001000 0x82228080
 244         ## ESD_ESDCTL1 : enable Auto-Refresh
 245         mww 0xB8001008 0x00002000
 246
 247
 248         #***********************************************
 249         # Adjust the ESDCDLY5 register
 250         #***********************************************
 251         # Vary DQS_ABS_OFFSET5 for writes
 252         mww 0xB8001020 0x00F48000       # this is the default value
 253         mww 0xB8001024 0x00F48000       # this is the default value
 254         mww 0xB8001028 0x00F48000       # this is the default value
 255         mww 0xB800102c 0x00F48000       # this is the default value
 256
 257
 258         #Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
 259         mww 0xB8001010 0x00000384
 260         # wait a while
 261         sleep 1000
 262         # now clear the force measurement bit
 263         mww 0xB8001010 0x00000304
 264
 265         # dummy write to DDR memory to set DQS low
 266         mww 0x80000000 0x00000000
 267
 268         mww 0x30000100 0x0
 269         mww 0x30000104 0x31024
 270
 271
 272 }