tcl/board/imx35pdk.cfg

   1 # The IMX35PDK eval board has a single IMX35 chip
   2 source [find target/imx35.cfg]
   3 $_TARGETNAME configure -event reset-init { imx35pdk_init }
   4
   5 memwrite burst disable
   6 #arm11 no_increment enable
   7
   8
   9 global TARGETNAME
  10 set TARGETNAME $_TARGETNAME
  11
  12 # rewrite commands of the form below to arm11 mcr...
  13 #       Data.Set c15:0x042f %long 0x40000015
  14 proc setc15 {regs value} {
  15         global TARGETNAME
  16
  17         echo [format "set p15 0x%04x, 0x%08x" $regs $value]
  18
  19         arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
  20 }
  21
  22 proc imx35pdk_init { } {
  23
  24         # this reset script comes from the Freescale PDK
  25         #
  26         # http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK
  27
  28         echo "Target Setup: initialize DRAM controller and peripherals"
  29
  30 #       Data.Set c15:0x01 %long 0x00050078
  31         setc15 0x01 0x00050078
  32
  33         echo "configuring CP15 for enabling the peripheral bus"
  34 #       Data.Set c15:0x042f %long 0x40000015
  35         setc15 0x042f 0x40000015
  36
  37         mww 0x43f00040 0x00000000
  38         mww 0x43f00044 0x00000000
  39         mww 0x43f00048 0x00000000
  40         mww 0x43f0004C 0x00000000
  41         mww 0x43f00050 0x00000000
  42         mww 0x43f00000 0x77777777
  43         mww 0x43f00004 0x77777777
  44         mww 0x53f00040 0x00000000
  45         mww 0x53f00044 0x00000000
  46         mww 0x53f00048 0x00000000
  47         mww 0x53f0004C 0x00000000
  48         mww 0x53f00050 0x00000000
  49         mww 0x53f00000 0x77777777
  50         mww 0x53f00004 0x77777777
  51
  52         # clock setup
  53         mww 0x53F80004 0x00821000 # first need to set IPU_HND_BYP
  54         mww 0x53F80004 0x00821000 #arm clock is 399Mhz and ahb clock is 133Mhz.
  55
  56         #=================================================
  57         # WEIM config
  58         #=================================================
  59         # CS0U
  60         mww 0xB8002000 0x0000CC03
  61         # CS0L
  62         mww 0xB8002004 0xA0330D01
  63         # CS0A
  64         mww 0xB8002008 0x00220800
  65         # CS5U
  66         mww 0xB8002050 0x0000dcf6
  67         # CS5L
  68         mww 0xB8002054 0x444a4541
  69         # CS5A
  70         mww 0xB8002058 0x44443302
  71
  72         # IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
  73         mww 0x43FAC368 0x00000006
  74         mww 0x43FAC36C 0x00000006
  75         mww 0x43FAC370 0x00000006
  76         mww 0x43FAC374 0x00000006
  77         mww 0x43FAC378 0x00000006
  78         mww 0x43FAC37C 0x00000006
  79         mww 0x43FAC380 0x00000006
  80         mww 0x43FAC384 0x00000006
  81         mww 0x43FAC388 0x00000006
  82         mww 0x43FAC38C 0x00000006
  83         mww 0x43FAC390 0x00000006
  84         mww 0x43FAC394 0x00000006
  85         mww 0x43FAC398 0x00000006
  86         mww 0x43FAC39C 0x00000006
  87         mww 0x43FAC3A0 0x00000006
  88         mww 0x43FAC3A4 0x00000006
  89         mww 0x43FAC3A8 0x00000006
  90         mww 0x43FAC3AC 0x00000006
  91         mww 0x43FAC3B0 0x00000006
  92         mww 0x43FAC3B4 0x00000006
  93         mww 0x43FAC3B8 0x00000006
  94         mww 0x43FAC3BC 0x00000006
  95         mww 0x43FAC3C0 0x00000006
  96         mww 0x43FAC3C4 0x00000006
  97         mww 0x43FAC3C8 0x00000006
  98         mww 0x43FAC3CC 0x00000006
  99         mww 0x43FAC3D0 0x00000006
 100         mww 0x43FAC3D4 0x00000006
 101         mww 0x43FAC3D8 0x00000006
 102
 103         # DDR data bus SD 0 through 31
 104         mww 0x43FAC3DC 0x00000082
 105         mww 0x43FAC3E0 0x00000082
 106         mww 0x43FAC3E4 0x00000082
 107         mww 0x43FAC3E8 0x00000082
 108         mww 0x43FAC3EC 0x00000082
 109         mww 0x43FAC3F0 0x00000082
 110         mww 0x43FAC3F4 0x00000082
 111         mww 0x43FAC3F8 0x00000082
 112         mww 0x43FAC3FC 0x00000082
 113         mww 0x43FAC400 0x00000082
 114         mww 0x43FAC404 0x00000082
 115         mww 0x43FAC408 0x00000082
 116         mww 0x43FAC40C 0x00000082
 117         mww 0x43FAC410 0x00000082
 118         mww 0x43FAC414 0x00000082
 119         mww 0x43FAC418 0x00000082
 120         mww 0x43FAC41c 0x00000082
 121         mww 0x43FAC420 0x00000082
 122         mww 0x43FAC424 0x00000082
 123         mww 0x43FAC428 0x00000082
 124         mww 0x43FAC42c 0x00000082
 125         mww 0x43FAC430 0x00000082
 126         mww 0x43FAC434 0x00000082
 127         mww 0x43FAC438 0x00000082
 128         mww 0x43FAC43c 0x00000082
 129         mww 0x43FAC440 0x00000082
 130         mww 0x43FAC444 0x00000082
 131         mww 0x43FAC448 0x00000082
 132         mww 0x43FAC44c 0x00000082
 133         mww 0x43FAC450 0x00000082
 134         mww 0x43FAC454 0x00000082
 135         mww 0x43FAC458 0x00000082
 136
 137         # DQM setup
 138         mww 0x43FAC45c 0x00000082
 139         mww 0x43FAC460 0x00000082
 140         mww 0x43FAC464 0x00000082
 141         mww 0x43FAC468 0x00000082
 142
 143         mww 0x43FAC46c 0x00000006
 144         mww 0x43FAC470 0x00000006
 145         mww 0x43FAC474 0x00000006
 146         mww 0x43FAC478 0x00000006
 147         mww 0x43FAC47c 0x00000006
 148         mww 0x43FAC480 0x00000006       # CSD0
 149         mww 0x43FAC484 0x00000006       # CSD1
 150         mww 0x43FAC488 0x00000006
 151         mww 0x43FAC48c 0x00000006
 152         mww 0x43FAC490 0x00000006
 153         mww 0x43FAC494 0x00000006
 154         mww 0x43FAC498 0x00000006
 155         mww 0x43FAC49c 0x00000006
 156         mww 0x43FAC4A0 0x00000006
 157         mww 0x43FAC4A4 0x00000006       # RAS
 158         mww 0x43FAC4A8 0x00000006       # CAS
 159         mww 0x43FAC4Ac 0x00000006       # SDWE
 160         mww 0x43FAC4B0 0x00000006       # SDCKE0
 161         mww 0x43FAC4B4 0x00000006  # SDCKE1
 162         mww 0x43FAC4B8 0x00000002  # SDCLK
 163
 164         # SDQS0 through SDQS3
 165         mww 0x43FAC4Bc 0x00000082
 166         mww 0x43FAC4C0 0x00000082
 167         mww 0x43FAC4C4 0x00000082
 168         mww 0x43FAC4C8 0x00000082
 169
 170
 171         # *==================================================
 172         #  Initialization script for 32 bit DDR2 on RINGO 3DS
 173         # *==================================================
 174
 175         #--------------------------------------------
 176         # Init CCM
 177         #--------------------------------------------
 178         mww 0x53F80028 0x7D000028
 179
 180         #--------------------------------------------
 181         # Init IOMUX for JTAG
 182         #--------------------------------------------
 183         mww 0x43FAC5EC 0x000000C3
 184         mww 0x43FAC5F0 0x000000C3
 185         mww 0x43FAC5F4 0x000000F3
 186         mww 0x43FAC5F8 0x000000F3
 187         mww 0x43FAC5FC 0x000000F3
 188         mww 0x43FAC600 0x000000F3
 189         mww 0x43FAC604 0x000000F3
 190
 191
 192         # ESD_MISC : enable DDR2
 193         mww 0xB8001010 0x00000304
 194
 195         #--------------------------------------------
 196         # Init 32-bit DDR2 memeory on CSD0
 197         # COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
 198         #--------------------------------------------
 199
 200         # ESD_ESDCFG0 : set timing paramters
 201         mww 0xB8001004 0x007ffC2f
 202
 203         # ESD_ESDCTL0 : select Prechare-All mode
 204         mww 0xB8001000 0x92220000
 205         # DDR2 : Prechare-All
 206         mww 0x80000400 0x12345678
 207
 208         # ESD_ESDCTL0 : select Load-Mode-Register mode
 209         mww 0xB8001000 0xB2220000
 210         # DDR2 : Load reg EMR2
 211         mwb 0x84000000 0xda
 212         # DDR2 : Load reg EMR3
 213         mwb 0x86000000 0xda
 214         # DDR2 : Load reg EMR1 -- enable DLL
 215         mwb 0x82000400 0xda
 216         # DDR2 : Load reg MR -- reset DLL
 217         mwb 0x80000333 0xda
 218
 219         # ESD_ESDCTL0 : select Prechare-All mode
 220         mww 0xB8001000 0x92220000
 221         # DDR2 : Prechare-All
 222         mwb 0x80000400 0x12345678
 223
 224         # ESD_ESDCTL0 : select Manual-Refresh mode
 225         mww 0xB8001000 0xA2220000
 226         # DDR2 : Manual-Refresh 2 times
 227         mww 0x80000000 0x87654321
 228         mww 0x80000000 0x87654321
 229
 230         # ESD_ESDCTL0 : select Load-Mode-Register mode
 231         mww 0xB8001000 0xB2220000
 232         # DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
 233         mwb 0x80000233 0xda
 234         # DDR2 : Load reg EMR1 -- OCD default
 235         mwb 0x82000780 0xda
 236         # DDR2 : Load reg EMR1 -- OCD exit
 237         mwb 0x82000400 0xda     # ODT disabled
 238
 239         # ESD_ESDCTL0 : select normal-operation mode
 240         # DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
 241         # disable PWT & PRCT
 242         # disable Auto-Refresh
 243         mww 0xB8001000 0x82220080
 244
 245         ## ESD_ESDCTL0 : enable Auto-Refresh
 246         mww 0xB8001000 0x82228080
 247         ## ESD_ESDCTL1 : enable Auto-Refresh
 248         mww 0xB8001008 0x00002000
 249
 250
 251         #***********************************************
 252         # Adjust the ESDCDLY5 register
 253         #***********************************************
 254         # Vary DQS_ABS_OFFSET5 for writes
 255         mww 0xB8001020 0x00F48000       # this is the default value
 256         mww 0xB8001024 0x00F48000       # this is the default value
 257         mww 0xB8001028 0x00F48000       # this is the default value
 258         mww 0xB800102c 0x00F48000       # this is the default value
 259
 260
 261         #Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
 262         mww 0xB8001010 0x00000384
 263         # wait a while
 264         sleep 1000
 265         # now clear the force measurement bit
 266         mww 0xB8001010 0x00000304
 267
 268         # dummy write to DDR memory to set DQS low
 269         mww 0x80000000 0x00000000
 270
 271         mww 0x30000100 0x0
 272         mww 0x30000104 0x31024
 273
 274
 275 }