1 # The IMX31PDK eval board has a single IMX31 chip
2 source [find target/imx31.cfg]
3 $_TARGETNAME configure -event reset-init { imx31pdk_init }
5 proc imx31pdk_init { } {
6 # This setup puts RAM at 0x80000000
8 # ========================================
10 # ========================================
12 mww 0x53F80000 0x074B0B7D
16 # ========================================
17 # 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
18 # ========================================
19 mww 0x53F80004 0xFF871D50
20 mww 0x53F80010 0x00271C1B
22 # ========================================
23 # Configure CPLD on CS5
24 # ========================================
25 mww 0xb8002050 0x0000DCF6
26 mww 0xb8002054 0x444A4541
27 mww 0xb8002058 0x44443302
29 # ========================================
31 # ========================================
34 # ========================================
36 # ========================================
39 # ========================================
41 # ========================================
44 # ========================================
46 # ========================================
49 # ========================================
51 # ========================================
54 # ========================================
55 # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
56 # ========================================
80 # ========================================
81 # Initialization script for 32 bit DDR on MX31 PDK
82 # ========================================
83 mww 0xB8001010 0x00000004
84 mww 0xB8001004 0x006ac73a
85 mww 0xB8001000 0x92100000
86 mww 0x80000f00 0x12344321
87 mww 0xB8001000 0xa2100000
88 mww 0x80000000 0x12344321
89 mww 0x80000000 0x12344321
90 mww 0xB8001000 0xb2100000
93 mww 0xB8001000 0x82226080
94 mww 0x80000000 0xDEADBEEF
95 mww 0xB8001010 0x0000000c
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