1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # Hitex eval board for LPC2929/LPC2939
4 # http://www.hitex.com/
6 # Delays on reset lines
10 # Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
11 # Adaptive clocking through RTCK is not supported.
14 # Target device: LPC29xx with ETB
15 # The following variables are used by the LPC2900 script:
16 # HAS_ETB Must be set to 1. The CPU on this board has ETB.
17 # FLASH_CLOCK CPU frequency at the time of flash programming (in kHz)
19 set FLASH_CLOCK 112000
20 source [find target/lpc2900.cfg]
22 # A working area will help speeding the flash programming
23 #$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 -work-area-backup 0
24 $_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-area-backup 0
27 $_TARGETNAME configure -event reset-start {
28 # Back to the slow JTAG clock
32 # External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
33 set _FLASHNAME $_CHIPNAME.extflash
34 flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
37 $_TARGETNAME configure -event reset-init {
39 mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not cached
42 mww 0xFFFF8020 0x00000001 ;# XTAL_OSC_CONTROL: enable, 1-20 MHz
43 mww 0xFFFF8070 0x01000000 ;# SYS_CLK_CONF: Crystal
44 mww 0xFFFF8028 0x00000005 ;# PLL: (power down)
45 mww 0xFFFF8028 0x01060004 ;# PLL: M=7, 2P=2 (power up)
46 # --> f=112 MHz, fcco=224 MHz
48 mww 0xFFFF8070 0x02000000 ;# SYS_CLK_CONF: PLL
53 # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
54 mww 0xE0001138 0x0000001F ;# P1.14 = D0
55 mww 0xE000113C 0x0000001F ;# P1.15 = D1
56 mww 0xE0001140 0x0000001F ;# P1.16 = D2
57 mww 0xE0001144 0x0000001F ;# P1.17 = D3
58 mww 0xE0001148 0x0000001F ;# P1.18 = D4
59 mww 0xE000114C 0x0000001F ;# P1.19 = D5
60 mww 0xE0001150 0x0000001F ;# P1.20 = D6
61 mww 0xE0001154 0x0000001F ;# P1.21 = D7
62 mww 0xE0001200 0x0000001F ;# P2.0 = D8
63 mww 0xE0001204 0x0000001F ;# P2.1 = D9
64 mww 0xE0001208 0x0000001F ;# P2.2 = D10
65 mww 0xE000120C 0x0000001F ;# P2.3 = D11
66 mww 0xE0001210 0x0000001F ;# P2.4 = D12
67 mww 0xE0001214 0x0000001F ;# P2.5 = D13
68 mww 0xE0001218 0x0000001F ;# P2.6 = D14
69 mww 0xE000121C 0x0000001F ;# P2.7 = D15
70 mww 0xE0001104 0x00000007 ;# P1.1 = A1
71 mww 0xE0001108 0x00000007 ;# P1.2 = A2
72 mww 0xE000110C 0x00000007 ;# P1.3 = A3
73 mww 0xE0001110 0x00000007 ;# P1.4 = A4
74 mww 0xE0001114 0x00000007 ;# P1.5 = A5
75 mww 0xE0001118 0x00000007 ;# P1.6 = A6
76 mww 0xE000111C 0x00000007 ;# P1.7 = A7
77 mww 0xE0001028 0x00000007 ;# P0.10 = A8
78 mww 0xE000102C 0x00000007 ;# P0.11 = A9
79 mww 0xE0001030 0x00000007 ;# P0.12 = A10
80 mww 0xE0001034 0x00000007 ;# P0.13 = A11
81 mww 0xE0001038 0x00000007 ;# P0.14 = A12
82 mww 0xE000103C 0x00000007 ;# P0.15 = A13
83 mww 0xE0001048 0x00000007 ;# P0.18 = A14
84 mww 0xE000104C 0x00000007 ;# P0.19 = A15
85 mww 0xE0001050 0x00000007 ;# P0.20 = A16
86 mww 0xE0001054 0x00000007 ;# P0.21 = A17
87 mww 0xE0001058 0x00000007 ;# P0.22 = A18
88 mww 0xE000105C 0x00000007 ;# P0.23 = A19
89 mww 0xE0001238 0x00000007 ;# P2.14 = BLS0
90 mww 0xE000123C 0x00000007 ;# P2.15 = BLS1
91 mww 0xE0001300 0x00000007 ;# P3.0 = CS6
92 mww 0xE0001304 0x00000007 ;# P3.1 = CS7
93 mww 0xE0001130 0x00000007 ;# P1.12 = OE_N
94 mww 0xE0001134 0x00000007 ;# P1.13 = WE_N
95 mww 0x600000BC 0x00000041 ;# Bank6 16-bit mode, RBLE=1
96 mww 0x600000B4 0x00000000 ;# Bank6 WSTOEN=0
97 mww 0x600000AC 0x00000005 ;# Bank6 WST1=5
98 mww 0x600000B8 0x00000001 ;# Bank6 WSTWEN=1
99 mww 0x600000B0 0x00000006 ;# Bank6 WST2=6
100 mww 0x600000A8 0x00000002 ;# Bank6 IDCY=2
101 mww 0x600000D8 0x00000041 ;# Bank7 16-bit mode, RBLE=1
102 mww 0x600000D0 0x00000000 ;# Bank7 WSTOEN=0
103 mww 0x600000C8 0x0000000A ;# Bank7 WST1=10
104 mww 0x600000D4 0x00000001 ;# Bank7 WSTWEN=1
105 mww 0x600000CC 0x0000000C ;# Bank7 WST2=8
106 mww 0x600000C4 0x00000002 ;# Bank7 IDCY=2