tcl/board/hitex_lpc2929.cfg

   1 # Hitex eval board for LPC2929/LPC2939
   2 # http://www.hitex.com/
   3
   4 # Delays on reset lines
   5 adapter srst delay 50
   6 jtag_ntrst_delay 1
   7
   8 # Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
   9 # Adaptive clocking through RTCK is not supported.
  10 adapter speed 2000
  11
  12 # Target device: LPC29xx with ETB
  13 # The following variables are used by the LPC2900 script:
  14 #   HAS_ETB             Must be set to 1. The CPU on this board has ETB.
  15 #   FLASH_CLOCK         CPU frequency at the time of flash programming (in kHz)
  16 set HAS_ETB             1
  17 set FLASH_CLOCK         112000
  18 source [find target/lpc2900.cfg]
  19
  20 # A working area will help speeding the flash programming
  21 #$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 -work-area-backup 0
  22 $_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-area-backup 0
  23
  24 # Event handlers
  25 $_TARGETNAME configure -event reset-start {
  26   # Back to the slow JTAG clock
  27   adapter speed 2000
  28 }
  29
  30 # External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
  31 set _FLASHNAME $_CHIPNAME.extflash
  32 flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
  33
  34
  35 $_TARGETNAME configure -event reset-init {
  36   # Flash
  37   mww 0x20200010 0x00000007     ;# FBWST: 7 wait states, not chached
  38
  39   # Use PLL
  40   mww 0xFFFF8020 0x00000001     ;# XTAL_OSC_CONTROL: enable, 1-20 MHz
  41   mww 0xFFFF8070 0x01000000     ;# SYS_CLK_CONF: Crystal
  42   mww 0xFFFF8028 0x00000005     ;# PLL: (power down)
  43   mww 0xFFFF8028 0x01060004     ;# PLL: M=7, 2P=2 (power up)
  44                                  # --> f=112 MHz, fcco=224 MHz
  45   sleep 100
  46   mww 0xFFFF8070 0x02000000     ;# SYS_CLK_CONF: PLL
  47
  48   # Increase JTAG speed
  49   adapter speed 6000
  50
  51   # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
  52   mww 0xE0001138 0x0000001F     ;# P1.14 = D0
  53   mww 0xE000113C 0x0000001F     ;# P1.15 = D1
  54   mww 0xE0001140 0x0000001F     ;# P1.16 = D2
  55   mww 0xE0001144 0x0000001F     ;# P1.17 = D3
  56   mww 0xE0001148 0x0000001F     ;# P1.18 = D4
  57   mww 0xE000114C 0x0000001F     ;# P1.19 = D5
  58   mww 0xE0001150 0x0000001F     ;# P1.20 = D6
  59   mww 0xE0001154 0x0000001F     ;# P1.21 = D7
  60   mww 0xE0001200 0x0000001F     ;# P2.0  = D8
  61   mww 0xE0001204 0x0000001F     ;# P2.1  = D9
  62   mww 0xE0001208 0x0000001F     ;# P2.2  = D10
  63   mww 0xE000120C 0x0000001F     ;# P2.3  = D11
  64   mww 0xE0001210 0x0000001F     ;# P2.4  = D12
  65   mww 0xE0001214 0x0000001F     ;# P2.5  = D13
  66   mww 0xE0001218 0x0000001F     ;# P2.6  = D14
  67   mww 0xE000121C 0x0000001F     ;# P2.7  = D15
  68   mww 0xE0001104 0x00000007     ;# P1.1  = A1
  69   mww 0xE0001108 0x00000007     ;# P1.2  = A2
  70   mww 0xE000110C 0x00000007     ;# P1.3  = A3
  71   mww 0xE0001110 0x00000007     ;# P1.4  = A4
  72   mww 0xE0001114 0x00000007     ;# P1.5  = A5
  73   mww 0xE0001118 0x00000007     ;# P1.6  = A6
  74   mww 0xE000111C 0x00000007     ;# P1.7  = A7
  75   mww 0xE0001028 0x00000007     ;# P0.10 = A8
  76   mww 0xE000102C 0x00000007     ;# P0.11 = A9
  77   mww 0xE0001030 0x00000007     ;# P0.12 = A10
  78   mww 0xE0001034 0x00000007     ;# P0.13 = A11
  79   mww 0xE0001038 0x00000007     ;# P0.14 = A12
  80   mww 0xE000103C 0x00000007     ;# P0.15 = A13
  81   mww 0xE0001048 0x00000007     ;# P0.18 = A14
  82   mww 0xE000104C 0x00000007     ;# P0.19 = A15
  83   mww 0xE0001050 0x00000007     ;# P0.20 = A16
  84   mww 0xE0001054 0x00000007     ;# P0.21 = A17
  85   mww 0xE0001058 0x00000007     ;# P0.22 = A18
  86   mww 0xE000105C 0x00000007     ;# P0.23 = A19
  87   mww 0xE0001238 0x00000007     ;# P2.14 = BLS0
  88   mww 0xE000123C 0x00000007     ;# P2.15 = BLS1
  89   mww 0xE0001300 0x00000007     ;# P3.0  = CS6
  90   mww 0xE0001304 0x00000007     ;# P3.1  = CS7
  91   mww 0xE0001130 0x00000007     ;# P1.12 = OE_N
  92   mww 0xE0001134 0x00000007     ;# P1.13 = WE_N
  93   mww 0x600000BC 0x00000041     ;# Bank6 16-bit mode, RBLE=1
  94   mww 0x600000B4 0x00000000     ;# Bank6 WSTOEN=0
  95   mww 0x600000AC 0x00000005     ;# Bank6 WST1=5
  96   mww 0x600000B8 0x00000001     ;# Bank6 WSTWEN=1
  97   mww 0x600000B0 0x00000006     ;# Bank6 WST2=6
  98   mww 0x600000A8 0x00000002     ;# Bank6 IDCY=2
  99   mww 0x600000D8 0x00000041     ;# Bank7 16-bit mode, RBLE=1
 100   mww 0x600000D0 0x00000000     ;# Bank7 WSTOEN=0
 101   mww 0x600000C8 0x0000000A     ;# Bank7 WST1=10
 102   mww 0x600000D4 0x00000001     ;# Bank7 WSTWEN=1
 103   mww 0x600000CC 0x0000000C     ;# Bank7 WST2=8
 104   mww 0x600000C4 0x00000002     ;# Bank7 IDCY=2
 105 }
 106