tcl/board/glyn_tonga2.cfg

   1 #
   2 # Glyn Tonga2 SO-DIMM CPU module (Toshiba TMPA900CMXBG, ARM9)
   3 #
   4 # http://toshiba-mikrocontroller.de/sites/TMPA900CPUBOARDStarter.htm
   5 #
   6 # Hardware on the S0-DIMM module:
   7 #   - Toshiba TMPA900CMXBG (ARM9, ARM926EJ-S, max. 200MHz)
   8 #   - DDR SDRAM: Hynix H5MS5162DFR-J3M (64Mbyte, x16, 1.8V, 166/83MHz at CL3/2)
   9 #   - NAND flash: Samsung K9F2G08U0B-PIB0 (256M x 8 Bit, 3.3V)
  10 #   - Ethernet: SMSC LAN9221I-ABZJ (10/100Mbit, Non-PCI, 16 bit interface)
  11 #
  12
  13 source [find target/tmpa900.cfg]
  14
  15 ########################
  16 # Target configuration #
  17 ########################
  18
  19 $_TARGETNAME configure -event reset-init { tonga2_init }
  20
  21 proc tonga2_init { } {
  22
  23         ######################
  24         # PLL initialization #
  25         ######################
  26
  27         # Clock overview (see datasheet chapter 3.5.2, page 57):
  28         #   - fs: Low-frequency oscillator
  29         #   - fOSCH: High-frequency oscillator (24MHz on this board)
  30         #   - fPLL = fOSCH * multiplier (where multiplier can be 6 or 8)
  31         #   - fFCLK = fPLL / gear (where gear can be 1/2/4/8)
  32         #   - fHCLK is always fFCLK/2. fPCLK is also fFCLK/2.
  33         #
  34         # We select multiplier = 8 and gear = 1, so
  35         #   fFCLK = fOSCH * 8 / 1 = 192MHz.
  36
  37         # SYSCR3 (System Control Register 3): Disable and configure PLL.
  38         #   - PLL operation control: off
  39         #   - PLL constant value setting 1: always 0, as per datasheet
  40         #   - PLL constant value setting 2: x8 (multiplier = 8)
  41         mww 0xf005000c 0x00000007
  42
  43         # SYSCR4 (System Control Register 4): Configure PLL.
  44         #   - PLL constant value setting 3: 140MHz or more
  45         #   - PLL constant value setting 4: always 1, as per datasheet
  46         #   - PLL constant value setting 5: 140MHz or more
  47         mww 0xf0050010 0x00000065
  48
  49         # SYSCR3 (System Control Register 3): Enable PLL.
  50         #   - PLL operation control: on
  51         #   - All other bits remain set as above.
  52         mww 0xf005000c 0x00000087
  53
  54         # Wait for PLL to stabilize.
  55         sleep 10
  56
  57         # SYSCR2 (System Control Register 2): Switch from fOSCH to fPLL.
  58         #   - Selection of the PLL output clock: fPLL
  59         mww 0xf0050008 0x00000002
  60
  61         # SYSCR1 (System Control Register 1):
  62         #   - Clock gear programming: fc/1 (i.e., gear = 1, don't divide).
  63         mww 0xf0050004 0x00000000
  64
  65         # CLKCR5 (Clock Control Register 5): Set bits 3 and 6. The datasheet
  66         # says the bits are reserved, but also recommends "Write as one".
  67         mww 0xf0050054 0x00000048
  68
  69
  70         ##############################################################
  71         # Dynamic Memory Controller (DMC) / DDR SDRAM initialization #
  72         ##############################################################
  73
  74         # PMC (Power Management Controller):
  75         # PMCDRV (External Port "Driverbility" control register):
  76         # Bits DRV_MEM0/DRV_MEM1 (memory relation port drive power):
  77         mww 0xf0020260 0x00000003       ;# Select 1.8V +/- 0.1V
  78
  79         # Setup DDR SDRAM timing parameters for our specific chip.
  80         mww 0xf4310014 0x00000004       ;# cas_latency = 2
  81         mww 0xf4310018 0x00000001       ;# t_dqss = 1
  82         mww 0xf431001c 0x00000002       ;# t_mrd = 2
  83         mww 0xf4310020 0x0000000a       ;# t_ras = 10
  84         mww 0xf4310024 0x0000000a       ;# t_rc = 10
  85         mww 0xf4310028 0x00000013       ;# t_rcd = 3, schedule_rcd = 2
  86         mww 0xf431002c 0x0000010a       ;# t_rfc = 10, schedule_rfc = 8
  87         mww 0xf4310030 0x00000013       ;# t_rp = 3, schedule_rp = 2
  88         mww 0xf4310034 0x00000002       ;# t_rrd = 2
  89         mww 0xf4310038 0x00000002       ;# t_wr = 2
  90         mww 0xf431003c 0x00000001       ;# t_wtr = 1
  91         mww 0xf4310040 0x0000000a       ;# t_xp = 10
  92         mww 0xf4310044 0x0000000c       ;# t_xsr = 12
  93         mww 0xf4310048 0x00000014       ;# t_esr = 20
  94
  95         # dmc_memory_cfg_5 (DMC Memory Configuration register):
  96         # Set memory configuration:
  97         # column_bits = 10, row_bits = 13, ap-bit = 10, power_down_prd = 0,
  98         # auto_power_down = disable, stop_mem_clock = disable, memory_burst = 4
  99         mww 0xf431000c 0x00010012
 100
 101         # dmc_user_config_5 (DMC user_config register):
 102         # Data bus width of DDR SDRAM: 16 bit
 103         mww 0xf4310304 0x00000058
 104
 105         # dmc_refresh_prd_5 (DMC Refresh Period register):
 106         # Auto refresh: every 2656 (0xa60) DMCSCLK periods.
 107         mww 0xf4310010 0x00000a60
 108
 109         # dmc_chip_0_cfg_5 (DMC chip_0_cfg registers):
 110         #   - SDRAM address structure: bank, row, column
 111         #   - address_match = 01000000 (start address [31:24])
 112         #   - address_mask  = 11111100 (start address [31:24] mask value)
 113         mww 0xf4310200 0x000140fc
 114
 115         # Initialize the DDR SDRAM chip.
 116         # dmc_direct_cmd_5 (DMC Direct Command register).
 117         # See datasheet chapter 3.10.5.1, page 268.
 118         mww 0xf4310008 0x000c0000       ;# RAM init: NOP
 119         mww 0xf4310008 0x00000000       ;# RAM init: Precharge all
 120         mww 0xf4310008 0x00040000       ;# RAM init: Autorefresh
 121         mww 0xf4310008 0x00040000       ;# RAM init: Autorefresh
 122         mww 0xf4310008 0x00080032       ;# RAM init: addr_13_to_0 = 0x32
 123         mww 0xf4310008 0x000c0000       ;# RAM init: NOP
 124         mww 0xf4310008 0x000a0000       ;# RAM init: bank_addr = bank 2
 125
 126         # dmc_id_<0-5>_cfg_5 (DMC id_<0-5>_cfg registers):
 127         # Set min./max. QoS values.
 128         #   - 0x5: Enable QoS, max. QoS = 1
 129         #   - 0xb: Enable QoS, min. QoS = 2
 130         mww 0xf4310100 0x00000005       ;# AHB0: CPU Data
 131         mww 0xf4310104 0x00000005       ;# AHB1: CPU Inst
 132         mww 0xf4310108 0x0000000b       ;# AHB2: LCDC
 133         mww 0xf431010c 0x00000005       ;# AHB3: LCDDA, USB
 134         mww 0xf4310110 0x00000005       ;# AHB4: DMA1
 135         mww 0xf4310114 0x00000005       ;# AHB5: DMA2
 136
 137         # dmc_memc_cmd_5 (DMC Memory Controller Command register):
 138         # Change DMC state to ready.
 139         mww 0xf4310004 0x00000000       ;# memc_cmd = "Go"
 140
 141         # EBI: SMC Timeout register
 142         mww 0xf00a0050 0x00000001       ;# smc_timeout = 1
 143
 144
 145         ########################################################
 146         # Static Memory Controller (SMC) / SRAM initialization #
 147         ########################################################
 148
 149         # smc_set_cycles_5 (SMC Set Cycles register):
 150         # tRC = 10, tWC = 10, tCEOE = 7, tWP = 5, tPC=2, tTR=2
 151         mww 0xf4311014 0x0004afaa
 152
 153         # smc_set_opmode_5 (SMC Set Opmode register):
 154         # Memory data bus width = 16 bits, async read mode, read burst
 155         # length = 1 beat, async write mode, write burst length = 1 beat,
 156         # byte enable (SMCBE0-1) timing = SMCCSn timing, memory burst boundary
 157         # split setting = burst can cross any address boundary
 158         mww 0xf4311018 0x00000001
 159
 160         # smc_direct_cmd_5 (SMC Direct Command register):
 161         # cmd_type = UpdateRegs, chip_select = CS1
 162         mww 0xf4311010 0x00c00000
 163 }
 164
 165 #######################
 166 # Flash configuration #
 167 #######################
 168
 169 # TODO: Implement NAND support.
 170