tcl/board/dm365evm.cfg

   1 # DM365 EVM board -- Beta
   2 #   http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html
   3 #   http://support.spectrumdigital.com/boards/evmdm365
   4
   5 source [find target/ti_dm365.cfg]
   6
   7 # NOTE:  in Rev C boards, the CPLD ignores SRST from the ARM-20 JTAG
   8 # connector, so it doesn't affect generation of the reset signal.
   9 # Accordingly, resets require something else.  ICEpick could do it;
  10 # but its docs aren't generally available.
  11 #
  12 # At this writing, newer boards aren't available ... so assume no SRST.
  13 # Also ICEpick docs aren't available ... so we must use watchdog reset,
  14 # and hope the CPU isn't wedged or in a WFI loop (either of which can
  15 # block access to CPU and thus watchdog registers).
  16
  17 reset_config trst_only
  18 $_TARGETNAME configure -event reset-assert "davinci_wdog_reset"
  19
  20 # SW5.1 routes CS0: NAND vs OneNAND.
  21 # SW4.6:4 controls AEMIF width (8 for NAND, 16 for OneNand)
  22 # for boot-from-flash, those must agree with SW4.3:1 settings.
  23
  24 if { [info exists CS0MODE] } {
  25         # NAND or OneNAND
  26         set CS0 $CS0MODE
  27 } else {
  28         set CS0 ""
  29         echo "WARNING:  CS0 configuration not known"
  30         proc cs0_setup {a_emif} {}
  31         proc flashprobe {} {}
  32 }
  33
  34 set a_emif [dict get $dm365 a_emif]
  35
  36 # As shipped:  boot from NAND.
  37 if { $CS0 == "NAND" } {
  38         echo "CS0 NAND"
  39
  40         # NAND socket has two chipselects.  Default MT29F16G08FAA chip
  41         # has 1GByte on each one.
  42         # NOTE:  "hwecc4" here presumes that you're not updating anything
  43         # that needs infix layout (e.g. UBL, old U-Boot, etc)
  44         nand device low davinci $_TARGETNAME 0x02000000 hwecc4 $a_emif
  45         nand device high davinci $_TARGETNAME 0x02004000 hwecc4 $a_emif
  46
  47         proc cs0_setup {a_emif} {
  48                 global dm365
  49
  50                 # 8 bit EMIF
  51                 davinci_pinmux $dm365 2 0x00000016
  52
  53                 # slow/pessimistic timings
  54                 set nand_timings 0x40400204
  55                 # fast (25% faster page reads)
  56                 #set nand_timings 0x0400008c
  57
  58                 # CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes)
  59                 mww [expr $a_emif + 0x10] $nand_timings
  60
  61                 # NANDFCR -- CS0 has NAND
  62                 mww [expr $a_emif + 0x60] 0x01
  63         }
  64         proc flashprobe {} {
  65                 nand probe 0
  66                 nand probe 1
  67         }
  68
  69 } elseif { $CS0 == "OneNAND" } {
  70         echo "CS0 OneNAND"
  71
  72         # No support for this OneNAND in OpenOCD (yet) or Linux ...
  73         # REVISIT OneNAND timings not verified to work!
  74         echo "WARNING -- OneNAND not yet tested!"
  75
  76         proc cs0_setup {a_emif} {
  77                 global dm365
  78
  79                 # 16 bit EMIF
  80                 davinci_pinmux $dm365 2 0x00000055
  81
  82                 # CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes)
  83                 mww [expr $a_emif + 0x10] 0x00000001
  84
  85                 # ONENANDCTRL -- CS0 has OneNAND, enable sync reads
  86                 mww [expr $a_emif + 0x5c] 0x0441
  87         }
  88         proc flashprobe {} { }
  89 }
  90
  91 # NOTE:  disable or replace this call to dm365evm_init if you're
  92 # debugging new UBL/NANDboot code from SRAM.
  93 $_TARGETNAME configure -event reset-init { dm365evm_init }
  94
  95 #
  96 # This post-reset init is called when the MMU isn't active, all IRQs
  97 # are disabled, etc.  It should do most of what a UBL does, except for
  98 # loading code (like U-Boot) into DRAM and running it.
  99 #
 100 proc dm365evm_init {} {
 101         global dm365
 102
 103         echo "Initialize DM365 EVM board"
 104
 105         # CLKIN = 24 MHz ... can't talk quickly to ARM yet
 106         adapter speed 1500
 107
 108         # FIXME -- PLL init
 109
 110         ########################
 111         # PINMUX setup
 112
 113         davinci_pinmux $dm365 0 0x00fd0000
 114         davinci_pinmux $dm365 1 0x00145555
 115         # mux2 controls AEMIF ... 8 bit for NAND, 16 for OneNand
 116         davinci_pinmux $dm365 3 0x375affff
 117         davinci_pinmux $dm365 4 0x55556555
 118
 119         ########################
 120         # PSC setup (minimal)
 121
 122         # DDR EMIF/13, AEMIF/14, UART0/19
 123         psc_enable 13
 124         psc_enable 14
 125         psc_enable 19
 126         psc_go
 127
 128         # FIXME setup DDR2 (needs PLL)
 129
 130         ########################
 131         # ASYNC EMIF
 132
 133         set a_emif [dict get $dm365 a_emif]
 134
 135         # AWCCR
 136         mww [expr $a_emif + 0x04] 0xff
 137         # CS0 == NAND or OneNAND
 138         cs0_setup $a_emif
 139         # CS1 == CPLD
 140         mww [expr $a_emif + 0x14] 0x00a00505
 141
 142         # FIXME setup UART0
 143
 144         flashprobe
 145 }