tcl/board/dm355evm.cfg

   1 # DM355 EVM board
   2 #   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
   3 #   http://c6000.spectrumdigital.com/evmdm355/
   4
   5 source [find target/ti_dm355.cfg]
   6
   7 reset_config trst_and_srst separate
   8
   9 # NOTE:  disable or replace this call to dm355evm_init if you're
  10 # debugging new UBL code from SRAM.
  11 $_TARGETNAME configure -event reset-init { dm355evm_init }
  12
  13 #
  14 # This post-reset init is called when the MMU isn't active, all IRQs
  15 # are disabled, etc.  It should do most of what a UBL does, except for
  16 # loading code (like U-Boot) into DRAM and running it.
  17 #
  18 proc dm355evm_init {} {
  19         global dm355
  20
  21         puts "Initialize DM355 EVM board"
  22
  23         # CLKIN = 24 MHz ... can't talk quickly to ARM yet
  24         jtag_rclk 1500
  25
  26         ########################
  27         # PLL1          = 432 MHz (/8, x144)
  28         # ...SYSCLK1    = 216 MHz (/2)  ... ARM, MJCP
  29         # ...SYSCLK2    = 108 MHz (/4)  ... Peripherals
  30         # ...SYSCLK3    = 27  MHz (/16) ... VPBE, DAC
  31         # ...SYSCLK4    = 108 MHz (/4)  ... VPSS
  32         #       pll1.{prediv,div1,div2} are fixed
  33         #       pll1.postdiv set in MISC (for *this* speed grade)
  34
  35         set addr [dict get $dm355 pllc1]
  36         set pll_divs [dict create]
  37         dict set pll_divs div3 16
  38         dict set pll_divs div4 8
  39         pll_v02_setup $addr 144 $pll_divs
  40
  41         # ARM is now running at 216 MHz, so JTAG can go faster
  42         jtag_rclk 20000
  43
  44         ########################
  45         # PLL2          = 342 MHz (/8, x114)
  46         # ....SYSCLK1   = 342 MHz (/1)  ... DDR PHY at 171 MHz, 2x clock
  47         #       pll2.{postdiv,div1} are fixed
  48
  49         set addr [dict get $dm355 pllc2]
  50         set pll_divs [dict create]
  51         dict set pll_divs prediv 8
  52         pll_v02_setup $addr 114 $pll_divs
  53
  54         ########################
  55         # PINMUX
  56
  57         # All Video Inputs
  58         davinci_pinmux $dm355 0 0x00007f55
  59         # All Video Outputs
  60         davinci_pinmux $dm355 1 0x00145555
  61         # EMIFA (NOTE: more could be set up for use as GPIOs)
  62         davinci_pinmux $dm355 2 0x00000c08
  63         # SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
  64         davinci_pinmux $dm355 3 0x1bff55ff
  65         # MMC/SD0 instead of MS; SPI0
  66         davinci_pinmux $dm355 4 0x00000000
  67
  68         ########################
  69         # PSC setup (minimal)
  70
  71         # DDR EMIF/13, AEMIF/14, UART0/19
  72         psc_enable 13
  73         psc_enable 14
  74         psc_enable 19
  75         psc_go
  76
  77         ########################
  78         # DDR2 EMIF
  79
  80         # FIXME setup
  81
  82         ########################
  83         # ASYNC EMIF
  84
  85         set addr [dict get $dm355 a_emif]
  86
  87         # slow/pessimistic timings
  88         set nand_timings 0x40400204
  89         # fast (25% faster page reads)
  90         #set nand_timings 0x0400008c
  91
  92         # AWCCR
  93         mww [expr $addr + 0x04] 0xff
  94         # CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
  95         mww [expr $addr + 0x10] $nand_timings
  96         # CS1 == dm9000 Ethernet
  97         mww [expr $addr + 0x14] 0x00a00505
  98         # NANDFCR -- only CS0 has NAND
  99         mww [expr $addr + 0x60] 0x01
 100
 101         ########################
 102         # UART0
 103
 104         # FIXME setup
 105 }
 106
 107 # NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
 108 #
 109 # NOTE:  "hwecc4" here presumes that if you're using the standard 2GB NAND
 110 # you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
 111 # use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
 112 # needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
 113 nand device davinci 0 0x02000000 hwecc4 0x01e10000
 114 nand device davinci 0 0x02004000 hwecc4 0x01e10000
 115
 116 # FIXME
 117 #  - support writing UBL with its header (new layout only with new ROMs)
 118 #  - support writing ABL/U-Boot with its header (new layout)