tcl/board/digi_connectcore_wi-9c.cfg

   1 ######################################
   2 # Target: DIGI ConnectCore Wi-9C
   3 ######################################
   4
   5 reset_config trst_and_srst
   6
   7 # FIXME use some standard target config, maybe create one from this
   8 #
   9 #       source [find target/...cfg]
  10
  11 if { [info exists CHIPNAME] } {
  12    set  _CHIPNAME $CHIPNAME
  13 } else {
  14    set  _CHIPNAME ns9360
  15 }
  16
  17 if { [info exists ENDIAN] } {
  18    set  _ENDIAN $ENDIAN
  19 } else {
  20   # This config file was defaulting to big endian..
  21    set  _ENDIAN big
  22 }
  23
  24
  25 # What's a good fallback frequency for this board if RCLK is
  26 # not available??
  27 jtag_rclk 1000
  28
  29
  30 if { [info exists CPUTAPID] } {
  31    set _CPUTAPID $CPUTAPID
  32 } else {
  33    set _CPUTAPID 0x07926031
  34 }
  35
  36 set _TARGETNAME $_CHIPNAME.cpu
  37 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  38
  39 adapter_nsrst_delay 200
  40 jtag_ntrst_delay 0
  41
  42
  43 ######################
  44 # Target configuration
  45 ######################
  46
  47 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
  48
  49 $_TARGETNAME configure -event reset-init {
  50         mww 0x90600104 0x33313333
  51         mww 0xA0700000 0x00000001  ;# Enable the memory controller.
  52         mww 0xA0700024 0x00000006  ;# Set the refresh counter 6
  53         mww 0xA0700028 0x00000001  ;#
  54         mww 0xA0700030 0x00000001  ;# Set the precharge period
  55         mww 0xA0700034 0x00000004  ;# Active to precharge command period is 16 clock cycles
  56         mww 0xA070003C 0x00000001  ;# tAPR
  57         mww 0xA0700040 0x00000005  ;# tDAL
  58         mww 0xA0700044 0x00000001  ;# tWR
  59         mww 0xA0700048 0x00000006  ;# tRC 32 clock cycles
  60         mww 0xA070004C 0x00000006  ;# tRFC 32 clock cycles
  61         mww 0xA0700054 0x00000001  ;# tRRD
  62         mww 0xA0700058 0x00000001  ;# tMRD
  63         mww 0xA0700100 0x00004280  ;# Dynamic Config 0 (cs4)
  64         mww 0xA0700120 0x00004280  ;# Dynamic Config 1 (cs5)
  65         mww 0xA0700140 0x00004280  ;# Dynamic Config 2 (cs6)
  66         mww 0xA0700160 0x00004280  ;# Dynamic Config 3 (cs7)
  67         #
  68         mww 0xA0700104 0x00000203  ;# CAS latency is 2 at 100 MHz
  69         mww 0xA0700124 0x00000203  ;# CAS latency is 2 at 100 MHz
  70         mww 0xA0700144 0x00000203  ;# CAS latency is 2 at 100 MHz
  71         mww 0xA0700164 0x00000203  ;# CAS latency is 2 at 100 MHz
  72         #
  73         mww 0xA0700020 0x00000103  ;# issue SDRAM PALL command
  74         #
  75         mww 0xA0700024 0x00000001  ;# Set the refresh counter to be as small as possible
  76         #
  77         # Add some dummy writes to give the SDRAM time to settle, it needs two
  78         # AHB clock cycles, here we poke in the debugger flag, this lets
  79         # the software know that we are in the debugger
  80         mww 0xA0900000 0x00000002
  81         mww 0xA0900000 0x00000002
  82         mww 0xA0900000 0x00000002
  83         mww 0xA0900000 0x00000002
  84         mww 0xA0900000 0x00000002
  85         #
  86         mdw 0xA0900000
  87         mdw 0xA0900000
  88         mdw 0xA0900000
  89         mdw 0xA0900000
  90         mdw 0xA0900000
  91         #
  92         mww 0xA0700024 0x00000030 ;# Set the refresh counter to 30
  93         mww 0xA0700020 0x00000083 ;# Issue SDRAM MODE command
  94         #
  95         # Next we perform a read of RAM.
  96         # mw = move word.
  97         mdw 0x00022000
  98         # mw 0x00022000:P, r3  # 22000 for cas2 latency, 32000 for cas 3
  99         #
 100         mww 0xA0700020 0x00000003   ;# issue SDRAM NORMAL command
 101         mww 0xA0700100 0x00084280   ;# Enable buffer access
 102         mww 0xA0700120 0x00084280   ;# Enable buffer access
 103         mww 0xA0700140 0x00084280   ;# Enable buffer access
 104         mww 0xA0700160 0x00084280   ;# Enable buffer access
 105
 106         #Set byte lane state (static mem 1)"
 107         mww 0xA0700220 0x00000082
 108         #Flash Start
 109         mww 0xA09001F8 0x50000000
 110         #Flash Mask Reg
 111         mww 0xA09001FC 0xFF000001
 112         mww 0xA0700028 0x00000001
 113
 114         #  RAMAddr = 0x00020000
 115         #  RAMSize = 0x00004000
 116
 117         # Set the processor mode
 118         reg cpsr 0xd3
 119 }
 120
 121 $_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
 122
 123 #####################
 124 # Flash configuration
 125 #####################
 126
 127 #M29DW323DB - not working
 128 #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
 129 set _FLASHNAME $_CHIPNAME.flash
 130 flash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 $_TARGETNAME