tcl/board/at91cap7a-stk-sdram.cfg

   1 # http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394
   2 #
   3 # use combined on interfaces or targets that can't set TRST/SRST separately
   4 reset_config trst_and_srst srst_pulls_trst
   5
   6 if { [info exists CHIPNAME] } {
   7    set  _CHIPNAME $CHIPNAME
   8 } else {
   9    set  _CHIPNAME cap7
  10 }
  11
  12 if { [info exists ENDIAN] } {
  13    set  _ENDIAN $ENDIAN
  14 } else {
  15    set  _ENDIAN little
  16 }
  17
  18 if { [info exists CPUTAPID ] } {
  19    set _CPUTAPID $CPUTAPID
  20 } else {
  21    set _CPUTAPID 0x40700f0f
  22 }
  23
  24 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  25
  26 set _TARGETNAME $_CHIPNAME.cpu
  27 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
  28
  29 $_TARGETNAME configure -event reset-start {
  30         # start off real slow when we're running off internal RC oscillator
  31         jtag_khz 10
  32 }
  33
  34 proc peek32 {address} {
  35         ocd_mem2array t 32 $address 1
  36         return $t(0)
  37 }
  38
  39 # Wait for an expression to be true with a timeout
  40 proc wait_state {expression} {
  41         for {set i 0} {$i < 1000} {set i [expr $i + 1]} {
  42                 if {[uplevel 1 $expression] == 0} {
  43                         return
  44                 }
  45         }
  46         return -code 1 "Timed out"
  47 }
  48
  49 # Use a global variable here to be able to tinker interactively with
  50 # post reset jtag frequency.
  51 global post_reset_khz
  52 # Danger!!!! Even 16MHz kinda works with this target, but
  53 # it needs to be as low as 2000kHz to be stable.
  54 set post_reset_khz 2000
  55
  56 $_TARGETNAME configure -event reset-init {
  57         echo "Configuring master clock"
  58         # disable watchdog
  59         mww 0xfffffd44 0xff008000
  60         # enable user reset
  61         mww 0xfffffd08 0xa5000001
  62         # Enable main oscillator
  63         mww 0xFFFFFc20  0x00000f01
  64         wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
  65
  66         # Set PLLA to 96MHz
  67         mww 0xFFFFFc28 0x20072801
  68         wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
  69
  70         # Select prescaler
  71         mww 0xFFFFFC30 0x00000004
  72         wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
  73
  74         # Select master clock to 48MHz
  75         mww 0xFFFFFC30 0x00000006
  76         wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
  77
  78         echo "Master clock ok."
  79         echo "Configuring the SDRAM controller..."
  80
  81         # Configure EBI Chip select for SDRAM
  82         mww 0xFFFFEF30 0x00000102
  83
  84         # Enable clock on EBI PIOs
  85         mww 0xFFFFFC10 0x00000004
  86
  87         # Configure PIO for SDRAM
  88         mww 0xFFFFF470 0xFFFF0000
  89         mww 0xFFFFF474 0x00000000
  90         mww 0xFFFFF404 0xFFFF0000
  91
  92         # Configure SDRAMC CR
  93         mww 0xFFFFEA08 0xA63392F9
  94
  95         # NOP command
  96         mww 0xFFFFEA00 0x1
  97         mww 0x20000000 0
  98
  99         # Precharge All Banks command
 100         mww 0xFFFFEA00 0x2
 101         mww 0x20000000 0
 102
 103         # Set 1st CBR
 104         mww 0xFFFFEA00 0x00000004
 105         mww 0x20000010 0x00000001
 106
 107         # Set 2nd CBR
 108         mww 0xFFFFEA00 0x00000004
 109         mww 0x20000020 0x00000002
 110
 111         # Set 3rd CBR
 112         mww 0xFFFFEA00 0x00000004
 113         mww 0x20000030 0x00000003
 114
 115         # Set 4th CBR
 116         mww 0xFFFFEA00 0x00000004
 117         mww 0x20000040 0x00000004
 118
 119         # Set 5th CBR
 120         mww 0xFFFFEA00 0x00000004
 121         mww 0x20000050 0x00000005
 122
 123         # Set 6th CBR
 124         mww 0xFFFFEA00 0x00000004
 125         mww 0x20000060 0x00000006
 126
 127         # Set 7th CBR
 128         mww 0xFFFFEA00 0x00000004
 129         mww 0x20000070 0x00000007
 130
 131         # Set 8th CBR
 132         mww 0xFFFFEA00 0x00000004
 133         mww 0x20000080 0x00000008
 134
 135         # Set LMR operation
 136         mww 0xFFFFEA00 0x00000003
 137
 138         # Perform LMR burst=1, lat=2
 139         mww 0x20000020 0xCAFEDEDE
 140
 141         # Set Refresh Timer
 142         mww 0xFFFFEA04 0x00000203
 143
 144         # Set Normal mode
 145         mww 0xFFFFEA00 0x00000000
 146         mww 0x20000000 0x00000000
 147
 148         #remap internal memory at address 0x0
 149         mww 0xffffef00 0x3
 150
 151         echo "SDRAM configuration ok."
 152
 153         # Now that we're up and running, crank up speed!
 154         global post_reset_khz
 155         jtag_khz $post_reset_khz
 156 }
 157
 158 $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
 159
 160 arm7_9 dcc_downloads enable
 161 arm7_9 fast_memory_access enable
 162
 163 #set _FLASHNAME $_CHIPNAME.flash
 164 #flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
 165