tcl/board/am3517evm.cfg

   1 # DANGER!!!! early work in progress for this PCB/target.
   2 #
   3 # The most basic operations work well enough that it is
   4 # useful to have this in the repository for cooperation
   5 # alpha testing purposes.
   6 #
   7 # TI AM3517
   8 #
   9 # http://focus.ti.com/docs/prod/folders/print/am3517.html
  10 # http://processors.wiki.ti.com/index.php/Debug_Access_Port_(DAP)
  11 # http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x
  12
  13 # Slooow during startup
  14 adapter_khz 10
  15
  16
  17 if { [info exists CHIPNAME] } {
  18    set  _CHIPNAME $CHIPNAME
  19 } else {
  20    set  _CHIPNAME am3517
  21 }
  22
  23 set JRC_TAPID 0
  24
  25 set DAP_TAPID 0x0b86802f
  26
  27 # Subsidiary TAP: CoreSight Debug Access Port (DAP)
  28 if { [info exists DAP_TAPID ] } {
  29    set _DAP_TAPID $DAP_TAPID
  30 } else {
  31    set _DAP_TAPID 0x0b6d602f
  32 }
  33
  34
  35 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
  36 if { [info exists JRC_TAPID ] } {
  37    set _JRC_TAPID $JRC_TAPID
  38 } else {
  39    set _JRC_TAPID 0x0b7ae02f
  40 }
  41
  42 # ICEpick-C ... used to route Cortex, and more not shown here
  43 source [find target/icepick.cfg]
  44
  45
  46 jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
  47         -expected-id $_DAP_TAPID -disable
  48 jtag configure $_CHIPNAME.dap -event tap-enable \
  49         "icepick_c_tapenable $_CHIPNAME.jrc 3"
  50
  51 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
  52         -expected-id $_JRC_TAPID
  53
  54
  55
  56 # GDB target:  Cortex-A8, using DAP
  57 set _TARGETNAME $_CHIPNAME.cpu
  58 target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
  59
  60 # SRAM: 64K at 0x4020.0000; use the first 16K
  61 $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
  62
  63 ###################
  64
  65 # the reset sequence is event-driven
  66 # and kind of finicky...
  67
  68 # some TCK tycles are required to activate the DEBUG power domain
  69 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
  70
  71 # have the DAP "always" be active
  72 jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
  73
  74 proc omap3_dbginit {target} {
  75
  76      # General Cortex A8 debug initialisation
  77      cortex_a8 dbginit
  78      # Enable DBGU signal for OMAP353x
  79      $target mww phys 0x5401d030 0x00002000
  80 }
  81
  82 # be absolutely certain the JTAG clock will work with the worst-case
  83 # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
  84 # OK to speed up *after* PLL and clock tree setup.
  85
  86 $_TARGETNAME configure -event "reset-start" { adapter_khz 10}
  87
  88 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
  89 # ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
  90 # would issue.  RST_DPLL3 (4) is a cold reset.
  91 set PRM_RSTCTRL 0x48307250
  92 $_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 2"
  93
  94 $_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME; adapter_khz 1000"
  95
  96
  97 reset_config trst_only