src/target/xscale.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  20  ***************************************************************************/
  21
  22 #ifndef OPENOCD_TARGET_XSCALE_H
  23 #define OPENOCD_TARGET_XSCALE_H
  24
  25 #include "arm.h"
  26 #include "armv4_5_mmu.h"
  27 #include "trace.h"
  28
  29 #define XSCALE_COMMON_MAGIC 0x58534341
  30
  31 /* These four JTAG instructions are architecturally defined.
  32  * Lengths are core-specific; originally 5 bits, later 7.
  33  */
  34 #define XSCALE_DBGRX    0x02
  35 #define XSCALE_DBGTX    0x10
  36 #define XSCALE_LDIC     0x07
  37 #define XSCALE_SELDCSR  0x09
  38
  39 /* Possible CPU types */
  40 #define XSCALE_IXP4XX_PXA2XX    0x0
  41 #define XSCALE_PXA3XX           0x4
  42
  43 enum xscale_debug_reason {
  44         XSCALE_DBG_REASON_GENERIC,
  45         XSCALE_DBG_REASON_RESET,
  46         XSCALE_DBG_REASON_TB_FULL,
  47 };
  48
  49 enum xscale_trace_entry_type {
  50         XSCALE_TRACE_MESSAGE = 0x0,
  51         XSCALE_TRACE_ADDRESS = 0x1,
  52 };
  53
  54 struct xscale_trace_entry {
  55         uint8_t data;
  56         enum xscale_trace_entry_type type;
  57 };
  58
  59 struct xscale_trace_data {
  60         struct xscale_trace_entry *entries;
  61         int depth;
  62         uint32_t chkpt0;
  63         uint32_t chkpt1;
  64         uint32_t last_instruction;
  65         unsigned int num_checkpoints;
  66         struct xscale_trace_data *next;
  67 };
  68
  69 enum trace_mode {
  70         XSCALE_TRACE_DISABLED,
  71         XSCALE_TRACE_FILL,
  72         XSCALE_TRACE_WRAP
  73 };
  74
  75 struct xscale_trace {
  76         struct image *image;                                    /* source for target opcodes */
  77         struct xscale_trace_data *data;         /* linked list of collected trace data */
  78         int buffer_fill;                                /* maximum number of trace runs to read */
  79         int fill_counter;                               /* running count during trace collection */
  80         enum trace_mode mode;
  81         enum arm_state core_state;      /* current core state (ARM, Thumb) */
  82 };
  83
  84 struct xscale_common {
  85         /* armv4/5 common stuff */
  86         struct arm arm;
  87
  88         int common_magic;
  89
  90         /* XScale registers (CP15, DBG) */
  91         struct reg_cache *reg_cache;
  92
  93         /* current state of the debug handler */
  94         uint32_t handler_address;
  95
  96         /* target-endian buffers with exception vectors */
  97         uint32_t low_vectors[8];
  98         uint32_t high_vectors[8];
  99
 100         /* static low vectors */
 101         uint8_t static_low_vectors_set; /* bit field with static vectors set by the user */
 102         uint8_t static_high_vectors_set; /* bit field with static vectors set by the user */
 103         uint32_t static_low_vectors[8];
 104         uint32_t static_high_vectors[8];
 105
 106         /* DCache cleaning */
 107         uint32_t cache_clean_address;
 108
 109         /* whether hold_rst and ext_dbg_break should be set */
 110         int hold_rst;
 111         int external_debug_break;
 112
 113         /* breakpoint / watchpoint handling */
 114         int dbr_available;
 115         int dbr0_used;
 116         int dbr1_used;
 117         int ibcr_available;
 118         int ibcr0_used;
 119         int     ibcr1_used;
 120         uint32_t arm_bkpt;
 121         uint16_t thumb_bkpt;
 122
 123         uint8_t vector_catch;
 124
 125         struct xscale_trace trace;
 126
 127         int arch_debug_reason;
 128
 129         /* MMU/Caches */
 130         struct armv4_5_mmu_common armv4_5_mmu;
 131         uint32_t cp15_control_reg;
 132
 133         int fast_memory_access;
 134
 135         /* CPU variant */
 136         int xscale_variant;
 137 };
 138
 139 static inline struct xscale_common *
 140 target_to_xscale(struct target *target)
 141 {
 142         return container_of(target->arch_info, struct xscale_common, arm);
 143 }
 144
 145 struct xscale_reg {
 146         int dbg_handler_number;
 147         struct target *target;
 148 };
 149
 150 enum {
 151         XSCALE_MAINID,          /* 0 */
 152         XSCALE_CACHETYPE,
 153         XSCALE_CTRL,
 154         XSCALE_AUXCTRL,
 155         XSCALE_TTB,
 156         XSCALE_DAC,
 157         XSCALE_FSR,
 158         XSCALE_FAR,
 159         XSCALE_PID,
 160         XSCALE_CPACCESS,
 161         XSCALE_IBCR0,           /* 10 */
 162         XSCALE_IBCR1,
 163         XSCALE_DBR0,
 164         XSCALE_DBR1,
 165         XSCALE_DBCON,
 166         XSCALE_TBREG,
 167         XSCALE_CHKPT0,
 168         XSCALE_CHKPT1,
 169         XSCALE_DCSR,
 170         XSCALE_TX,
 171         XSCALE_RX,                      /* 20 */
 172         XSCALE_TXRXCTRL,
 173 };
 174
 175 #define ERROR_XSCALE_NO_TRACE_DATA      (-700)
 176
 177 /* DCSR bit and field definitions */
 178 #define DCSR_TR (1 << 16)
 179 #define DCSR_TU (1 << 17)
 180 #define DCSR_TS (1 << 18)
 181 #define DCSR_TA (1 << 19)
 182 #define DCSR_TD (1 << 20)
 183 #define DCSR_TI (1 << 22)
 184 #define DCSR_TF (1 << 23)
 185 #define DCSR_TRAP_MASK \
 186         (DCSR_TF | DCSR_TI | DCSR_TD | DCSR_TA | DCSR_TS | DCSR_TU | DCSR_TR)
 187
 188 #endif /* OPENOCD_TARGET_XSCALE_H */