1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "arm_simulator.h"
32 #include "arm_disassembler.h"
35 #include "binarybuffer.h"
36 #include "time_support.h"
37 #include "breakpoints.h"
43 #include <sys/types.h>
49 int xscale_register_commands(struct command_context_s
*cmd_ctx
);
51 /* forward declarations */
52 int xscale_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
53 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
56 int xscale_arch_state(struct target_s
*target
);
57 int xscale_poll(target_t
*target
);
58 int xscale_halt(target_t
*target
);
59 int xscale_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
);
60 int xscale_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
);
61 int xscale_debug_entry(target_t
*target
);
62 int xscale_restore_context(target_t
*target
);
64 int xscale_assert_reset(target_t
*target
);
65 int xscale_deassert_reset(target_t
*target
);
66 int xscale_soft_reset_halt(struct target_s
*target
);
67 int xscale_prepare_reset_halt(struct target_s
*target
);
69 int xscale_set_reg_u32(reg_t
*reg
, u32 value
);
71 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
);
72 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
);
74 int xscale_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
75 int xscale_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
76 int xscale_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
);
77 int xscale_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
);
79 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
80 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
81 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
82 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
83 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
84 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
85 void xscale_enable_watchpoints(struct target_s
*target
);
86 void xscale_enable_breakpoints(struct target_s
*target
);
87 static int xscale_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
);
88 static int xscale_mmu(struct target_s
*target
, int *enabled
);
90 int xscale_read_trace(target_t
*target
);
92 target_type_t xscale_target
=
97 .arch_state
= xscale_arch_state
,
99 .target_request_data
= NULL
,
102 .resume
= xscale_resume
,
105 .assert_reset
= xscale_assert_reset
,
106 .deassert_reset
= xscale_deassert_reset
,
107 .soft_reset_halt
= xscale_soft_reset_halt
,
108 .prepare_reset_halt
= xscale_prepare_reset_halt
,
110 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
112 .read_memory
= xscale_read_memory
,
113 .write_memory
= xscale_write_memory
,
114 .bulk_write_memory
= xscale_bulk_write_memory
,
115 .checksum_memory
= xscale_checksum_memory
,
117 .run_algorithm
= armv4_5_run_algorithm
,
119 .add_breakpoint
= xscale_add_breakpoint
,
120 .remove_breakpoint
= xscale_remove_breakpoint
,
121 .add_watchpoint
= xscale_add_watchpoint
,
122 .remove_watchpoint
= xscale_remove_watchpoint
,
124 .register_commands
= xscale_register_commands
,
125 .target_command
= xscale_target_command
,
126 .init_target
= xscale_init_target
,
129 .virt2phys
= xscale_virt2phys
,
133 char* xscale_reg_list
[] =
135 "XSCALE_MAINID", /* 0 */
145 "XSCALE_IBCR0", /* 10 */
155 "XSCALE_RX", /* 20 */
159 xscale_reg_t xscale_reg_arch_info
[] =
161 {XSCALE_MAINID
, NULL
},
162 {XSCALE_CACHETYPE
, NULL
},
164 {XSCALE_AUXCTRL
, NULL
},
170 {XSCALE_CPACCESS
, NULL
},
171 {XSCALE_IBCR0
, NULL
},
172 {XSCALE_IBCR1
, NULL
},
175 {XSCALE_DBCON
, NULL
},
176 {XSCALE_TBREG
, NULL
},
177 {XSCALE_CHKPT0
, NULL
},
178 {XSCALE_CHKPT1
, NULL
},
179 {XSCALE_DCSR
, NULL
}, /* DCSR accessed via JTAG or SW */
180 {-1, NULL
}, /* TX accessed via JTAG */
181 {-1, NULL
}, /* RX accessed via JTAG */
182 {-1, NULL
}, /* TXRXCTRL implicit access via JTAG */
185 int xscale_reg_arch_type
= -1;
187 int xscale_get_reg(reg_t
*reg
);
188 int xscale_set_reg(reg_t
*reg
, u8
*buf
);
190 int xscale_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, xscale_common_t
**xscale_p
)
192 armv4_5_common_t
*armv4_5
= target
->arch_info
;
193 xscale_common_t
*xscale
= armv4_5
->arch_info
;
195 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
197 ERROR("target isn't an XScale target");
201 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
)
203 ERROR("target isn't an XScale target");
207 *armv4_5_p
= armv4_5
;
213 int xscale_jtag_set_instr(int chain_pos
, u32 new_instr
)
215 jtag_device_t
*device
= jtag_get_device(chain_pos
);
217 if (buf_get_u32(device
->cur_instr
, 0, device
->ir_length
) != new_instr
)
221 field
.device
= chain_pos
;
222 field
.num_bits
= device
->ir_length
;
223 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
224 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
225 field
.out_mask
= NULL
;
226 field
.in_value
= NULL
;
227 jtag_set_check_value(&field
, device
->expected
, device
->expected_mask
, NULL
);
229 jtag_add_ir_scan(1, &field
, -1);
231 free(field
.out_value
);
237 int xscale_read_dcsr(target_t
*target
)
239 armv4_5_common_t
*armv4_5
= target
->arch_info
;
240 xscale_common_t
*xscale
= armv4_5
->arch_info
;
244 scan_field_t fields
[3];
246 u8 field0_check_value
= 0x2;
247 u8 field0_check_mask
= 0x7;
249 u8 field2_check_value
= 0x0;
250 u8 field2_check_mask
= 0x1;
252 jtag_add_end_state(TAP_PD
);
253 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dcsr
);
255 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
256 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
258 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
259 fields
[0].num_bits
= 3;
260 fields
[0].out_value
= &field0
;
261 fields
[0].out_mask
= NULL
;
262 fields
[0].in_value
= NULL
;
263 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
265 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
266 fields
[1].num_bits
= 32;
267 fields
[1].out_value
= NULL
;
268 fields
[1].out_mask
= NULL
;
269 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
270 fields
[1].in_handler
= NULL
;
271 fields
[1].in_handler_priv
= NULL
;
272 fields
[1].in_check_value
= NULL
;
273 fields
[1].in_check_mask
= NULL
;
275 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
276 fields
[2].num_bits
= 1;
277 fields
[2].out_value
= &field2
;
278 fields
[2].out_mask
= NULL
;
279 fields
[2].in_value
= NULL
;
280 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
282 jtag_add_dr_scan(3, fields
, -1);
284 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
286 ERROR("JTAG error while reading DCSR");
290 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
291 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
293 /* write the register with the value we just read
294 * on this second pass, only the first bit of field0 is guaranteed to be 0)
296 field0_check_mask
= 0x1;
297 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
298 fields
[1].in_value
= NULL
;
300 jtag_add_end_state(TAP_RTI
);
302 jtag_add_dr_scan(3, fields
, -1);
304 /* DANGER!!! this must be here. It will make sure that the arguments
305 * to jtag_set_check_value() does not go out of scope! */
306 return jtag_execute_queue();
309 int xscale_receive(target_t
*target
, u32
*buffer
, int num_words
)
312 return ERROR_INVALID_ARGUMENTS
;
315 armv4_5_common_t
*armv4_5
= target
->arch_info
;
316 xscale_common_t
*xscale
= armv4_5
->arch_info
;
318 enum tap_state path
[3];
319 scan_field_t fields
[3];
321 u8
*field0
= malloc(num_words
* 1);
322 u8 field0_check_value
= 0x2;
323 u8 field0_check_mask
= 0x6;
324 u32
*field1
= malloc(num_words
* 4);
325 u8 field2_check_value
= 0x0;
326 u8 field2_check_mask
= 0x1;
328 int words_scheduled
= 0;
336 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
337 fields
[0].num_bits
= 3;
338 fields
[0].out_value
= NULL
;
339 fields
[0].out_mask
= NULL
;
340 fields
[0].in_value
= NULL
;
341 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
343 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
344 fields
[1].num_bits
= 32;
345 fields
[1].out_value
= NULL
;
346 fields
[1].out_mask
= NULL
;
347 fields
[1].in_value
= NULL
;
348 fields
[1].in_handler
= NULL
;
349 fields
[1].in_handler_priv
= NULL
;
350 fields
[1].in_check_value
= NULL
;
351 fields
[1].in_check_mask
= NULL
;
355 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
356 fields
[2].num_bits
= 1;
357 fields
[2].out_value
= NULL
;
358 fields
[2].out_mask
= NULL
;
359 fields
[2].in_value
= NULL
;
360 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
362 jtag_add_end_state(TAP_RTI
);
363 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgtx
);
364 jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
366 /* repeat until all words have been collected */
368 while (words_done
< num_words
)
372 for (i
= words_done
; i
< num_words
; i
++)
374 fields
[0].in_value
= &field0
[i
];
375 fields
[1].in_handler
= buf_to_u32_handler
;
376 fields
[1].in_handler_priv
= (u8
*)&field1
[i
];
378 jtag_add_pathmove(3, path
);
379 jtag_add_dr_scan(3, fields
, TAP_RTI
);
383 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
385 ERROR("JTAG error while receiving data from debug handler");
389 /* examine results */
390 for (i
= words_done
; i
< num_words
; i
++)
392 if (!(field0
[0] & 1))
394 /* move backwards if necessary */
396 for (j
= i
; j
< num_words
- 1; j
++)
398 field0
[j
] = field0
[j
+1];
399 field1
[j
] = field1
[j
+1];
404 if (words_scheduled
==0)
406 if (attempts
++==1000)
408 ERROR("Failed to receiving data from debug handler after 1000 attempts");
409 retval
=ERROR_TARGET_TIMEOUT
;
414 words_done
+= words_scheduled
;
417 for (i
= 0; i
< num_words
; i
++)
418 *(buffer
++) = buf_get_u32((u8
*)&field1
[i
], 0, 32);
425 int xscale_read_tx(target_t
*target
, int consume
)
427 armv4_5_common_t
*armv4_5
= target
->arch_info
;
428 xscale_common_t
*xscale
= armv4_5
->arch_info
;
429 enum tap_state path
[3];
430 enum tap_state noconsume_path
[6];
433 struct timeval timeout
, now
;
435 scan_field_t fields
[3];
437 u8 field0_check_value
= 0x2;
438 u8 field0_check_mask
= 0x6;
439 u8 field2_check_value
= 0x0;
440 u8 field2_check_mask
= 0x1;
442 jtag_add_end_state(TAP_RTI
);
444 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgtx
);
450 noconsume_path
[0] = TAP_SDS
;
451 noconsume_path
[1] = TAP_CD
;
452 noconsume_path
[2] = TAP_E1D
;
453 noconsume_path
[3] = TAP_PD
;
454 noconsume_path
[4] = TAP_E2D
;
455 noconsume_path
[5] = TAP_SD
;
457 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
458 fields
[0].num_bits
= 3;
459 fields
[0].out_value
= NULL
;
460 fields
[0].out_mask
= NULL
;
461 fields
[0].in_value
= &field0_in
;
462 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
464 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
465 fields
[1].num_bits
= 32;
466 fields
[1].out_value
= NULL
;
467 fields
[1].out_mask
= NULL
;
468 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
;
469 fields
[1].in_handler
= NULL
;
470 fields
[1].in_handler_priv
= NULL
;
471 fields
[1].in_check_value
= NULL
;
472 fields
[1].in_check_mask
= NULL
;
476 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
477 fields
[2].num_bits
= 1;
478 fields
[2].out_value
= NULL
;
479 fields
[2].out_mask
= NULL
;
480 fields
[2].in_value
= NULL
;
481 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
483 gettimeofday(&timeout
, NULL
);
484 timeval_add_time(&timeout
, 5, 0);
488 /* if we want to consume the register content (i.e. clear TX_READY),
489 * we have to go straight from Capture-DR to Shift-DR
490 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
493 jtag_add_pathmove(3, path
);
496 jtag_add_pathmove(sizeof(noconsume_path
)/sizeof(*noconsume_path
), noconsume_path
);
499 jtag_add_dr_scan(3, fields
, TAP_RTI
);
501 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
503 ERROR("JTAG error while reading TX");
504 return ERROR_TARGET_TIMEOUT
;
507 gettimeofday(&now
, NULL
);
508 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
510 ERROR("time out reading TX register");
511 return ERROR_TARGET_TIMEOUT
;
513 if (!((!(field0_in
& 1)) && consume
))
517 usleep(500*1000); /* avoid flooding the logs */
520 if (!(field0_in
& 1))
521 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
526 int xscale_write_rx(target_t
*target
)
528 armv4_5_common_t
*armv4_5
= target
->arch_info
;
529 xscale_common_t
*xscale
= armv4_5
->arch_info
;
532 struct timeval timeout
, now
;
534 scan_field_t fields
[3];
537 u8 field0_check_value
= 0x2;
538 u8 field0_check_mask
= 0x6;
540 u8 field2_check_value
= 0x0;
541 u8 field2_check_mask
= 0x1;
543 jtag_add_end_state(TAP_RTI
);
545 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgrx
);
547 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
548 fields
[0].num_bits
= 3;
549 fields
[0].out_value
= &field0_out
;
550 fields
[0].out_mask
= NULL
;
551 fields
[0].in_value
= &field0_in
;
552 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
554 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
555 fields
[1].num_bits
= 32;
556 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
;
557 fields
[1].out_mask
= NULL
;
558 fields
[1].in_value
= NULL
;
559 fields
[1].in_handler
= NULL
;
560 fields
[1].in_handler_priv
= NULL
;
561 fields
[1].in_check_value
= NULL
;
562 fields
[1].in_check_mask
= NULL
;
566 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
567 fields
[2].num_bits
= 1;
568 fields
[2].out_value
= &field2
;
569 fields
[2].out_mask
= NULL
;
570 fields
[2].in_value
= NULL
;
571 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
573 gettimeofday(&timeout
, NULL
);
574 timeval_add_time(&timeout
, 5, 0);
576 /* poll until rx_read is low */
580 jtag_add_dr_scan(3, fields
, TAP_RTI
);
582 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
584 ERROR("JTAG error while writing RX");
588 gettimeofday(&now
, NULL
);
589 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
591 ERROR("time out writing RX register");
592 return ERROR_TARGET_TIMEOUT
;
594 if (!(field0_in
& 1))
596 usleep(500*1000); /* wait 500ms to avoid flooding the logs */
601 jtag_add_dr_scan(3, fields
, TAP_RTI
);
603 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
605 ERROR("JTAG error while writing RX");
612 /* send count elements of size byte to the debug handler */
613 int xscale_send(target_t
*target
, u8
*buffer
, int count
, int size
)
615 armv4_5_common_t
*armv4_5
= target
->arch_info
;
616 xscale_common_t
*xscale
= armv4_5
->arch_info
;
621 u8 output
[4] = {0, 0, 0, 0};
623 scan_field_t fields
[3];
625 u8 field0_check_value
= 0x2;
626 u8 field0_check_mask
= 0x6;
628 u8 field2_check_value
= 0x0;
629 u8 field2_check_mask
= 0x1;
631 jtag_add_end_state(TAP_RTI
);
633 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgrx
);
635 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
636 fields
[0].num_bits
= 3;
637 fields
[0].out_value
= &field0_out
;
638 fields
[0].out_mask
= NULL
;
639 fields
[0].in_handler
= NULL
;
640 fields
[0].in_value
= NULL
;
641 if (!xscale
->fast_memory_access
)
643 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
646 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
647 fields
[1].num_bits
= 32;
648 fields
[1].out_value
= output
;
649 fields
[1].out_mask
= NULL
;
650 fields
[1].in_value
= NULL
;
651 fields
[1].in_handler
= NULL
;
652 fields
[1].in_handler_priv
= NULL
;
653 fields
[1].in_check_value
= NULL
;
654 fields
[1].in_check_mask
= NULL
;
658 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
659 fields
[2].num_bits
= 1;
660 fields
[2].out_value
= &field2
;
661 fields
[2].out_mask
= NULL
;
662 fields
[2].in_value
= NULL
;
663 fields
[2].in_handler
= NULL
;
664 if (!xscale
->fast_memory_access
)
666 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
671 int endianness
= target
->endianness
;
672 while (done_count
++ < count
)
674 if (endianness
== TARGET_LITTLE_ENDIAN
)
687 jtag_add_dr_scan(3, fields
, TAP_RTI
);
693 while (done_count
++ < count
)
695 /* extract sized element from target-endian buffer, and put it
696 * into little-endian output buffer
701 buf_set_u32(output
, 0, 32, target_buffer_get_u16(target
, buffer
));
707 ERROR("BUG: size neither 4, 2 nor 1");
711 jtag_add_dr_scan(3, fields
, TAP_RTI
);
717 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
719 ERROR("JTAG error while sending data to debug handler");
726 int xscale_send_u32(target_t
*target
, u32 value
)
728 armv4_5_common_t
*armv4_5
= target
->arch_info
;
729 xscale_common_t
*xscale
= armv4_5
->arch_info
;
731 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
732 return xscale_write_rx(target
);
735 int xscale_write_dcsr(target_t
*target
, int hold_rst
, int ext_dbg_brk
)
737 armv4_5_common_t
*armv4_5
= target
->arch_info
;
738 xscale_common_t
*xscale
= armv4_5
->arch_info
;
742 scan_field_t fields
[3];
744 u8 field0_check_value
= 0x2;
745 u8 field0_check_mask
= 0x7;
747 u8 field2_check_value
= 0x0;
748 u8 field2_check_mask
= 0x1;
751 xscale
->hold_rst
= hold_rst
;
753 if (ext_dbg_brk
!= -1)
754 xscale
->external_debug_break
= ext_dbg_brk
;
756 jtag_add_end_state(TAP_RTI
);
757 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dcsr
);
759 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
760 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
762 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
763 fields
[0].num_bits
= 3;
764 fields
[0].out_value
= &field0
;
765 fields
[0].out_mask
= NULL
;
766 fields
[0].in_value
= NULL
;
767 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
769 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
770 fields
[1].num_bits
= 32;
771 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
772 fields
[1].out_mask
= NULL
;
773 fields
[1].in_value
= NULL
;
774 fields
[1].in_handler
= NULL
;
775 fields
[1].in_handler_priv
= NULL
;
776 fields
[1].in_check_value
= NULL
;
777 fields
[1].in_check_mask
= NULL
;
781 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
782 fields
[2].num_bits
= 1;
783 fields
[2].out_value
= &field2
;
784 fields
[2].out_mask
= NULL
;
785 fields
[2].in_value
= NULL
;
786 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
788 jtag_add_dr_scan(3, fields
, -1);
790 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
792 ERROR("JTAG error while writing DCSR");
796 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
797 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
802 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
803 unsigned int parity (unsigned int v
)
810 DEBUG("parity of 0x%x is %i", ov
, (0x6996 >> v
) & 1);
811 return (0x6996 >> v
) & 1;
814 int xscale_load_ic(target_t
*target
, int mini
, u32 va
, u32 buffer
[8])
816 armv4_5_common_t
*armv4_5
= target
->arch_info
;
817 xscale_common_t
*xscale
= armv4_5
->arch_info
;
822 scan_field_t fields
[2];
824 DEBUG("loading miniIC at 0x%8.8x", va
);
826 jtag_add_end_state(TAP_RTI
);
827 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.ldic
); /* LDIC */
829 /* CMD is b010 for Main IC and b011 for Mini IC */
831 buf_set_u32(&cmd
, 0, 3, 0x3);
833 buf_set_u32(&cmd
, 0, 3, 0x2);
835 buf_set_u32(&cmd
, 3, 3, 0x0);
837 /* virtual address of desired cache line */
838 buf_set_u32(packet
, 0, 27, va
>> 5);
840 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
841 fields
[0].num_bits
= 6;
842 fields
[0].out_value
= &cmd
;
843 fields
[0].out_mask
= NULL
;
844 fields
[0].in_value
= NULL
;
845 fields
[0].in_check_value
= NULL
;
846 fields
[0].in_check_mask
= NULL
;
847 fields
[0].in_handler
= NULL
;
848 fields
[0].in_handler_priv
= NULL
;
850 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
851 fields
[1].num_bits
= 27;
852 fields
[1].out_value
= packet
;
853 fields
[1].out_mask
= NULL
;
854 fields
[1].in_value
= NULL
;
855 fields
[1].in_check_value
= NULL
;
856 fields
[1].in_check_mask
= NULL
;
857 fields
[1].in_handler
= NULL
;
858 fields
[1].in_handler_priv
= NULL
;
860 jtag_add_dr_scan(2, fields
, -1);
862 fields
[0].num_bits
= 32;
863 fields
[0].out_value
= packet
;
865 fields
[1].num_bits
= 1;
866 fields
[1].out_value
= &cmd
;
868 for (word
= 0; word
< 8; word
++)
870 buf_set_u32(packet
, 0, 32, buffer
[word
]);
871 cmd
= parity(*((u32
*)packet
));
872 jtag_add_dr_scan(2, fields
, -1);
875 jtag_execute_queue();
880 int xscale_invalidate_ic_line(target_t
*target
, u32 va
)
882 armv4_5_common_t
*armv4_5
= target
->arch_info
;
883 xscale_common_t
*xscale
= armv4_5
->arch_info
;
887 scan_field_t fields
[2];
889 jtag_add_end_state(TAP_RTI
);
890 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.ldic
); /* LDIC */
892 /* CMD for invalidate IC line b000, bits [6:4] b000 */
893 buf_set_u32(&cmd
, 0, 6, 0x0);
895 /* virtual address of desired cache line */
896 buf_set_u32(packet
, 0, 27, va
>> 5);
898 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
899 fields
[0].num_bits
= 6;
900 fields
[0].out_value
= &cmd
;
901 fields
[0].out_mask
= NULL
;
902 fields
[0].in_value
= NULL
;
903 fields
[0].in_check_value
= NULL
;
904 fields
[0].in_check_mask
= NULL
;
905 fields
[0].in_handler
= NULL
;
906 fields
[0].in_handler_priv
= NULL
;
908 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
909 fields
[1].num_bits
= 27;
910 fields
[1].out_value
= packet
;
911 fields
[1].out_mask
= NULL
;
912 fields
[1].in_value
= NULL
;
913 fields
[1].in_check_value
= NULL
;
914 fields
[1].in_check_mask
= NULL
;
915 fields
[1].in_handler
= NULL
;
916 fields
[1].in_handler_priv
= NULL
;
918 jtag_add_dr_scan(2, fields
, -1);
923 int xscale_update_vectors(target_t
*target
)
925 armv4_5_common_t
*armv4_5
= target
->arch_info
;
926 xscale_common_t
*xscale
= armv4_5
->arch_info
;
930 u32 low_reset_branch
, high_reset_branch
;
932 for (i
= 1; i
< 8; i
++)
934 /* if there's a static vector specified for this exception, override */
935 if (xscale
->static_high_vectors_set
& (1 << i
))
937 xscale
->high_vectors
[i
] = xscale
->static_high_vectors
[i
];
941 retval
=target_read_u32(target
, 0xffff0000 + 4*i
, &xscale
->high_vectors
[i
]);
942 if (retval
== ERROR_TARGET_TIMEOUT
)
944 if (retval
!=ERROR_OK
)
946 /* Some of these reads will fail as part of normal execution */
947 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
952 for (i
= 1; i
< 8; i
++)
954 if (xscale
->static_low_vectors_set
& (1 << i
))
956 xscale
->low_vectors
[i
] = xscale
->static_low_vectors
[i
];
960 retval
=target_read_u32(target
, 0x0 + 4*i
, &xscale
->low_vectors
[i
]);
961 if (retval
== ERROR_TARGET_TIMEOUT
)
963 if (retval
!=ERROR_OK
)
965 /* Some of these reads will fail as part of normal execution */
966 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
971 /* calculate branches to debug handler */
972 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
973 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
975 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
976 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
978 /* invalidate and load exception vectors in mini i-cache */
979 xscale_invalidate_ic_line(target
, 0x0);
980 xscale_invalidate_ic_line(target
, 0xffff0000);
982 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
983 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
988 int xscale_arch_state(struct target_s
*target
)
990 armv4_5_common_t
*armv4_5
= target
->arch_info
;
991 xscale_common_t
*xscale
= armv4_5
->arch_info
;
995 "disabled", "enabled"
998 char *arch_dbg_reason
[] =
1000 "", "\n(processor reset)", "\n(trace buffer full)"
1003 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
1005 ERROR("BUG: called for a non-ARMv4/5 target");
1009 USER("target halted in %s state due to %s, current mode: %s\n"
1010 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
1011 "MMU: %s, D-Cache: %s, I-Cache: %s"
1013 armv4_5_state_strings
[armv4_5
->core_state
],
1014 target_debug_reason_strings
[target
->debug_reason
],
1015 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
1016 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
1017 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
1018 state
[xscale
->armv4_5_mmu
.mmu_enabled
],
1019 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
1020 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
],
1021 arch_dbg_reason
[xscale
->arch_debug_reason
]);
1026 int xscale_poll(target_t
*target
)
1028 int retval
=ERROR_OK
;
1029 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1030 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1032 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_DEBUG_RUNNING
))
1034 enum target_state previous_state
= target
->state
;
1035 if ((retval
= xscale_read_tx(target
, 0)) == ERROR_OK
)
1038 /* there's data to read from the tx register, we entered debug state */
1039 xscale
->handler_running
= 1;
1041 target
->state
= TARGET_HALTED
;
1043 /* process debug entry, fetching current mode regs */
1044 retval
= xscale_debug_entry(target
);
1046 else if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1048 USER("error while polling TX register, reset CPU");
1049 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
1050 target
->state
= TARGET_HALTED
;
1053 /* debug_entry could have overwritten target state (i.e. immediate resume)
1054 * don't signal event handlers in that case
1056 if (target
->state
!= TARGET_HALTED
)
1059 /* if target was running, signal that we halted
1060 * otherwise we reentered from debug execution */
1061 if (previous_state
== TARGET_RUNNING
)
1062 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1064 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
1070 int xscale_debug_entry(target_t
*target
)
1072 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1073 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1081 /* clear external dbg break (will be written on next DCSR read) */
1082 xscale
->external_debug_break
= 0;
1083 if ((retval
=xscale_read_dcsr(target
))!=ERROR_OK
)
1086 /* get r0, pc, r1 to r7 and cpsr */
1087 if ((retval
=xscale_receive(target
, buffer
, 10))!=ERROR_OK
)
1090 /* move r0 from buffer to register cache */
1091 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, buffer
[0]);
1092 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1093 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1094 DEBUG("r0: 0x%8.8x", buffer
[0]);
1096 /* move pc from buffer to register cache */
1097 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, buffer
[1]);
1098 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1099 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1100 DEBUG("pc: 0x%8.8x", buffer
[1]);
1102 /* move data from buffer to register cache */
1103 for (i
= 1; i
<= 7; i
++)
1105 buf_set_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32, buffer
[1 + i
]);
1106 armv4_5
->core_cache
->reg_list
[i
].dirty
= 1;
1107 armv4_5
->core_cache
->reg_list
[i
].valid
= 1;
1108 DEBUG("r%i: 0x%8.8x", i
, buffer
[i
+ 1]);
1111 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, buffer
[9]);
1112 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
1113 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1114 DEBUG("cpsr: 0x%8.8x", buffer
[9]);
1116 armv4_5
->core_mode
= buffer
[9] & 0x1f;
1117 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
1119 target
->state
= TARGET_UNKNOWN
;
1120 ERROR("cpsr contains invalid mode value - communication failure");
1121 return ERROR_TARGET_FAILURE
;
1123 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
1125 if (buffer
[9] & 0x20)
1126 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1128 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1130 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1131 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
1133 xscale_receive(target
, buffer
, 8);
1134 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1135 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1136 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1140 /* r8 to r14, but no spsr */
1141 xscale_receive(target
, buffer
, 7);
1144 /* move data from buffer to register cache */
1145 for (i
= 8; i
<= 14; i
++)
1147 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, buffer
[i
- 8]);
1148 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1149 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1152 /* examine debug reason */
1153 xscale_read_dcsr(target
);
1154 moe
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 2, 3);
1156 /* stored PC (for calculating fixup) */
1157 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1161 case 0x0: /* Processor reset */
1162 target
->debug_reason
= DBG_REASON_DBGRQ
;
1163 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_RESET
;
1166 case 0x1: /* Instruction breakpoint hit */
1167 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1168 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1171 case 0x2: /* Data breakpoint hit */
1172 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1173 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1176 case 0x3: /* BKPT instruction executed */
1177 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1178 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1181 case 0x4: /* Ext. debug event */
1182 target
->debug_reason
= DBG_REASON_DBGRQ
;
1183 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1186 case 0x5: /* Vector trap occured */
1187 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1188 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1191 case 0x6: /* Trace buffer full break */
1192 target
->debug_reason
= DBG_REASON_DBGRQ
;
1193 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_TB_FULL
;
1196 case 0x7: /* Reserved */
1198 ERROR("Method of Entry is 'Reserved'");
1203 /* apply PC fixup */
1204 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
1206 /* on the first debug entry, identify cache type */
1207 if (xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
1211 /* read cp15 cache type register */
1212 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
]);
1213 cache_type_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
].value
, 0, 32);
1215 armv4_5_identify_cache(cache_type_reg
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
1218 /* examine MMU and Cache settings */
1219 /* read cp15 control register */
1220 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1221 xscale
->cp15_control_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1222 xscale
->armv4_5_mmu
.mmu_enabled
= (xscale
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1223 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (xscale
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1224 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (xscale
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1226 /* tracing enabled, read collected trace data */
1227 if (xscale
->trace
.buffer_enabled
)
1229 xscale_read_trace(target
);
1230 xscale
->trace
.buffer_fill
--;
1232 /* resume if we're still collecting trace data */
1233 if ((xscale
->arch_debug_reason
== XSCALE_DBG_REASON_TB_FULL
)
1234 && (xscale
->trace
.buffer_fill
> 0))
1236 xscale_resume(target
, 1, 0x0, 1, 0);
1240 xscale
->trace
.buffer_enabled
= 0;
1247 int xscale_halt(target_t
*target
)
1249 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1250 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1252 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
1254 if (target
->state
== TARGET_HALTED
)
1256 WARNING("target was already halted");
1259 else if (target
->state
== TARGET_UNKNOWN
)
1261 /* this must not happen for a xscale target */
1262 ERROR("target was in unknown state when halt was requested");
1263 return ERROR_TARGET_INVALID
;
1265 else if (target
->state
== TARGET_RESET
)
1267 DEBUG("target->state == TARGET_RESET");
1271 /* assert external dbg break */
1272 xscale
->external_debug_break
= 1;
1273 xscale_read_dcsr(target
);
1275 target
->debug_reason
= DBG_REASON_DBGRQ
;
1281 int xscale_enable_single_step(struct target_s
*target
, u32 next_pc
)
1283 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1284 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1285 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1287 if (xscale
->ibcr0_used
)
1289 breakpoint_t
*ibcr0_bp
= breakpoint_find(target
, buf_get_u32(ibcr0
->value
, 0, 32) & 0xfffffffe);
1293 xscale_unset_breakpoint(target
, ibcr0_bp
);
1297 ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1302 xscale_set_reg_u32(ibcr0
, next_pc
| 0x1);
1307 int xscale_disable_single_step(struct target_s
*target
)
1309 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1310 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1311 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1313 xscale_set_reg_u32(ibcr0
, 0x0);
1318 int xscale_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
1320 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1321 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1322 breakpoint_t
*breakpoint
= target
->breakpoints
;
1331 if (target
->state
!= TARGET_HALTED
)
1333 WARNING("target not halted");
1334 return ERROR_TARGET_NOT_HALTED
;
1337 if (!debug_execution
)
1339 target_free_all_working_areas(target
);
1342 /* update vector tables */
1343 if ((retval
=xscale_update_vectors(target
))!=ERROR_OK
)
1346 /* current = 1: continue on current pc, otherwise continue at <address> */
1348 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1350 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1352 /* if we're at the reset vector, we have to simulate the branch */
1353 if (current_pc
== 0x0)
1355 arm_simulate_step(target
, NULL
);
1356 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1359 /* the front-end may request us not to handle breakpoints */
1360 if (handle_breakpoints
)
1362 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1366 /* there's a breakpoint at the current PC, we have to step over it */
1367 DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1368 xscale_unset_breakpoint(target
, breakpoint
);
1370 /* calculate PC of next instruction */
1371 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1374 target_read_u32(target
, current_pc
, ¤t_opcode
);
1375 ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode
);
1378 DEBUG("enable single-step");
1379 xscale_enable_single_step(target
, next_pc
);
1381 /* restore banked registers */
1382 xscale_restore_context(target
);
1384 /* send resume request (command 0x30 or 0x31)
1385 * clean the trace buffer if it is to be enabled (0x62) */
1386 if (xscale
->trace
.buffer_enabled
)
1388 xscale_send_u32(target
, 0x62);
1389 xscale_send_u32(target
, 0x31);
1392 xscale_send_u32(target
, 0x30);
1395 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1396 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1398 for (i
= 7; i
>= 0; i
--)
1401 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1402 DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1406 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1407 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1409 /* wait for and process debug entry */
1410 xscale_debug_entry(target
);
1412 DEBUG("disable single-step");
1413 xscale_disable_single_step(target
);
1415 DEBUG("set breakpoint at 0x%8.8x", breakpoint
->address
);
1416 xscale_set_breakpoint(target
, breakpoint
);
1420 /* enable any pending breakpoints and watchpoints */
1421 xscale_enable_breakpoints(target
);
1422 xscale_enable_watchpoints(target
);
1424 /* restore banked registers */
1425 xscale_restore_context(target
);
1427 /* send resume request (command 0x30 or 0x31)
1428 * clean the trace buffer if it is to be enabled (0x62) */
1429 if (xscale
->trace
.buffer_enabled
)
1431 xscale_send_u32(target
, 0x62);
1432 xscale_send_u32(target
, 0x31);
1435 xscale_send_u32(target
, 0x30);
1438 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1439 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1441 for (i
= 7; i
>= 0; i
--)
1444 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1445 DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1449 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1450 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1452 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1454 if (!debug_execution
)
1456 /* registers are now invalid */
1457 armv4_5_invalidate_core_regs(target
);
1458 target
->state
= TARGET_RUNNING
;
1459 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1463 target
->state
= TARGET_DEBUG_RUNNING
;
1464 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1467 DEBUG("target resumed");
1469 xscale
->handler_running
= 1;
1474 int xscale_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1476 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1477 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1478 breakpoint_t
*breakpoint
= target
->breakpoints
;
1480 u32 current_pc
, next_pc
;
1484 if (target
->state
!= TARGET_HALTED
)
1486 WARNING("target not halted");
1487 return ERROR_TARGET_NOT_HALTED
;
1490 /* current = 1: continue on current pc, otherwise continue at <address> */
1492 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1494 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1496 /* if we're at the reset vector, we have to simulate the step */
1497 if (current_pc
== 0x0)
1499 arm_simulate_step(target
, NULL
);
1500 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1502 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1503 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1508 /* the front-end may request us not to handle breakpoints */
1509 if (handle_breakpoints
)
1510 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1512 xscale_unset_breakpoint(target
, breakpoint
);
1515 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1517 /* calculate PC of next instruction */
1518 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1521 target_read_u32(target
, current_pc
, ¤t_opcode
);
1522 ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode
);
1525 DEBUG("enable single-step");
1526 xscale_enable_single_step(target
, next_pc
);
1528 /* restore banked registers */
1529 xscale_restore_context(target
);
1531 /* send resume request (command 0x30 or 0x31)
1532 * clean the trace buffer if it is to be enabled (0x62) */
1533 if (xscale
->trace
.buffer_enabled
)
1535 xscale_send_u32(target
, 0x62);
1536 xscale_send_u32(target
, 0x31);
1539 xscale_send_u32(target
, 0x30);
1542 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1543 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1545 for (i
= 7; i
>= 0; i
--)
1548 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1549 DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1553 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1554 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1556 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1558 /* registers are now invalid */
1559 armv4_5_invalidate_core_regs(target
);
1561 /* wait for and process debug entry */
1562 xscale_debug_entry(target
);
1564 DEBUG("disable single-step");
1565 xscale_disable_single_step(target
);
1567 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1571 xscale_set_breakpoint(target
, breakpoint
);
1574 DEBUG("target stepped");
1580 int xscale_assert_reset(target_t
*target
)
1582 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1583 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1585 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
1587 /* TRST every time. We want to be able to support daemon_startup attach */
1588 jtag_add_reset(1, 0);
1589 jtag_add_sleep(5000);
1590 jtag_add_reset(0, 0);
1591 jtag_add_sleep(5000);
1592 jtag_execute_queue();
1596 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1597 * end up in T-L-R, which would reset JTAG
1599 jtag_add_end_state(TAP_RTI
);
1600 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dcsr
);
1602 /* set Hold reset, Halt mode and Trap Reset */
1603 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1604 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1605 xscale_write_dcsr(target
, 1, 0);
1607 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1608 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, 0x7f);
1609 jtag_execute_queue();
1612 jtag_add_reset(0, 1);
1614 /* sleep 1ms, to be sure we fulfill any requirements */
1615 jtag_add_sleep(1000);
1616 jtag_execute_queue();
1618 target
->state
= TARGET_RESET
;
1623 int xscale_deassert_reset(target_t
*target
)
1625 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1626 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1628 fileio_t debug_handler
;
1636 breakpoint_t
*breakpoint
= target
->breakpoints
;
1640 xscale
->ibcr_available
= 2;
1641 xscale
->ibcr0_used
= 0;
1642 xscale
->ibcr1_used
= 0;
1644 xscale
->dbr_available
= 2;
1645 xscale
->dbr0_used
= 0;
1646 xscale
->dbr1_used
= 0;
1648 /* mark all hardware breakpoints as unset */
1651 if (breakpoint
->type
== BKPT_HARD
)
1653 breakpoint
->set
= 0;
1655 breakpoint
= breakpoint
->next
;
1658 if (!xscale
->handler_installed
)
1661 jtag_add_reset(0, 0);
1663 /* wait 300ms; 150 and 100ms were not enough */
1664 jtag_add_sleep(300*1000);
1666 jtag_add_runtest(2030, TAP_RTI
);
1667 jtag_execute_queue();
1669 /* set Hold reset, Halt mode and Trap Reset */
1670 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1671 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1672 xscale_write_dcsr(target
, 1, 0);
1674 /* Load debug handler */
1675 if (fileio_open(&debug_handler
, "xscale/debug_handler.bin", FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1680 if ((binary_size
= debug_handler
.size
) % 4)
1682 ERROR("debug_handler.bin: size not a multiple of 4");
1686 if (binary_size
> 0x800)
1688 ERROR("debug_handler.bin: larger than 2kb");
1692 binary_size
= CEIL(binary_size
, 32) * 32;
1694 address
= xscale
->handler_address
;
1695 while (binary_size
> 0)
1700 if ((retval
= fileio_read(&debug_handler
, 32, buffer
, &buf_cnt
)) != ERROR_OK
)
1705 for (i
= 0; i
< buf_cnt
; i
+= 4)
1707 /* convert LE buffer to host-endian u32 */
1708 cache_line
[i
/ 4] = le_to_h_u32(&buffer
[i
]);
1711 for (; buf_cnt
< 32; buf_cnt
+= 4)
1713 cache_line
[buf_cnt
/ 4] = 0xe1a08008;
1716 /* only load addresses other than the reset vectors */
1717 if ((address
% 0x400) != 0x0)
1719 xscale_load_ic(target
, 1, address
, cache_line
);
1723 binary_size
-= buf_cnt
;
1726 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
1727 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
1729 jtag_add_runtest(30, TAP_RTI
);
1731 jtag_add_sleep(100000);
1733 /* set Hold reset, Halt mode and Trap Reset */
1734 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1735 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1736 xscale_write_dcsr(target
, 1, 0);
1738 /* clear Hold reset to let the target run (should enter debug handler) */
1739 xscale_write_dcsr(target
, 0, 1);
1740 target
->state
= TARGET_RUNNING
;
1742 if ((target
->reset_mode
!= RESET_HALT
) && (target
->reset_mode
!= RESET_INIT
))
1744 jtag_add_sleep(10000);
1746 /* we should have entered debug now */
1747 xscale_debug_entry(target
);
1748 target
->state
= TARGET_HALTED
;
1750 /* resume the target */
1751 xscale_resume(target
, 1, 0x0, 1, 0);
1754 fileio_close(&debug_handler
);
1758 jtag_add_reset(0, 0);
1765 int xscale_soft_reset_halt(struct target_s
*target
)
1771 int xscale_prepare_reset_halt(struct target_s
*target
)
1773 /* nothing to be done for reset_halt on XScale targets
1774 * we always halt after a reset to upload the debug handler
1779 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
1785 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
)
1791 int xscale_full_context(target_t
*target
)
1793 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1801 if (target
->state
!= TARGET_HALTED
)
1803 WARNING("target not halted");
1804 return ERROR_TARGET_NOT_HALTED
;
1807 buffer
= malloc(4 * 8);
1809 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1810 * we can't enter User mode on an XScale (unpredictable),
1811 * but User shares registers with SYS
1813 for(i
= 1; i
< 7; i
++)
1817 /* check if there are invalid registers in the current mode
1819 for (j
= 0; j
<= 16; j
++)
1821 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1829 /* request banked registers */
1830 xscale_send_u32(target
, 0x0);
1833 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1834 tmp_cpsr
|= 0xc0; /* I/F bits */
1836 /* send CPSR for desired mode */
1837 xscale_send_u32(target
, tmp_cpsr
);
1839 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1840 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1842 xscale_receive(target
, buffer
, 8);
1843 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1844 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1845 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1849 xscale_receive(target
, buffer
, 7);
1852 /* move data from buffer to register cache */
1853 for (j
= 8; j
<= 14; j
++)
1855 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
, 0, 32, buffer
[j
- 8]);
1856 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1857 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1867 int xscale_restore_context(target_t
*target
)
1869 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1875 if (target
->state
!= TARGET_HALTED
)
1877 WARNING("target not halted");
1878 return ERROR_TARGET_NOT_HALTED
;
1881 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1882 * we can't enter User mode on an XScale (unpredictable),
1883 * but User shares registers with SYS
1885 for(i
= 1; i
< 7; i
++)
1889 /* check if there are invalid registers in the current mode
1891 for (j
= 8; j
<= 14; j
++)
1893 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
== 1)
1897 /* if not USR/SYS, check if the SPSR needs to be written */
1898 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1900 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
== 1)
1908 /* send banked registers */
1909 xscale_send_u32(target
, 0x1);
1912 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1913 tmp_cpsr
|= 0xc0; /* I/F bits */
1915 /* send CPSR for desired mode */
1916 xscale_send_u32(target
, tmp_cpsr
);
1918 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1919 for (j
= 8; j
<= 14; j
++)
1921 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, j
).value
, 0, 32));
1922 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1925 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1927 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32));
1928 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1936 int xscale_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1938 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1939 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1944 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1946 if (target
->state
!= TARGET_HALTED
)
1948 WARNING("target not halted");
1949 return ERROR_TARGET_NOT_HALTED
;
1952 /* sanitize arguments */
1953 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1954 return ERROR_INVALID_ARGUMENTS
;
1956 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1957 return ERROR_TARGET_UNALIGNED_ACCESS
;
1959 /* send memory read request (command 0x1n, n: access size) */
1960 if ((retval
=xscale_send_u32(target
, 0x10 | size
))!=ERROR_OK
)
1963 /* send base address for read request */
1964 if ((retval
=xscale_send_u32(target
, address
))!=ERROR_OK
)
1967 /* send number of requested data words */
1968 if ((retval
=xscale_send_u32(target
, count
))!=ERROR_OK
)
1971 /* receive data from target (count times 32-bit words in host endianness) */
1972 buf32
= malloc(4 * count
);
1973 if ((retval
=xscale_receive(target
, buf32
, count
))!=ERROR_OK
)
1976 /* extract data from host-endian buffer into byte stream */
1977 for (i
= 0; i
< count
; i
++)
1982 target_buffer_set_u32(target
, buffer
, buf32
[i
]);
1986 target_buffer_set_u16(target
, buffer
, buf32
[i
] & 0xffff);
1990 *buffer
++ = buf32
[i
] & 0xff;
1993 ERROR("should never get here");
2000 /* examine DCSR, to see if Sticky Abort (SA) got set */
2001 if ((retval
=xscale_read_dcsr(target
))!=ERROR_OK
)
2003 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
2006 if ((retval
=xscale_send_u32(target
, 0x60))!=ERROR_OK
)
2009 return ERROR_TARGET_DATA_ABORT
;
2015 int xscale_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
2017 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2018 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2021 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
2023 if (target
->state
!= TARGET_HALTED
)
2025 WARNING("target not halted");
2026 return ERROR_TARGET_NOT_HALTED
;
2029 /* sanitize arguments */
2030 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
2031 return ERROR_INVALID_ARGUMENTS
;
2033 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2034 return ERROR_TARGET_UNALIGNED_ACCESS
;
2036 /* send memory write request (command 0x2n, n: access size) */
2037 if ((retval
=xscale_send_u32(target
, 0x20 | size
))!=ERROR_OK
)
2040 /* send base address for read request */
2041 if ((retval
=xscale_send_u32(target
, address
))!=ERROR_OK
)
2044 /* send number of requested data words to be written*/
2045 if ((retval
=xscale_send_u32(target
, count
))!=ERROR_OK
)
2048 /* extract data from host-endian buffer into byte stream */
2050 for (i
= 0; i
< count
; i
++)
2055 value
= target_buffer_get_u32(target
, buffer
);
2056 xscale_send_u32(target
, value
);
2060 value
= target_buffer_get_u16(target
, buffer
);
2061 xscale_send_u32(target
, value
);
2066 xscale_send_u32(target
, value
);
2070 ERROR("should never get here");
2075 if ((retval
=xscale_send(target
, buffer
, count
, size
))!=ERROR_OK
)
2078 /* examine DCSR, to see if Sticky Abort (SA) got set */
2079 if ((retval
=xscale_read_dcsr(target
))!=ERROR_OK
)
2081 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
2084 if ((retval
=xscale_send_u32(target
, 0x60))!=ERROR_OK
)
2087 return ERROR_TARGET_DATA_ABORT
;
2093 int xscale_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
2095 return xscale_write_memory(target
, address
, 4, count
, buffer
);
2098 int xscale_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
2100 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2103 u32
xscale_get_ttb(target_t
*target
)
2105 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2106 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2109 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_TTB
]);
2110 ttb
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_TTB
].value
, 0, 32);
2115 void xscale_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2117 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2118 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2121 /* read cp15 control register */
2122 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2123 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2126 cp15_control
&= ~0x1U
;
2131 xscale_send_u32(target
, 0x50);
2132 xscale_send_u32(target
, xscale
->cache_clean_address
);
2134 /* invalidate DCache */
2135 xscale_send_u32(target
, 0x51);
2137 cp15_control
&= ~0x4U
;
2142 /* invalidate ICache */
2143 xscale_send_u32(target
, 0x52);
2144 cp15_control
&= ~0x1000U
;
2147 /* write new cp15 control register */
2148 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2150 /* execute cpwait to ensure outstanding operations complete */
2151 xscale_send_u32(target
, 0x53);
2154 void xscale_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2156 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2157 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2160 /* read cp15 control register */
2161 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2162 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2165 cp15_control
|= 0x1U
;
2168 cp15_control
|= 0x4U
;
2171 cp15_control
|= 0x1000U
;
2173 /* write new cp15 control register */
2174 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2176 /* execute cpwait to ensure outstanding operations complete */
2177 xscale_send_u32(target
, 0x53);
2180 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2182 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2183 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2185 if (target
->state
!= TARGET_HALTED
)
2187 WARNING("target not halted");
2188 return ERROR_TARGET_NOT_HALTED
;
2191 if (xscale
->force_hw_bkpts
)
2192 breakpoint
->type
= BKPT_HARD
;
2194 if (breakpoint
->set
)
2196 WARNING("breakpoint already set");
2200 if (breakpoint
->type
== BKPT_HARD
)
2202 u32 value
= breakpoint
->address
| 1;
2203 if (!xscale
->ibcr0_used
)
2205 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], value
);
2206 xscale
->ibcr0_used
= 1;
2207 breakpoint
->set
= 1; /* breakpoint set on first breakpoint register */
2209 else if (!xscale
->ibcr1_used
)
2211 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], value
);
2212 xscale
->ibcr1_used
= 1;
2213 breakpoint
->set
= 2; /* breakpoint set on second breakpoint register */
2217 ERROR("BUG: no hardware comparator available");
2221 else if (breakpoint
->type
== BKPT_SOFT
)
2223 if (breakpoint
->length
== 4)
2225 /* keep the original instruction in target endianness */
2226 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
2227 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2228 target_write_u32(target
, breakpoint
->address
, xscale
->arm_bkpt
);
2232 /* keep the original instruction in target endianness */
2233 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
2234 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2235 target_write_u32(target
, breakpoint
->address
, xscale
->thumb_bkpt
);
2237 breakpoint
->set
= 1;
2244 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2246 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2247 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2249 if (target
->state
!= TARGET_HALTED
)
2251 WARNING("target not halted");
2252 return ERROR_TARGET_NOT_HALTED
;
2255 if (xscale
->force_hw_bkpts
)
2257 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint
->address
);
2258 breakpoint
->type
= BKPT_HARD
;
2261 if ((breakpoint
->type
== BKPT_HARD
) && (xscale
->ibcr_available
< 1))
2263 INFO("no breakpoint unit available for hardware breakpoint");
2264 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2268 xscale
->ibcr_available
--;
2271 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
2273 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2274 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2280 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2282 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2283 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2285 if (target
->state
!= TARGET_HALTED
)
2287 WARNING("target not halted");
2288 return ERROR_TARGET_NOT_HALTED
;
2291 if (!breakpoint
->set
)
2293 WARNING("breakpoint not set");
2297 if (breakpoint
->type
== BKPT_HARD
)
2299 if (breakpoint
->set
== 1)
2301 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], 0x0);
2302 xscale
->ibcr0_used
= 0;
2304 else if (breakpoint
->set
== 2)
2306 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], 0x0);
2307 xscale
->ibcr1_used
= 0;
2309 breakpoint
->set
= 0;
2313 /* restore original instruction (kept in target endianness) */
2314 if (breakpoint
->length
== 4)
2316 target
->type
->write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
2320 target
->type
->write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
2322 breakpoint
->set
= 0;
2328 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2330 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2331 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2333 if (target
->state
!= TARGET_HALTED
)
2335 WARNING("target not halted");
2336 return ERROR_TARGET_NOT_HALTED
;
2339 if (breakpoint
->set
)
2341 xscale_unset_breakpoint(target
, breakpoint
);
2344 if (breakpoint
->type
== BKPT_HARD
)
2345 xscale
->ibcr_available
++;
2350 int xscale_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2352 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2353 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2355 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2356 u32 dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2358 if (target
->state
!= TARGET_HALTED
)
2360 WARNING("target not halted");
2361 return ERROR_TARGET_NOT_HALTED
;
2364 xscale_get_reg(dbcon
);
2366 switch (watchpoint
->rw
)
2378 ERROR("BUG: watchpoint->rw neither read, write nor access");
2381 if (!xscale
->dbr0_used
)
2383 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR0
], watchpoint
->address
);
2384 dbcon_value
|= enable
;
2385 xscale_set_reg_u32(dbcon
, dbcon_value
);
2386 watchpoint
->set
= 1;
2387 xscale
->dbr0_used
= 1;
2389 else if (!xscale
->dbr1_used
)
2391 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
], watchpoint
->address
);
2392 dbcon_value
|= enable
<< 2;
2393 xscale_set_reg_u32(dbcon
, dbcon_value
);
2394 watchpoint
->set
= 2;
2395 xscale
->dbr1_used
= 1;
2399 ERROR("BUG: no hardware comparator available");
2406 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2408 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2409 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2411 if (target
->state
!= TARGET_HALTED
)
2413 WARNING("target not halted");
2414 return ERROR_TARGET_NOT_HALTED
;
2417 if (xscale
->dbr_available
< 1)
2419 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2422 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
2424 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2427 xscale
->dbr_available
--;
2432 int xscale_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2434 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2435 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2436 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2437 u32 dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2439 if (target
->state
!= TARGET_HALTED
)
2441 WARNING("target not halted");
2442 return ERROR_TARGET_NOT_HALTED
;
2445 if (!watchpoint
->set
)
2447 WARNING("breakpoint not set");
2451 if (watchpoint
->set
== 1)
2453 dbcon_value
&= ~0x3;
2454 xscale_set_reg_u32(dbcon
, dbcon_value
);
2455 xscale
->dbr0_used
= 0;
2457 else if (watchpoint
->set
== 2)
2459 dbcon_value
&= ~0xc;
2460 xscale_set_reg_u32(dbcon
, dbcon_value
);
2461 xscale
->dbr1_used
= 0;
2463 watchpoint
->set
= 0;
2468 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2470 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2471 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2473 if (target
->state
!= TARGET_HALTED
)
2475 WARNING("target not halted");
2476 return ERROR_TARGET_NOT_HALTED
;
2479 if (watchpoint
->set
)
2481 xscale_unset_watchpoint(target
, watchpoint
);
2484 xscale
->dbr_available
++;
2489 void xscale_enable_watchpoints(struct target_s
*target
)
2491 watchpoint_t
*watchpoint
= target
->watchpoints
;
2495 if (watchpoint
->set
== 0)
2496 xscale_set_watchpoint(target
, watchpoint
);
2497 watchpoint
= watchpoint
->next
;
2501 void xscale_enable_breakpoints(struct target_s
*target
)
2503 breakpoint_t
*breakpoint
= target
->breakpoints
;
2505 /* set any pending breakpoints */
2508 if (breakpoint
->set
== 0)
2509 xscale_set_breakpoint(target
, breakpoint
);
2510 breakpoint
= breakpoint
->next
;
2514 int xscale_get_reg(reg_t
*reg
)
2516 xscale_reg_t
*arch_info
= reg
->arch_info
;
2517 target_t
*target
= arch_info
->target
;
2518 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2519 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2521 /* DCSR, TX and RX are accessible via JTAG */
2522 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2524 return xscale_read_dcsr(arch_info
->target
);
2526 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2528 /* 1 = consume register content */
2529 return xscale_read_tx(arch_info
->target
, 1);
2531 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2533 /* can't read from RX register (host -> debug handler) */
2536 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2538 /* can't (explicitly) read from TXRXCTRL register */
2541 else /* Other DBG registers have to be transfered by the debug handler */
2543 /* send CP read request (command 0x40) */
2544 xscale_send_u32(target
, 0x40);
2546 /* send CP register number */
2547 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2549 /* read register value */
2550 xscale_read_tx(target
, 1);
2551 buf_cpy(xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
, reg
->value
, 32);
2560 int xscale_set_reg(reg_t
*reg
, u8
* buf
)
2562 xscale_reg_t
*arch_info
= reg
->arch_info
;
2563 target_t
*target
= arch_info
->target
;
2564 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2565 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2566 u32 value
= buf_get_u32(buf
, 0, 32);
2568 /* DCSR, TX and RX are accessible via JTAG */
2569 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2571 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32, value
);
2572 return xscale_write_dcsr(arch_info
->target
, -1, -1);
2574 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2576 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
2577 return xscale_write_rx(arch_info
->target
);
2579 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2581 /* can't write to TX register (debug-handler -> host) */
2584 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2586 /* can't (explicitly) write to TXRXCTRL register */
2589 else /* Other DBG registers have to be transfered by the debug handler */
2591 /* send CP write request (command 0x41) */
2592 xscale_send_u32(target
, 0x41);
2594 /* send CP register number */
2595 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2597 /* send CP register value */
2598 xscale_send_u32(target
, value
);
2599 buf_set_u32(reg
->value
, 0, 32, value
);
2605 /* convenience wrapper to access XScale specific registers */
2606 int xscale_set_reg_u32(reg_t
*reg
, u32 value
)
2610 buf_set_u32(buf
, 0, 32, value
);
2612 return xscale_set_reg(reg
, buf
);
2615 int xscale_write_dcsr_sw(target_t
*target
, u32 value
)
2617 /* get pointers to arch-specific information */
2618 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2619 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2620 reg_t
*dcsr
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
2621 xscale_reg_t
*dcsr_arch_info
= dcsr
->arch_info
;
2623 /* send CP write request (command 0x41) */
2624 xscale_send_u32(target
, 0x41);
2626 /* send CP register number */
2627 xscale_send_u32(target
, dcsr_arch_info
->dbg_handler_number
);
2629 /* send CP register value */
2630 xscale_send_u32(target
, value
);
2631 buf_set_u32(dcsr
->value
, 0, 32, value
);
2636 int xscale_read_trace(target_t
*target
)
2638 /* get pointers to arch-specific information */
2639 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2640 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2641 xscale_trace_data_t
**trace_data_p
;
2643 /* 258 words from debug handler
2644 * 256 trace buffer entries
2645 * 2 checkpoint addresses
2647 u32 trace_buffer
[258];
2648 int is_address
[256];
2651 if (target
->state
!= TARGET_HALTED
)
2653 WARNING("target must be stopped to read trace data");
2654 return ERROR_TARGET_NOT_HALTED
;
2657 /* send read trace buffer command (command 0x61) */
2658 xscale_send_u32(target
, 0x61);
2660 /* receive trace buffer content */
2661 xscale_receive(target
, trace_buffer
, 258);
2663 /* parse buffer backwards to identify address entries */
2664 for (i
= 255; i
>= 0; i
--)
2667 if (((trace_buffer
[i
] & 0xf0) == 0x90) ||
2668 ((trace_buffer
[i
] & 0xf0) == 0xd0))
2671 is_address
[--i
] = 1;
2673 is_address
[--i
] = 1;
2675 is_address
[--i
] = 1;
2677 is_address
[--i
] = 1;
2682 /* search first non-zero entry */
2683 for (j
= 0; (j
< 256) && (trace_buffer
[j
] == 0) && (!is_address
[j
]); j
++)
2688 DEBUG("no trace data collected");
2689 return ERROR_XSCALE_NO_TRACE_DATA
;
2692 for (trace_data_p
= &xscale
->trace
.data
; *trace_data_p
; trace_data_p
= &(*trace_data_p
)->next
)
2695 *trace_data_p
= malloc(sizeof(xscale_trace_data_t
));
2696 (*trace_data_p
)->next
= NULL
;
2697 (*trace_data_p
)->chkpt0
= trace_buffer
[256];
2698 (*trace_data_p
)->chkpt1
= trace_buffer
[257];
2699 (*trace_data_p
)->last_instruction
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2700 (*trace_data_p
)->entries
= malloc(sizeof(xscale_trace_entry_t
) * (256 - j
));
2701 (*trace_data_p
)->depth
= 256 - j
;
2703 for (i
= j
; i
< 256; i
++)
2705 (*trace_data_p
)->entries
[i
- j
].data
= trace_buffer
[i
];
2707 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_ADDRESS
;
2709 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_MESSAGE
;
2715 int xscale_read_instruction(target_t
*target
, arm_instruction_t
*instruction
)
2717 /* get pointers to arch-specific information */
2718 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2719 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2726 if (!xscale
->trace
.image
)
2727 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
2729 /* search for the section the current instruction belongs to */
2730 for (i
= 0; i
< xscale
->trace
.image
->num_sections
; i
++)
2732 if ((xscale
->trace
.image
->sections
[i
].base_address
<= xscale
->trace
.current_pc
) &&
2733 (xscale
->trace
.image
->sections
[i
].base_address
+ xscale
->trace
.image
->sections
[i
].size
> xscale
->trace
.current_pc
))
2742 /* current instruction couldn't be found in the image */
2743 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2746 if (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
)
2749 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2750 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2751 4, buf
, &size_read
)) != ERROR_OK
)
2753 ERROR("error while reading instruction: %i", retval
);
2754 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2756 opcode
= target_buffer_get_u32(target
, buf
);
2757 arm_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2759 else if (xscale
->trace
.core_state
== ARMV4_5_STATE_THUMB
)
2762 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2763 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2764 2, buf
, &size_read
)) != ERROR_OK
)
2766 ERROR("error while reading instruction: %i", retval
);
2767 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2769 opcode
= target_buffer_get_u16(target
, buf
);
2770 thumb_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2774 ERROR("BUG: unknown core state encountered");
2781 int xscale_branch_address(xscale_trace_data_t
*trace_data
, int i
, u32
*target
)
2783 /* if there are less than four entries prior to the indirect branch message
2784 * we can't extract the address */
2790 *target
= (trace_data
->entries
[i
-1].data
) | (trace_data
->entries
[i
-2].data
<< 8) |
2791 (trace_data
->entries
[i
-3].data
<< 16) | (trace_data
->entries
[i
-4].data
<< 24);
2796 int xscale_analyze_trace(target_t
*target
, command_context_t
*cmd_ctx
)
2798 /* get pointers to arch-specific information */
2799 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2800 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2803 xscale_trace_data_t
*trace_data
= xscale
->trace
.data
;
2812 xscale
->trace
.core_state
= ARMV4_5_STATE_ARM
;
2817 for (i
= 0; i
< trace_data
->depth
; i
++)
2823 if (trace_data
->entries
[i
].type
== XSCALE_TRACE_ADDRESS
)
2826 switch ((trace_data
->entries
[i
].data
& 0xf0) >> 4)
2828 case 0: /* Exceptions */
2836 exception
= (trace_data
->entries
[i
].data
& 0x70) >> 4;
2838 next_pc
= (trace_data
->entries
[i
].data
& 0xf0) >> 2;
2839 command_print(cmd_ctx
, "--- exception %i ---", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2841 case 8: /* Direct Branch */
2844 case 9: /* Indirect Branch */
2846 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2851 case 13: /* Checkpointed Indirect Branch */
2852 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2855 if (((chkpt
== 0) && (next_pc
!= trace_data
->chkpt0
))
2856 || ((chkpt
== 1) && (next_pc
!= trace_data
->chkpt1
)))
2857 WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2859 /* explicit fall-through */
2860 case 12: /* Checkpointed Direct Branch */
2865 next_pc
= trace_data
->chkpt0
;
2868 else if (chkpt
== 1)
2871 next_pc
= trace_data
->chkpt0
;
2876 WARNING("more than two checkpointed branches encountered");
2879 case 15: /* Roll-over */
2882 default: /* Reserved */
2883 command_print(cmd_ctx
, "--- reserved trace message ---");
2884 ERROR("BUG: trace message %i is reserved", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2888 if (xscale
->trace
.pc_ok
)
2890 int executed
= (trace_data
->entries
[i
].data
& 0xf) + rollover
* 16;
2891 arm_instruction_t instruction
;
2893 if ((exception
== 6) || (exception
== 7))
2895 /* IRQ or FIQ exception, no instruction executed */
2899 while (executed
-- >= 0)
2901 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2903 /* can't continue tracing with no image available */
2904 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2908 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2910 /* TODO: handle incomplete images */
2914 /* a precise abort on a load to the PC is included in the incremental
2915 * word count, other instructions causing data aborts are not included
2917 if ((executed
== 0) && (exception
== 4)
2918 && ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDM
)))
2920 if ((instruction
.type
== ARM_LDM
)
2921 && ((instruction
.info
.load_store_multiple
.register_list
& 0x8000) == 0))
2925 else if (((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDRSH
))
2926 && (instruction
.info
.load_store
.Rd
!= 15))
2932 /* only the last instruction executed
2933 * (the one that caused the control flow change)
2934 * could be a taken branch
2936 if (((executed
== -1) && (branch
== 1)) &&
2937 (((instruction
.type
== ARM_B
) ||
2938 (instruction
.type
== ARM_BL
) ||
2939 (instruction
.type
== ARM_BLX
)) &&
2940 (instruction
.info
.b_bl_bx_blx
.target_address
!= -1)))
2942 xscale
->trace
.current_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
2946 xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
2948 command_print(cmd_ctx
, "%s", instruction
.text
);
2956 xscale
->trace
.current_pc
= next_pc
;
2957 xscale
->trace
.pc_ok
= 1;
2961 for (; xscale
->trace
.current_pc
< trace_data
->last_instruction
; xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2)
2963 arm_instruction_t instruction
;
2964 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2966 /* can't continue tracing with no image available */
2967 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2971 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2973 /* TODO: handle incomplete images */
2976 command_print(cmd_ctx
, "%s", instruction
.text
);
2979 trace_data
= trace_data
->next
;
2985 void xscale_build_reg_cache(target_t
*target
)
2987 /* get pointers to arch-specific information */
2988 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2989 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2991 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2992 xscale_reg_t
*arch_info
= malloc(sizeof(xscale_reg_arch_info
));
2994 int num_regs
= sizeof(xscale_reg_arch_info
) / sizeof(xscale_reg_t
);
2996 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
2997 armv4_5
->core_cache
= (*cache_p
);
2999 /* register a register arch-type for XScale dbg registers only once */
3000 if (xscale_reg_arch_type
== -1)
3001 xscale_reg_arch_type
= register_reg_arch_type(xscale_get_reg
, xscale_set_reg
);
3003 (*cache_p
)->next
= malloc(sizeof(reg_cache_t
));
3004 cache_p
= &(*cache_p
)->next
;
3006 /* fill in values for the xscale reg cache */
3007 (*cache_p
)->name
= "XScale registers";
3008 (*cache_p
)->next
= NULL
;
3009 (*cache_p
)->reg_list
= malloc(num_regs
* sizeof(reg_t
));
3010 (*cache_p
)->num_regs
= num_regs
;
3012 for (i
= 0; i
< num_regs
; i
++)
3014 (*cache_p
)->reg_list
[i
].name
= xscale_reg_list
[i
];
3015 (*cache_p
)->reg_list
[i
].value
= calloc(4, 1);
3016 (*cache_p
)->reg_list
[i
].dirty
= 0;
3017 (*cache_p
)->reg_list
[i
].valid
= 0;
3018 (*cache_p
)->reg_list
[i
].size
= 32;
3019 (*cache_p
)->reg_list
[i
].bitfield_desc
= NULL
;
3020 (*cache_p
)->reg_list
[i
].num_bitfields
= 0;
3021 (*cache_p
)->reg_list
[i
].arch_info
= &arch_info
[i
];
3022 (*cache_p
)->reg_list
[i
].arch_type
= xscale_reg_arch_type
;
3023 arch_info
[i
] = xscale_reg_arch_info
[i
];
3024 arch_info
[i
].target
= target
;
3027 xscale
->reg_cache
= (*cache_p
);
3030 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
3041 int xscale_init_arch_info(target_t
*target
, xscale_common_t
*xscale
, int chain_pos
, char *variant
)
3043 armv4_5_common_t
*armv4_5
;
3044 u32 high_reset_branch
, low_reset_branch
;
3047 armv4_5
= &xscale
->armv4_5_common
;
3049 /* store architecture specfic data (none so far) */
3050 xscale
->arch_info
= NULL
;
3051 xscale
->common_magic
= XSCALE_COMMON_MAGIC
;
3053 /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
3054 xscale
->variant
= strdup(variant
);
3056 /* prepare JTAG information for the new target */
3057 xscale
->jtag_info
.chain_pos
= chain_pos
;
3059 xscale
->jtag_info
.dbgrx
= 0x02;
3060 xscale
->jtag_info
.dbgtx
= 0x10;
3061 xscale
->jtag_info
.dcsr
= 0x09;
3062 xscale
->jtag_info
.ldic
= 0x07;
3064 if ((strcmp(xscale
->variant
, "pxa250") == 0) ||
3065 (strcmp(xscale
->variant
, "pxa255") == 0) ||
3066 (strcmp(xscale
->variant
, "pxa26x") == 0))
3068 xscale
->jtag_info
.ir_length
= 5;
3070 else if ((strcmp(xscale
->variant
, "pxa27x") == 0) ||
3071 (strcmp(xscale
->variant
, "ixp42x") == 0) ||
3072 (strcmp(xscale
->variant
, "ixp45x") == 0) ||
3073 (strcmp(xscale
->variant
, "ixp46x") == 0))
3075 xscale
->jtag_info
.ir_length
= 7;
3078 /* the debug handler isn't installed (and thus not running) at this time */
3079 xscale
->handler_installed
= 0;
3080 xscale
->handler_running
= 0;
3081 xscale
->handler_address
= 0xfe000800;
3083 /* clear the vectors we keep locally for reference */
3084 memset(xscale
->low_vectors
, 0, sizeof(xscale
->low_vectors
));
3085 memset(xscale
->high_vectors
, 0, sizeof(xscale
->high_vectors
));
3087 /* no user-specified vectors have been configured yet */
3088 xscale
->static_low_vectors_set
= 0x0;
3089 xscale
->static_high_vectors_set
= 0x0;
3091 /* calculate branches to debug handler */
3092 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
3093 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
3095 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
3096 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
3098 for (i
= 1; i
<= 7; i
++)
3100 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3101 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3104 /* 64kB aligned region used for DCache cleaning */
3105 xscale
->cache_clean_address
= 0xfffe0000;
3107 xscale
->hold_rst
= 0;
3108 xscale
->external_debug_break
= 0;
3110 xscale
->force_hw_bkpts
= 1;
3112 xscale
->ibcr_available
= 2;
3113 xscale
->ibcr0_used
= 0;
3114 xscale
->ibcr1_used
= 0;
3116 xscale
->dbr_available
= 2;
3117 xscale
->dbr0_used
= 0;
3118 xscale
->dbr1_used
= 0;
3120 xscale
->arm_bkpt
= ARMV5_BKPT(0x0);
3121 xscale
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
3123 xscale
->vector_catch
= 0x1;
3125 xscale
->trace
.capture_status
= TRACE_IDLE
;
3126 xscale
->trace
.data
= NULL
;
3127 xscale
->trace
.image
= NULL
;
3128 xscale
->trace
.buffer_enabled
= 0;
3129 xscale
->trace
.buffer_fill
= 0;
3131 /* prepare ARMv4/5 specific information */
3132 armv4_5
->arch_info
= xscale
;
3133 armv4_5
->read_core_reg
= xscale_read_core_reg
;
3134 armv4_5
->write_core_reg
= xscale_write_core_reg
;
3135 armv4_5
->full_context
= xscale_full_context
;
3137 armv4_5_init_arch_info(target
, armv4_5
);
3139 xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
3140 xscale
->armv4_5_mmu
.get_ttb
= xscale_get_ttb
;
3141 xscale
->armv4_5_mmu
.read_memory
= xscale_read_memory
;
3142 xscale
->armv4_5_mmu
.write_memory
= xscale_write_memory
;
3143 xscale
->armv4_5_mmu
.disable_mmu_caches
= xscale_disable_mmu_caches
;
3144 xscale
->armv4_5_mmu
.enable_mmu_caches
= xscale_enable_mmu_caches
;
3145 xscale
->armv4_5_mmu
.has_tiny_pages
= 1;
3146 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3148 xscale
->fast_memory_access
= 0;
3153 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
3154 int xscale_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
3157 char *variant
= NULL
;
3158 xscale_common_t
*xscale
= malloc(sizeof(xscale_common_t
));
3159 memset(xscale
, 0, sizeof(*xscale
));
3163 ERROR("'target xscale' requires four arguments: <endianess> <startup_mode> <chain_pos> <variant>");
3167 chain_pos
= strtoul(args
[3], NULL
, 0);
3171 xscale_init_arch_info(target
, xscale
, chain_pos
, variant
);
3172 xscale_build_reg_cache(target
);
3177 int xscale_handle_debug_handler_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3179 target_t
*target
= NULL
;
3180 armv4_5_common_t
*armv4_5
;
3181 xscale_common_t
*xscale
;
3183 u32 handler_address
;
3187 ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3191 if ((target
= get_target_by_num(strtoul(args
[0], NULL
, 0))) == NULL
)
3193 ERROR("no target '%s' configured", args
[0]);
3197 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3202 handler_address
= strtoul(args
[1], NULL
, 0);
3204 if (((handler_address
>= 0x800) && (handler_address
<= 0x1fef800)) ||
3205 ((handler_address
>= 0xfe000800) && (handler_address
<= 0xfffff800)))
3207 xscale
->handler_address
= handler_address
;
3211 ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3217 int xscale_handle_cache_clean_address_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3219 target_t
*target
= NULL
;
3220 armv4_5_common_t
*armv4_5
;
3221 xscale_common_t
*xscale
;
3223 u32 cache_clean_address
;
3227 ERROR("'xscale cache_clean_address <target#> <address>' command takes two required operands");
3231 if ((target
= get_target_by_num(strtoul(args
[0], NULL
, 0))) == NULL
)
3233 ERROR("no target '%s' configured", args
[0]);
3237 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3242 cache_clean_address
= strtoul(args
[1], NULL
, 0);
3244 if (cache_clean_address
& 0xffff)
3246 ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3250 xscale
->cache_clean_address
= cache_clean_address
;
3256 int xscale_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3258 target_t
*target
= get_current_target(cmd_ctx
);
3259 armv4_5_common_t
*armv4_5
;
3260 xscale_common_t
*xscale
;
3262 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3267 return armv4_5_handle_cache_info_command(cmd_ctx
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
3270 static int xscale_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
)
3272 armv4_5_common_t
*armv4_5
;
3273 xscale_common_t
*xscale
;
3281 if ((retval
= xscale_get_arch_pointers(target
, &armv4_5
, &xscale
)) != ERROR_OK
)
3285 u32 ret
= armv4_5_mmu_translate_va(target
, &xscale
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
3294 static int xscale_mmu(struct target_s
*target
, int *enabled
)
3296 armv4_5_common_t
*armv4_5
= target
->arch_info
;
3297 xscale_common_t
*xscale
= armv4_5
->arch_info
;
3299 if (target
->state
!= TARGET_HALTED
)
3301 ERROR("Target not halted");
3302 return ERROR_TARGET_INVALID
;
3304 *enabled
= xscale
->armv4_5_mmu
.mmu_enabled
;
3309 int xscale_handle_mmu_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3311 target_t
*target
= get_current_target(cmd_ctx
);
3312 armv4_5_common_t
*armv4_5
;
3313 xscale_common_t
*xscale
;
3315 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3320 if (target
->state
!= TARGET_HALTED
)
3322 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3328 if (strcmp("enable", args
[0]) == 0)
3330 xscale_enable_mmu_caches(target
, 1, 0, 0);
3331 xscale
->armv4_5_mmu
.mmu_enabled
= 1;
3333 else if (strcmp("disable", args
[0]) == 0)
3335 xscale_disable_mmu_caches(target
, 1, 0, 0);
3336 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3340 command_print(cmd_ctx
, "mmu %s", (xscale
->armv4_5_mmu
.mmu_enabled
) ? "enabled" : "disabled");
3345 int xscale_handle_idcache_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3347 target_t
*target
= get_current_target(cmd_ctx
);
3348 armv4_5_common_t
*armv4_5
;
3349 xscale_common_t
*xscale
;
3350 int icache
= 0, dcache
= 0;
3352 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3357 if (target
->state
!= TARGET_HALTED
)
3359 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3363 if (strcmp(cmd
, "icache") == 0)
3365 else if (strcmp(cmd
, "dcache") == 0)
3370 if (strcmp("enable", args
[0]) == 0)
3372 xscale_enable_mmu_caches(target
, 0, dcache
, icache
);
3375 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 1;
3377 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 1;
3379 else if (strcmp("disable", args
[0]) == 0)
3381 xscale_disable_mmu_caches(target
, 0, dcache
, icache
);
3384 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
3386 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
3391 command_print(cmd_ctx
, "icache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
) ? "enabled" : "disabled");
3394 command_print(cmd_ctx
, "dcache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) ? "enabled" : "disabled");
3399 int xscale_handle_vector_catch_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3401 target_t
*target
= get_current_target(cmd_ctx
);
3402 armv4_5_common_t
*armv4_5
;
3403 xscale_common_t
*xscale
;
3405 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3412 command_print(cmd_ctx
, "usage: xscale vector_catch [mask]");
3416 xscale
->vector_catch
= strtoul(args
[0], NULL
, 0);
3417 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 8, xscale
->vector_catch
);
3418 xscale_write_dcsr(target
, -1, -1);
3421 command_print(cmd_ctx
, "vector catch mask: 0x%2.2x", xscale
->vector_catch
);
3426 int xscale_handle_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3428 target_t
*target
= get_current_target(cmd_ctx
);
3429 armv4_5_common_t
*armv4_5
;
3430 xscale_common_t
*xscale
;
3432 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3437 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
3439 xscale
->force_hw_bkpts
= 1;
3441 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
3443 xscale
->force_hw_bkpts
= 0;
3447 command_print(cmd_ctx
, "usage: xscale force_hw_bkpts <enable|disable>");
3450 command_print(cmd_ctx
, "force hardware breakpoints %s", (xscale
->force_hw_bkpts
) ? "enabled" : "disabled");
3455 int xscale_handle_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3457 target_t
*target
= get_current_target(cmd_ctx
);
3458 armv4_5_common_t
*armv4_5
;
3459 xscale_common_t
*xscale
;
3462 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3467 if (target
->state
!= TARGET_HALTED
)
3469 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3473 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
3475 xscale_trace_data_t
*td
, *next_td
;
3476 xscale
->trace
.buffer_enabled
= 1;
3478 /* free old trace data */
3479 td
= xscale
->trace
.data
;
3489 xscale
->trace
.data
= NULL
;
3491 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
3493 xscale
->trace
.buffer_enabled
= 0;
3496 if ((argc
>= 2) && (strcmp("fill", args
[1]) == 0))
3499 xscale
->trace
.buffer_fill
= strtoul(args
[2], NULL
, 0);
3501 xscale
->trace
.buffer_fill
= 1;
3503 else if ((argc
>= 2) && (strcmp("wrap", args
[1]) == 0))
3505 xscale
->trace
.buffer_fill
= -1;
3508 if (xscale
->trace
.buffer_enabled
)
3510 /* if we enable the trace buffer in fill-once
3511 * mode we know the address of the first instruction */
3512 xscale
->trace
.pc_ok
= 1;
3513 xscale
->trace
.current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
3517 /* otherwise the address is unknown, and we have no known good PC */
3518 xscale
->trace
.pc_ok
= 0;
3521 command_print(cmd_ctx
, "trace buffer %s (%s)",
3522 (xscale
->trace
.buffer_enabled
) ? "enabled" : "disabled",
3523 (xscale
->trace
.buffer_fill
> 0) ? "fill" : "wrap");
3525 dcsr_value
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32);
3526 if (xscale
->trace
.buffer_fill
>= 0)
3527 xscale_write_dcsr_sw(target
, (dcsr_value
& 0xfffffffc) | 2);
3529 xscale_write_dcsr_sw(target
, dcsr_value
& 0xfffffffc);
3534 int xscale_handle_trace_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3537 armv4_5_common_t
*armv4_5
;
3538 xscale_common_t
*xscale
;
3542 command_print(cmd_ctx
, "usage: xscale trace_image <file> [base address] [type]");
3546 target
= get_current_target(cmd_ctx
);
3548 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3553 if (xscale
->trace
.image
)
3555 image_close(xscale
->trace
.image
);
3556 free(xscale
->trace
.image
);
3557 command_print(cmd_ctx
, "previously loaded image found and closed");
3560 xscale
->trace
.image
= malloc(sizeof(image_t
));
3561 xscale
->trace
.image
->base_address_set
= 0;
3562 xscale
->trace
.image
->start_address_set
= 0;
3564 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3567 xscale
->trace
.image
->base_address_set
= 1;
3568 xscale
->trace
.image
->base_address
= strtoul(args
[1], NULL
, 0);
3572 xscale
->trace
.image
->base_address_set
= 0;
3575 if (image_open(xscale
->trace
.image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
3577 free(xscale
->trace
.image
);
3578 xscale
->trace
.image
= NULL
;
3585 int xscale_handle_dump_trace_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3587 target_t
*target
= get_current_target(cmd_ctx
);
3588 armv4_5_common_t
*armv4_5
;
3589 xscale_common_t
*xscale
;
3590 xscale_trace_data_t
*trace_data
;
3593 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3598 if (target
->state
!= TARGET_HALTED
)
3600 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3606 command_print(cmd_ctx
, "usage: xscale dump_trace <file>");
3610 trace_data
= xscale
->trace
.data
;
3614 command_print(cmd_ctx
, "no trace data collected");
3618 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
3627 fileio_write_u32(&file
, trace_data
->chkpt0
);
3628 fileio_write_u32(&file
, trace_data
->chkpt1
);
3629 fileio_write_u32(&file
, trace_data
->last_instruction
);
3630 fileio_write_u32(&file
, trace_data
->depth
);
3632 for (i
= 0; i
< trace_data
->depth
; i
++)
3633 fileio_write_u32(&file
, trace_data
->entries
[i
].data
| ((trace_data
->entries
[i
].type
& 0xffff) << 16));
3635 trace_data
= trace_data
->next
;
3638 fileio_close(&file
);
3643 int xscale_handle_analyze_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3645 target_t
*target
= get_current_target(cmd_ctx
);
3646 armv4_5_common_t
*armv4_5
;
3647 xscale_common_t
*xscale
;
3649 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3654 xscale_analyze_trace(target
, cmd_ctx
);
3659 int xscale_handle_cp15(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3661 target_t
*target
= get_current_target(cmd_ctx
);
3662 armv4_5_common_t
*armv4_5
;
3663 xscale_common_t
*xscale
;
3665 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3670 if (target
->state
!= TARGET_HALTED
)
3672 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3679 reg_no
= strtoul(args
[0], NULL
, 0);
3680 /*translate from xscale cp15 register no to openocd register*/
3684 reg_no
= XSCALE_MAINID
;
3687 reg_no
= XSCALE_CTRL
;
3690 reg_no
= XSCALE_TTB
;
3693 reg_no
= XSCALE_DAC
;
3696 reg_no
= XSCALE_FSR
;
3699 reg_no
= XSCALE_FAR
;
3702 reg_no
= XSCALE_PID
;
3705 reg_no
= XSCALE_CPACCESS
;
3708 command_print(cmd_ctx
, "invalid register number");
3709 return ERROR_INVALID_ARGUMENTS
;
3711 reg
= &xscale
->reg_cache
->reg_list
[reg_no
];
3718 /* read cp15 control register */
3719 xscale_get_reg(reg
);
3720 value
= buf_get_u32(reg
->value
, 0, 32);
3721 command_print(cmd_ctx
, "%s (/%i): 0x%x", reg
->name
, reg
->size
, value
);
3726 u32 value
= strtoul(args
[1], NULL
, 0);
3728 /* send CP write request (command 0x41) */
3729 xscale_send_u32(target
, 0x41);
3731 /* send CP register number */
3732 xscale_send_u32(target
, reg_no
);
3734 /* send CP register value */
3735 xscale_send_u32(target
, value
);
3737 /* execute cpwait to ensure outstanding operations complete */
3738 xscale_send_u32(target
, 0x53);
3742 command_print(cmd_ctx
, "usage: cp15 [register]<, [value]>");
3748 int handle_xscale_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3750 target_t
*target
= get_current_target(cmd_ctx
);
3751 armv4_5_common_t
*armv4_5
;
3752 xscale_common_t
*xscale
;
3754 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3761 if (strcmp("enable", args
[0]) == 0)
3763 xscale
->fast_memory_access
= 1;
3765 else if (strcmp("disable", args
[0]) == 0)
3767 xscale
->fast_memory_access
= 0;
3771 return ERROR_COMMAND_SYNTAX_ERROR
;
3775 return ERROR_COMMAND_SYNTAX_ERROR
;
3778 command_print(cmd_ctx
, "fast memory access is %s", (xscale
->fast_memory_access
) ? "enabled" : "disabled");
3783 int xscale_register_commands(struct command_context_s
*cmd_ctx
)
3785 command_t
*xscale_cmd
;
3787 xscale_cmd
= register_command(cmd_ctx
, NULL
, "xscale", NULL
, COMMAND_ANY
, "xscale specific commands");
3789 register_command(cmd_ctx
, xscale_cmd
, "debug_handler", xscale_handle_debug_handler_command
, COMMAND_ANY
, "'xscale debug_handler <target#> <address>' command takes two required operands");
3790 register_command(cmd_ctx
, xscale_cmd
, "cache_clean_address", xscale_handle_cache_clean_address_command
, COMMAND_ANY
, NULL
);
3792 register_command(cmd_ctx
, xscale_cmd
, "cache_info", xscale_handle_cache_info_command
, COMMAND_EXEC
, NULL
);
3793 register_command(cmd_ctx
, xscale_cmd
, "mmu", xscale_handle_mmu_command
, COMMAND_EXEC
, "['enable'|'disable'] the MMU");
3794 register_command(cmd_ctx
, xscale_cmd
, "icache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the ICache");
3795 register_command(cmd_ctx
, xscale_cmd
, "dcache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the DCache");
3797 register_command(cmd_ctx
, xscale_cmd
, "vector_catch", xscale_handle_idcache_command
, COMMAND_EXEC
, "<mask> of vectors that should be catched");
3799 register_command(cmd_ctx
, xscale_cmd
, "trace_buffer", xscale_handle_trace_buffer_command
, COMMAND_EXEC
, "<enable|disable> ['fill' [n]|'wrap']");
3801 register_command(cmd_ctx
, xscale_cmd
, "dump_trace", xscale_handle_dump_trace_command
, COMMAND_EXEC
, "dump content of trace buffer to <file>");
3802 register_command(cmd_ctx
, xscale_cmd
, "analyze_trace", xscale_handle_analyze_trace_buffer_command
, COMMAND_EXEC
, "analyze content of trace buffer");
3803 register_command(cmd_ctx
, xscale_cmd
, "trace_image", xscale_handle_trace_image_command
,
3804 COMMAND_EXEC
, "load image from <file> [base address]");
3806 register_command(cmd_ctx
, xscale_cmd
, "cp15", xscale_handle_cp15
, COMMAND_EXEC
, "access coproc 15 <register> [value]");
3807 register_command(cmd_ctx
, xscale_cmd
, "fast_memory_access", handle_xscale_fast_memory_access_command
,
3808 COMMAND_ANY
, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
3811 armv4_5_register_commands(cmd_ctx
);
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