1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "replacements.h"
31 #include "arm7_9_common.h"
35 #include "arm_simulator.h"
36 #include "arm_disassembler.h"
39 #include "binarybuffer.h"
40 #include "time_support.h"
41 #include "breakpoints.h"
52 int xscale_register_commands(struct command_context_s
*cmd_ctx
);
54 /* forward declarations */
55 int xscale_target_create(struct target_s
*target
, Jim_Interp
*interp
);
56 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
57 int xscale_quit(void);
59 int xscale_arch_state(struct target_s
*target
);
60 int xscale_poll(target_t
*target
);
61 int xscale_halt(target_t
*target
);
62 int xscale_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
);
63 int xscale_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
);
64 int xscale_debug_entry(target_t
*target
);
65 int xscale_restore_context(target_t
*target
);
67 int xscale_assert_reset(target_t
*target
);
68 int xscale_deassert_reset(target_t
*target
);
69 int xscale_soft_reset_halt(struct target_s
*target
);
71 int xscale_set_reg_u32(reg_t
*reg
, u32 value
);
73 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
);
74 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
);
76 int xscale_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
77 int xscale_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
78 int xscale_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
);
80 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
81 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
82 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
83 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
84 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
85 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
86 void xscale_enable_watchpoints(struct target_s
*target
);
87 void xscale_enable_breakpoints(struct target_s
*target
);
88 static int xscale_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
);
89 static int xscale_mmu(struct target_s
*target
, int *enabled
);
91 int xscale_read_trace(target_t
*target
);
93 target_type_t xscale_target
=
98 .arch_state
= xscale_arch_state
,
100 .target_request_data
= NULL
,
103 .resume
= xscale_resume
,
106 .assert_reset
= xscale_assert_reset
,
107 .deassert_reset
= xscale_deassert_reset
,
108 .soft_reset_halt
= xscale_soft_reset_halt
,
110 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
112 .read_memory
= xscale_read_memory
,
113 .write_memory
= xscale_write_memory
,
114 .bulk_write_memory
= xscale_bulk_write_memory
,
115 .checksum_memory
= arm7_9_checksum_memory
,
116 .blank_check_memory
= arm7_9_blank_check_memory
,
118 .run_algorithm
= armv4_5_run_algorithm
,
120 .add_breakpoint
= xscale_add_breakpoint
,
121 .remove_breakpoint
= xscale_remove_breakpoint
,
122 .add_watchpoint
= xscale_add_watchpoint
,
123 .remove_watchpoint
= xscale_remove_watchpoint
,
125 .register_commands
= xscale_register_commands
,
126 .target_create
= xscale_target_create
,
127 .init_target
= xscale_init_target
,
130 .virt2phys
= xscale_virt2phys
,
134 char* xscale_reg_list
[] =
136 "XSCALE_MAINID", /* 0 */
146 "XSCALE_IBCR0", /* 10 */
156 "XSCALE_RX", /* 20 */
160 xscale_reg_t xscale_reg_arch_info
[] =
162 {XSCALE_MAINID
, NULL
},
163 {XSCALE_CACHETYPE
, NULL
},
165 {XSCALE_AUXCTRL
, NULL
},
171 {XSCALE_CPACCESS
, NULL
},
172 {XSCALE_IBCR0
, NULL
},
173 {XSCALE_IBCR1
, NULL
},
176 {XSCALE_DBCON
, NULL
},
177 {XSCALE_TBREG
, NULL
},
178 {XSCALE_CHKPT0
, NULL
},
179 {XSCALE_CHKPT1
, NULL
},
180 {XSCALE_DCSR
, NULL
}, /* DCSR accessed via JTAG or SW */
181 {-1, NULL
}, /* TX accessed via JTAG */
182 {-1, NULL
}, /* RX accessed via JTAG */
183 {-1, NULL
}, /* TXRXCTRL implicit access via JTAG */
186 int xscale_reg_arch_type
= -1;
188 int xscale_get_reg(reg_t
*reg
);
189 int xscale_set_reg(reg_t
*reg
, u8
*buf
);
191 int xscale_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, xscale_common_t
**xscale_p
)
193 armv4_5_common_t
*armv4_5
= target
->arch_info
;
194 xscale_common_t
*xscale
= armv4_5
->arch_info
;
196 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
198 LOG_ERROR("target isn't an XScale target");
202 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
)
204 LOG_ERROR("target isn't an XScale target");
208 *armv4_5_p
= armv4_5
;
214 int xscale_jtag_set_instr(jtag_tap_t
*tap
, u32 new_instr
)
219 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
224 field
.num_bits
= tap
->ir_length
;
225 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
226 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
229 field
.in_value
= tmp
;
231 jtag_add_ir_scan(1, &field
, TAP_INVALID
);
233 jtag_check_value_mask(&field
, tap
->expected
, tap
->expected_mask
);
235 free(field
.out_value
);
241 int xscale_read_dcsr(target_t
*target
)
243 armv4_5_common_t
*armv4_5
= target
->arch_info
;
244 xscale_common_t
*xscale
= armv4_5
->arch_info
;
248 scan_field_t fields
[3];
250 u8 field0_check_value
= 0x2;
251 u8 field0_check_mask
= 0x7;
253 u8 field2_check_value
= 0x0;
254 u8 field2_check_mask
= 0x1;
256 jtag_add_end_state(TAP_DRPAUSE
);
257 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dcsr
);
259 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
260 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
262 fields
[0].tap
= xscale
->jtag_info
.tap
;
263 fields
[0].num_bits
= 3;
264 fields
[0].out_value
= &field0
;
266 fields
[0].in_value
= &tmp
;
268 fields
[1].tap
= xscale
->jtag_info
.tap
;
269 fields
[1].num_bits
= 32;
270 fields
[1].out_value
= NULL
;
271 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
274 fields
[2].tap
= xscale
->jtag_info
.tap
;
275 fields
[2].num_bits
= 1;
276 fields
[2].out_value
= &field2
;
278 fields
[2].in_value
= &tmp2
;
280 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
282 jtag_check_value_mask(fields
+0, &field0_check_value
, &field0_check_mask
);
283 jtag_check_value_mask(fields
+2, &field2_check_value
, &field2_check_mask
);
285 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
287 LOG_ERROR("JTAG error while reading DCSR");
291 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
292 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
294 /* write the register with the value we just read
295 * on this second pass, only the first bit of field0 is guaranteed to be 0)
297 field0_check_mask
= 0x1;
298 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
299 fields
[1].in_value
= NULL
;
301 jtag_add_end_state(TAP_IDLE
);
303 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
305 /* DANGER!!! this must be here. It will make sure that the arguments
306 * to jtag_set_check_value() does not go out of scope! */
307 return jtag_execute_queue();
310 int xscale_receive(target_t
*target
, u32
*buffer
, int num_words
)
313 return ERROR_INVALID_ARGUMENTS
;
316 armv4_5_common_t
*armv4_5
= target
->arch_info
;
317 xscale_common_t
*xscale
= armv4_5
->arch_info
;
320 scan_field_t fields
[3];
322 u8
*field0
= malloc(num_words
* 1);
323 u8 field0_check_value
= 0x2;
324 u8 field0_check_mask
= 0x6;
325 u32
*field1
= malloc(num_words
* 4);
326 u8 field2_check_value
= 0x0;
327 u8 field2_check_mask
= 0x1;
329 int words_scheduled
= 0;
333 path
[0] = TAP_DRSELECT
;
334 path
[1] = TAP_DRCAPTURE
;
335 path
[2] = TAP_DRSHIFT
;
337 fields
[0].tap
= xscale
->jtag_info
.tap
;
338 fields
[0].num_bits
= 3;
339 fields
[0].out_value
= NULL
;
341 fields
[0].in_value
= &tmp2
;
343 fields
[1].tap
= xscale
->jtag_info
.tap
;
344 fields
[1].num_bits
= 32;
345 fields
[1].out_value
= NULL
;
347 fields
[1].in_value
= tmp
;
350 fields
[2].tap
= xscale
->jtag_info
.tap
;
351 fields
[2].num_bits
= 1;
352 fields
[2].out_value
= NULL
;
354 fields
[2].in_value
= &tmp3
;
356 jtag_add_end_state(TAP_IDLE
);
357 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dbgtx
);
358 jtag_add_runtest(1, TAP_INVALID
); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
360 /* repeat until all words have been collected */
362 while (words_done
< num_words
)
366 for (i
= words_done
; i
< num_words
; i
++)
368 fields
[0].in_value
= &field0
[i
];
370 jtag_add_pathmove(3, path
);
371 jtag_add_dr_scan_now(3, fields
, TAP_IDLE
);
373 jtag_check_value_mask(fields
+0, &field0_check_value
, &field0_check_mask
);
374 jtag_check_value_mask(fields
+2, &field2_check_value
, &field2_check_mask
);
376 field1
[i
]=buf_get_u32(tmp
, 0, 32);
381 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
383 LOG_ERROR("JTAG error while receiving data from debug handler");
387 /* examine results */
388 for (i
= words_done
; i
< num_words
; i
++)
390 if (!(field0
[0] & 1))
392 /* move backwards if necessary */
394 for (j
= i
; j
< num_words
- 1; j
++)
396 field0
[j
] = field0
[j
+1];
397 field1
[j
] = field1
[j
+1];
402 if (words_scheduled
==0)
404 if (attempts
++==1000)
406 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
407 retval
=ERROR_TARGET_TIMEOUT
;
412 words_done
+= words_scheduled
;
415 for (i
= 0; i
< num_words
; i
++)
416 *(buffer
++) = buf_get_u32((u8
*)&field1
[i
], 0, 32);
423 int xscale_read_tx(target_t
*target
, int consume
)
425 armv4_5_common_t
*armv4_5
= target
->arch_info
;
426 xscale_common_t
*xscale
= armv4_5
->arch_info
;
428 tap_state_t noconsume_path
[6];
431 struct timeval timeout
, now
;
433 scan_field_t fields
[3];
435 u8 field0_check_value
= 0x2;
436 u8 field0_check_mask
= 0x6;
437 u8 field2_check_value
= 0x0;
438 u8 field2_check_mask
= 0x1;
440 jtag_add_end_state(TAP_IDLE
);
442 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dbgtx
);
444 path
[0] = TAP_DRSELECT
;
445 path
[1] = TAP_DRCAPTURE
;
446 path
[2] = TAP_DRSHIFT
;
448 noconsume_path
[0] = TAP_DRSELECT
;
449 noconsume_path
[1] = TAP_DRCAPTURE
;
450 noconsume_path
[2] = TAP_DREXIT1
;
451 noconsume_path
[3] = TAP_DRPAUSE
;
452 noconsume_path
[4] = TAP_DREXIT2
;
453 noconsume_path
[5] = TAP_DRSHIFT
;
455 fields
[0].tap
= xscale
->jtag_info
.tap
;
456 fields
[0].num_bits
= 3;
457 fields
[0].out_value
= NULL
;
458 fields
[0].in_value
= &field0_in
;
460 fields
[1].tap
= xscale
->jtag_info
.tap
;
461 fields
[1].num_bits
= 32;
462 fields
[1].out_value
= NULL
;
463 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
;
466 fields
[2].tap
= xscale
->jtag_info
.tap
;
467 fields
[2].num_bits
= 1;
468 fields
[2].out_value
= NULL
;
470 fields
[2].in_value
= &tmp
;
472 gettimeofday(&timeout
, NULL
);
473 timeval_add_time(&timeout
, 1, 0);
477 /* if we want to consume the register content (i.e. clear TX_READY),
478 * we have to go straight from Capture-DR to Shift-DR
479 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
482 jtag_add_pathmove(3, path
);
485 jtag_add_pathmove(sizeof(noconsume_path
)/sizeof(*noconsume_path
), noconsume_path
);
488 jtag_add_dr_scan(3, fields
, TAP_IDLE
);
490 jtag_check_value_mask(fields
+0, &field0_check_value
, &field0_check_mask
);
491 jtag_check_value_mask(fields
+2, &field2_check_value
, &field2_check_mask
);
493 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
495 LOG_ERROR("JTAG error while reading TX");
496 return ERROR_TARGET_TIMEOUT
;
499 gettimeofday(&now
, NULL
);
500 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
502 LOG_ERROR("time out reading TX register");
503 return ERROR_TARGET_TIMEOUT
;
505 if (!((!(field0_in
& 1)) && consume
))
511 LOG_DEBUG("waiting 100ms");
512 alive_sleep(100); /* avoid flooding the logs */
520 if (!(field0_in
& 1))
521 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
526 int xscale_write_rx(target_t
*target
)
528 armv4_5_common_t
*armv4_5
= target
->arch_info
;
529 xscale_common_t
*xscale
= armv4_5
->arch_info
;
532 struct timeval timeout
, now
;
534 scan_field_t fields
[3];
537 u8 field0_check_value
= 0x2;
538 u8 field0_check_mask
= 0x6;
540 u8 field2_check_value
= 0x0;
541 u8 field2_check_mask
= 0x1;
543 jtag_add_end_state(TAP_IDLE
);
545 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dbgrx
);
547 fields
[0].tap
= xscale
->jtag_info
.tap
;
548 fields
[0].num_bits
= 3;
549 fields
[0].out_value
= &field0_out
;
550 fields
[0].in_value
= &field0_in
;
552 fields
[1].tap
= xscale
->jtag_info
.tap
;
553 fields
[1].num_bits
= 32;
554 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
;
555 fields
[1].in_value
= NULL
;
558 fields
[2].tap
= xscale
->jtag_info
.tap
;
559 fields
[2].num_bits
= 1;
560 fields
[2].out_value
= &field2
;
562 fields
[2].in_value
= &tmp
;
564 gettimeofday(&timeout
, NULL
);
565 timeval_add_time(&timeout
, 1, 0);
567 /* poll until rx_read is low */
568 LOG_DEBUG("polling RX");
571 jtag_add_dr_scan(3, fields
, TAP_IDLE
);
573 jtag_check_value_mask(fields
+0, &field0_check_value
, &field0_check_mask
);
574 jtag_check_value_mask(fields
+2, &field2_check_value
, &field2_check_mask
);
576 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
578 LOG_ERROR("JTAG error while writing RX");
582 gettimeofday(&now
, NULL
);
583 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
585 LOG_ERROR("time out writing RX register");
586 return ERROR_TARGET_TIMEOUT
;
588 if (!(field0_in
& 1))
592 LOG_DEBUG("waiting 100ms");
593 alive_sleep(100); /* avoid flooding the logs */
603 jtag_add_dr_scan(3, fields
, TAP_IDLE
);
605 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
607 LOG_ERROR("JTAG error while writing RX");
614 /* send count elements of size byte to the debug handler */
615 int xscale_send(target_t
*target
, u8
*buffer
, int count
, int size
)
617 armv4_5_common_t
*armv4_5
= target
->arch_info
;
618 xscale_common_t
*xscale
= armv4_5
->arch_info
;
626 jtag_add_end_state(TAP_IDLE
);
628 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dbgrx
);
635 int endianness
= target
->endianness
;
636 while (done_count
++ < count
)
641 if (endianness
== TARGET_LITTLE_ENDIAN
)
643 t
[1]=le_to_h_u32(buffer
);
646 t
[1]=be_to_h_u32(buffer
);
650 if (endianness
== TARGET_LITTLE_ENDIAN
)
652 t
[1]=le_to_h_u16(buffer
);
655 t
[1]=be_to_h_u16(buffer
);
662 LOG_ERROR("BUG: size neither 4, 2 nor 1");
665 jtag_add_dr_out(xscale
->jtag_info
.tap
,
673 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
675 LOG_ERROR("JTAG error while sending data to debug handler");
682 int xscale_send_u32(target_t
*target
, u32 value
)
684 armv4_5_common_t
*armv4_5
= target
->arch_info
;
685 xscale_common_t
*xscale
= armv4_5
->arch_info
;
687 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
688 return xscale_write_rx(target
);
691 int xscale_write_dcsr(target_t
*target
, int hold_rst
, int ext_dbg_brk
)
693 armv4_5_common_t
*armv4_5
= target
->arch_info
;
694 xscale_common_t
*xscale
= armv4_5
->arch_info
;
698 scan_field_t fields
[3];
700 u8 field0_check_value
= 0x2;
701 u8 field0_check_mask
= 0x7;
703 u8 field2_check_value
= 0x0;
704 u8 field2_check_mask
= 0x1;
707 xscale
->hold_rst
= hold_rst
;
709 if (ext_dbg_brk
!= -1)
710 xscale
->external_debug_break
= ext_dbg_brk
;
712 jtag_add_end_state(TAP_IDLE
);
713 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dcsr
);
715 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
716 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
718 fields
[0].tap
= xscale
->jtag_info
.tap
;
719 fields
[0].num_bits
= 3;
720 fields
[0].out_value
= &field0
;
722 fields
[0].in_value
= &tmp
;
724 fields
[1].tap
= xscale
->jtag_info
.tap
;
725 fields
[1].num_bits
= 32;
726 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
727 fields
[1].in_value
= NULL
;
730 fields
[2].tap
= xscale
->jtag_info
.tap
;
731 fields
[2].num_bits
= 1;
732 fields
[2].out_value
= &field2
;
734 fields
[2].in_value
= &tmp2
;
736 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
738 jtag_check_value_mask(fields
+0, &field0_check_value
, &field0_check_mask
);
739 jtag_check_value_mask(fields
+2, &field2_check_value
, &field2_check_mask
);
741 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
743 LOG_ERROR("JTAG error while writing DCSR");
747 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
748 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
753 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
754 unsigned int parity (unsigned int v
)
761 LOG_DEBUG("parity of 0x%x is %i", ov
, (0x6996 >> v
) & 1);
762 return (0x6996 >> v
) & 1;
765 int xscale_load_ic(target_t
*target
, int mini
, u32 va
, u32 buffer
[8])
767 armv4_5_common_t
*armv4_5
= target
->arch_info
;
768 xscale_common_t
*xscale
= armv4_5
->arch_info
;
773 scan_field_t fields
[2];
775 LOG_DEBUG("loading miniIC at 0x%8.8x", va
);
777 jtag_add_end_state(TAP_IDLE
);
778 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.ldic
); /* LDIC */
780 /* CMD is b010 for Main IC and b011 for Mini IC */
782 buf_set_u32(&cmd
, 0, 3, 0x3);
784 buf_set_u32(&cmd
, 0, 3, 0x2);
786 buf_set_u32(&cmd
, 3, 3, 0x0);
788 /* virtual address of desired cache line */
789 buf_set_u32(packet
, 0, 27, va
>> 5);
791 fields
[0].tap
= xscale
->jtag_info
.tap
;
792 fields
[0].num_bits
= 6;
793 fields
[0].out_value
= &cmd
;
795 fields
[0].in_value
= NULL
;
801 fields
[1].tap
= xscale
->jtag_info
.tap
;
802 fields
[1].num_bits
= 27;
803 fields
[1].out_value
= packet
;
805 fields
[1].in_value
= NULL
;
811 jtag_add_dr_scan(2, fields
, TAP_INVALID
);
813 fields
[0].num_bits
= 32;
814 fields
[0].out_value
= packet
;
816 fields
[1].num_bits
= 1;
817 fields
[1].out_value
= &cmd
;
819 for (word
= 0; word
< 8; word
++)
821 buf_set_u32(packet
, 0, 32, buffer
[word
]);
824 memcpy(&value
, packet
, sizeof(u32
));
827 jtag_add_dr_scan(2, fields
, TAP_INVALID
);
830 jtag_execute_queue();
835 int xscale_invalidate_ic_line(target_t
*target
, u32 va
)
837 armv4_5_common_t
*armv4_5
= target
->arch_info
;
838 xscale_common_t
*xscale
= armv4_5
->arch_info
;
842 scan_field_t fields
[2];
844 jtag_add_end_state(TAP_IDLE
);
845 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.ldic
); /* LDIC */
847 /* CMD for invalidate IC line b000, bits [6:4] b000 */
848 buf_set_u32(&cmd
, 0, 6, 0x0);
850 /* virtual address of desired cache line */
851 buf_set_u32(packet
, 0, 27, va
>> 5);
853 fields
[0].tap
= xscale
->jtag_info
.tap
;
854 fields
[0].num_bits
= 6;
855 fields
[0].out_value
= &cmd
;
857 fields
[0].in_value
= NULL
;
863 fields
[1].tap
= xscale
->jtag_info
.tap
;
864 fields
[1].num_bits
= 27;
865 fields
[1].out_value
= packet
;
867 fields
[1].in_value
= NULL
;
873 jtag_add_dr_scan(2, fields
, TAP_INVALID
);
878 int xscale_update_vectors(target_t
*target
)
880 armv4_5_common_t
*armv4_5
= target
->arch_info
;
881 xscale_common_t
*xscale
= armv4_5
->arch_info
;
885 u32 low_reset_branch
, high_reset_branch
;
887 for (i
= 1; i
< 8; i
++)
889 /* if there's a static vector specified for this exception, override */
890 if (xscale
->static_high_vectors_set
& (1 << i
))
892 xscale
->high_vectors
[i
] = xscale
->static_high_vectors
[i
];
896 retval
=target_read_u32(target
, 0xffff0000 + 4*i
, &xscale
->high_vectors
[i
]);
897 if (retval
== ERROR_TARGET_TIMEOUT
)
899 if (retval
!=ERROR_OK
)
901 /* Some of these reads will fail as part of normal execution */
902 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
907 for (i
= 1; i
< 8; i
++)
909 if (xscale
->static_low_vectors_set
& (1 << i
))
911 xscale
->low_vectors
[i
] = xscale
->static_low_vectors
[i
];
915 retval
=target_read_u32(target
, 0x0 + 4*i
, &xscale
->low_vectors
[i
]);
916 if (retval
== ERROR_TARGET_TIMEOUT
)
918 if (retval
!=ERROR_OK
)
920 /* Some of these reads will fail as part of normal execution */
921 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
926 /* calculate branches to debug handler */
927 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
928 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
930 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
931 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
933 /* invalidate and load exception vectors in mini i-cache */
934 xscale_invalidate_ic_line(target
, 0x0);
935 xscale_invalidate_ic_line(target
, 0xffff0000);
937 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
938 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
943 int xscale_arch_state(struct target_s
*target
)
945 armv4_5_common_t
*armv4_5
= target
->arch_info
;
946 xscale_common_t
*xscale
= armv4_5
->arch_info
;
950 "disabled", "enabled"
953 char *arch_dbg_reason
[] =
955 "", "\n(processor reset)", "\n(trace buffer full)"
958 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
960 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
964 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
965 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
966 "MMU: %s, D-Cache: %s, I-Cache: %s"
968 armv4_5_state_strings
[armv4_5
->core_state
],
969 Jim_Nvp_value2name_simple( nvp_target_debug_reason
, target
->debug_reason
)->name
,
970 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
971 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
972 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
973 state
[xscale
->armv4_5_mmu
.mmu_enabled
],
974 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
975 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
],
976 arch_dbg_reason
[xscale
->arch_debug_reason
]);
981 int xscale_poll(target_t
*target
)
984 armv4_5_common_t
*armv4_5
= target
->arch_info
;
985 xscale_common_t
*xscale
= armv4_5
->arch_info
;
987 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_DEBUG_RUNNING
))
989 enum target_state previous_state
= target
->state
;
990 if ((retval
= xscale_read_tx(target
, 0)) == ERROR_OK
)
993 /* there's data to read from the tx register, we entered debug state */
994 xscale
->handler_running
= 1;
996 target
->state
= TARGET_HALTED
;
998 /* process debug entry, fetching current mode regs */
999 retval
= xscale_debug_entry(target
);
1001 else if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1003 LOG_USER("error while polling TX register, reset CPU");
1004 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
1005 target
->state
= TARGET_HALTED
;
1008 /* debug_entry could have overwritten target state (i.e. immediate resume)
1009 * don't signal event handlers in that case
1011 if (target
->state
!= TARGET_HALTED
)
1014 /* if target was running, signal that we halted
1015 * otherwise we reentered from debug execution */
1016 if (previous_state
== TARGET_RUNNING
)
1017 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1019 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
1025 int xscale_debug_entry(target_t
*target
)
1027 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1028 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1036 /* clear external dbg break (will be written on next DCSR read) */
1037 xscale
->external_debug_break
= 0;
1038 if ((retval
=xscale_read_dcsr(target
))!=ERROR_OK
)
1041 /* get r0, pc, r1 to r7 and cpsr */
1042 if ((retval
=xscale_receive(target
, buffer
, 10))!=ERROR_OK
)
1045 /* move r0 from buffer to register cache */
1046 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, buffer
[0]);
1047 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1048 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1049 LOG_DEBUG("r0: 0x%8.8x", buffer
[0]);
1051 /* move pc from buffer to register cache */
1052 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, buffer
[1]);
1053 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1054 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1055 LOG_DEBUG("pc: 0x%8.8x", buffer
[1]);
1057 /* move data from buffer to register cache */
1058 for (i
= 1; i
<= 7; i
++)
1060 buf_set_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32, buffer
[1 + i
]);
1061 armv4_5
->core_cache
->reg_list
[i
].dirty
= 1;
1062 armv4_5
->core_cache
->reg_list
[i
].valid
= 1;
1063 LOG_DEBUG("r%i: 0x%8.8x", i
, buffer
[i
+ 1]);
1066 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, buffer
[9]);
1067 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
1068 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1069 LOG_DEBUG("cpsr: 0x%8.8x", buffer
[9]);
1071 armv4_5
->core_mode
= buffer
[9] & 0x1f;
1072 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
1074 target
->state
= TARGET_UNKNOWN
;
1075 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1076 return ERROR_TARGET_FAILURE
;
1078 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
1080 if (buffer
[9] & 0x20)
1081 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1083 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1086 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1089 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1090 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
1092 xscale_receive(target
, buffer
, 8);
1093 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1094 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1095 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1099 /* r8 to r14, but no spsr */
1100 xscale_receive(target
, buffer
, 7);
1103 /* move data from buffer to register cache */
1104 for (i
= 8; i
<= 14; i
++)
1106 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, buffer
[i
- 8]);
1107 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1108 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1111 /* examine debug reason */
1112 xscale_read_dcsr(target
);
1113 moe
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 2, 3);
1115 /* stored PC (for calculating fixup) */
1116 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1120 case 0x0: /* Processor reset */
1121 target
->debug_reason
= DBG_REASON_DBGRQ
;
1122 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_RESET
;
1125 case 0x1: /* Instruction breakpoint hit */
1126 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1127 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1130 case 0x2: /* Data breakpoint hit */
1131 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1132 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1135 case 0x3: /* BKPT instruction executed */
1136 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1137 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1140 case 0x4: /* Ext. debug event */
1141 target
->debug_reason
= DBG_REASON_DBGRQ
;
1142 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1145 case 0x5: /* Vector trap occured */
1146 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1147 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1150 case 0x6: /* Trace buffer full break */
1151 target
->debug_reason
= DBG_REASON_DBGRQ
;
1152 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_TB_FULL
;
1155 case 0x7: /* Reserved */
1157 LOG_ERROR("Method of Entry is 'Reserved'");
1162 /* apply PC fixup */
1163 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
1165 /* on the first debug entry, identify cache type */
1166 if (xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
1170 /* read cp15 cache type register */
1171 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
]);
1172 cache_type_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
].value
, 0, 32);
1174 armv4_5_identify_cache(cache_type_reg
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
1177 /* examine MMU and Cache settings */
1178 /* read cp15 control register */
1179 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1180 xscale
->cp15_control_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1181 xscale
->armv4_5_mmu
.mmu_enabled
= (xscale
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1182 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (xscale
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1183 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (xscale
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1185 /* tracing enabled, read collected trace data */
1186 if (xscale
->trace
.buffer_enabled
)
1188 xscale_read_trace(target
);
1189 xscale
->trace
.buffer_fill
--;
1191 /* resume if we're still collecting trace data */
1192 if ((xscale
->arch_debug_reason
== XSCALE_DBG_REASON_TB_FULL
)
1193 && (xscale
->trace
.buffer_fill
> 0))
1195 xscale_resume(target
, 1, 0x0, 1, 0);
1199 xscale
->trace
.buffer_enabled
= 0;
1206 int xscale_halt(target_t
*target
)
1208 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1209 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1211 LOG_DEBUG("target->state: %s",
1212 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
1214 if (target
->state
== TARGET_HALTED
)
1216 LOG_DEBUG("target was already halted");
1219 else if (target
->state
== TARGET_UNKNOWN
)
1221 /* this must not happen for a xscale target */
1222 LOG_ERROR("target was in unknown state when halt was requested");
1223 return ERROR_TARGET_INVALID
;
1225 else if (target
->state
== TARGET_RESET
)
1227 LOG_DEBUG("target->state == TARGET_RESET");
1231 /* assert external dbg break */
1232 xscale
->external_debug_break
= 1;
1233 xscale_read_dcsr(target
);
1235 target
->debug_reason
= DBG_REASON_DBGRQ
;
1241 int xscale_enable_single_step(struct target_s
*target
, u32 next_pc
)
1243 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1244 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1245 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1248 if (xscale
->ibcr0_used
)
1250 breakpoint_t
*ibcr0_bp
= breakpoint_find(target
, buf_get_u32(ibcr0
->value
, 0, 32) & 0xfffffffe);
1254 xscale_unset_breakpoint(target
, ibcr0_bp
);
1258 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1263 if ((retval
=xscale_set_reg_u32(ibcr0
, next_pc
| 0x1))!=ERROR_OK
)
1269 int xscale_disable_single_step(struct target_s
*target
)
1271 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1272 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1273 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1276 if ((retval
=xscale_set_reg_u32(ibcr0
, 0x0))!=ERROR_OK
)
1282 int xscale_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
1284 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1285 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1286 breakpoint_t
*breakpoint
= target
->breakpoints
;
1295 if (target
->state
!= TARGET_HALTED
)
1297 LOG_WARNING("target not halted");
1298 return ERROR_TARGET_NOT_HALTED
;
1301 if (!debug_execution
)
1303 target_free_all_working_areas(target
);
1306 /* update vector tables */
1307 if ((retval
=xscale_update_vectors(target
))!=ERROR_OK
)
1310 /* current = 1: continue on current pc, otherwise continue at <address> */
1312 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1314 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1316 /* if we're at the reset vector, we have to simulate the branch */
1317 if (current_pc
== 0x0)
1319 arm_simulate_step(target
, NULL
);
1320 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1323 /* the front-end may request us not to handle breakpoints */
1324 if (handle_breakpoints
)
1326 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1330 /* there's a breakpoint at the current PC, we have to step over it */
1331 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1332 xscale_unset_breakpoint(target
, breakpoint
);
1334 /* calculate PC of next instruction */
1335 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1338 target_read_u32(target
, current_pc
, ¤t_opcode
);
1339 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode
);
1342 LOG_DEBUG("enable single-step");
1343 xscale_enable_single_step(target
, next_pc
);
1345 /* restore banked registers */
1346 xscale_restore_context(target
);
1348 /* send resume request (command 0x30 or 0x31)
1349 * clean the trace buffer if it is to be enabled (0x62) */
1350 if (xscale
->trace
.buffer_enabled
)
1352 xscale_send_u32(target
, 0x62);
1353 xscale_send_u32(target
, 0x31);
1356 xscale_send_u32(target
, 0x30);
1359 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1360 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1362 for (i
= 7; i
>= 0; i
--)
1365 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1366 LOG_DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1370 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1371 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1373 /* wait for and process debug entry */
1374 xscale_debug_entry(target
);
1376 LOG_DEBUG("disable single-step");
1377 xscale_disable_single_step(target
);
1379 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint
->address
);
1380 xscale_set_breakpoint(target
, breakpoint
);
1384 /* enable any pending breakpoints and watchpoints */
1385 xscale_enable_breakpoints(target
);
1386 xscale_enable_watchpoints(target
);
1388 /* restore banked registers */
1389 xscale_restore_context(target
);
1391 /* send resume request (command 0x30 or 0x31)
1392 * clean the trace buffer if it is to be enabled (0x62) */
1393 if (xscale
->trace
.buffer_enabled
)
1395 xscale_send_u32(target
, 0x62);
1396 xscale_send_u32(target
, 0x31);
1399 xscale_send_u32(target
, 0x30);
1402 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1403 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1405 for (i
= 7; i
>= 0; i
--)
1408 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1409 LOG_DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1413 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1414 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1416 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1418 if (!debug_execution
)
1420 /* registers are now invalid */
1421 armv4_5_invalidate_core_regs(target
);
1422 target
->state
= TARGET_RUNNING
;
1423 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1427 target
->state
= TARGET_DEBUG_RUNNING
;
1428 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1431 LOG_DEBUG("target resumed");
1433 xscale
->handler_running
= 1;
1438 static int xscale_step_inner(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1440 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1441 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1447 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1449 /* calculate PC of next instruction */
1450 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1452 u32 current_opcode
, current_pc
;
1453 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1455 target_read_u32(target
, current_pc
, ¤t_opcode
);
1456 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode
);
1460 LOG_DEBUG("enable single-step");
1461 if ((retval
=xscale_enable_single_step(target
, next_pc
))!=ERROR_OK
)
1464 /* restore banked registers */
1465 if ((retval
=xscale_restore_context(target
))!=ERROR_OK
)
1468 /* send resume request (command 0x30 or 0x31)
1469 * clean the trace buffer if it is to be enabled (0x62) */
1470 if (xscale
->trace
.buffer_enabled
)
1472 if ((retval
=xscale_send_u32(target
, 0x62))!=ERROR_OK
)
1474 if ((retval
=xscale_send_u32(target
, 0x31))!=ERROR_OK
)
1478 if ((retval
=xscale_send_u32(target
, 0x30))!=ERROR_OK
)
1482 if ((retval
=xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32)))!=ERROR_OK
)
1484 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1486 for (i
= 7; i
>= 0; i
--)
1489 if ((retval
=xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32)))!=ERROR_OK
)
1491 LOG_DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1495 if ((retval
=xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32)))!=ERROR_OK
)
1497 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1499 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1501 /* registers are now invalid */
1502 if ((retval
=armv4_5_invalidate_core_regs(target
))!=ERROR_OK
)
1505 /* wait for and process debug entry */
1506 if ((retval
=xscale_debug_entry(target
))!=ERROR_OK
)
1509 LOG_DEBUG("disable single-step");
1510 if ((retval
=xscale_disable_single_step(target
))!=ERROR_OK
)
1513 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1518 int xscale_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1520 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1521 breakpoint_t
*breakpoint
= target
->breakpoints
;
1526 if (target
->state
!= TARGET_HALTED
)
1528 LOG_WARNING("target not halted");
1529 return ERROR_TARGET_NOT_HALTED
;
1532 /* current = 1: continue on current pc, otherwise continue at <address> */
1534 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1536 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1538 /* if we're at the reset vector, we have to simulate the step */
1539 if (current_pc
== 0x0)
1541 if ((retval
=arm_simulate_step(target
, NULL
))!=ERROR_OK
)
1543 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1545 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1546 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1551 /* the front-end may request us not to handle breakpoints */
1552 if (handle_breakpoints
)
1553 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1555 if ((retval
=xscale_unset_breakpoint(target
, breakpoint
))!=ERROR_OK
)
1559 retval
= xscale_step_inner(target
, current
, address
, handle_breakpoints
);
1563 xscale_set_breakpoint(target
, breakpoint
);
1566 LOG_DEBUG("target stepped");
1572 int xscale_assert_reset(target_t
*target
)
1574 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1575 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1577 LOG_DEBUG("target->state: %s",
1578 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
1580 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1581 * end up in T-L-R, which would reset JTAG
1583 jtag_add_end_state(TAP_IDLE
);
1584 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dcsr
);
1586 /* set Hold reset, Halt mode and Trap Reset */
1587 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1588 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1589 xscale_write_dcsr(target
, 1, 0);
1591 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1592 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, 0x7f);
1593 jtag_execute_queue();
1596 jtag_add_reset(0, 1);
1598 /* sleep 1ms, to be sure we fulfill any requirements */
1599 jtag_add_sleep(1000);
1600 jtag_execute_queue();
1602 target
->state
= TARGET_RESET
;
1604 if (target
->reset_halt
)
1607 if ((retval
= target_halt(target
))!=ERROR_OK
)
1614 int xscale_deassert_reset(target_t
*target
)
1616 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1617 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1619 fileio_t debug_handler
;
1627 breakpoint_t
*breakpoint
= target
->breakpoints
;
1631 xscale
->ibcr_available
= 2;
1632 xscale
->ibcr0_used
= 0;
1633 xscale
->ibcr1_used
= 0;
1635 xscale
->dbr_available
= 2;
1636 xscale
->dbr0_used
= 0;
1637 xscale
->dbr1_used
= 0;
1639 /* mark all hardware breakpoints as unset */
1642 if (breakpoint
->type
== BKPT_HARD
)
1644 breakpoint
->set
= 0;
1646 breakpoint
= breakpoint
->next
;
1649 if (!xscale
->handler_installed
)
1652 jtag_add_reset(0, 0);
1654 /* wait 300ms; 150 and 100ms were not enough */
1655 jtag_add_sleep(300*1000);
1657 jtag_add_runtest(2030, TAP_IDLE
);
1658 jtag_execute_queue();
1660 /* set Hold reset, Halt mode and Trap Reset */
1661 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1662 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1663 xscale_write_dcsr(target
, 1, 0);
1665 /* Load debug handler */
1666 if (fileio_open(&debug_handler
, "xscale/debug_handler.bin", FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1671 if ((binary_size
= debug_handler
.size
) % 4)
1673 LOG_ERROR("debug_handler.bin: size not a multiple of 4");
1677 if (binary_size
> 0x800)
1679 LOG_ERROR("debug_handler.bin: larger than 2kb");
1683 binary_size
= CEIL(binary_size
, 32) * 32;
1685 address
= xscale
->handler_address
;
1686 while (binary_size
> 0)
1691 if ((retval
= fileio_read(&debug_handler
, 32, buffer
, &buf_cnt
)) != ERROR_OK
)
1696 for (i
= 0; i
< buf_cnt
; i
+= 4)
1698 /* convert LE buffer to host-endian u32 */
1699 cache_line
[i
/ 4] = le_to_h_u32(&buffer
[i
]);
1702 for (; buf_cnt
< 32; buf_cnt
+= 4)
1704 cache_line
[buf_cnt
/ 4] = 0xe1a08008;
1707 /* only load addresses other than the reset vectors */
1708 if ((address
% 0x400) != 0x0)
1710 xscale_load_ic(target
, 1, address
, cache_line
);
1714 binary_size
-= buf_cnt
;
1717 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
1718 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
1720 jtag_add_runtest(30, TAP_IDLE
);
1722 jtag_add_sleep(100000);
1724 /* set Hold reset, Halt mode and Trap Reset */
1725 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1726 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1727 xscale_write_dcsr(target
, 1, 0);
1729 /* clear Hold reset to let the target run (should enter debug handler) */
1730 xscale_write_dcsr(target
, 0, 1);
1731 target
->state
= TARGET_RUNNING
;
1733 if (!target
->reset_halt
)
1735 jtag_add_sleep(10000);
1737 /* we should have entered debug now */
1738 xscale_debug_entry(target
);
1739 target
->state
= TARGET_HALTED
;
1741 /* resume the target */
1742 xscale_resume(target
, 1, 0x0, 1, 0);
1745 fileio_close(&debug_handler
);
1749 jtag_add_reset(0, 0);
1755 int xscale_soft_reset_halt(struct target_s
*target
)
1760 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
1765 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
)
1771 int xscale_full_context(target_t
*target
)
1773 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1781 if (target
->state
!= TARGET_HALTED
)
1783 LOG_WARNING("target not halted");
1784 return ERROR_TARGET_NOT_HALTED
;
1787 buffer
= malloc(4 * 8);
1789 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1790 * we can't enter User mode on an XScale (unpredictable),
1791 * but User shares registers with SYS
1793 for(i
= 1; i
< 7; i
++)
1797 /* check if there are invalid registers in the current mode
1799 for (j
= 0; j
<= 16; j
++)
1801 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1809 /* request banked registers */
1810 xscale_send_u32(target
, 0x0);
1813 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1814 tmp_cpsr
|= 0xc0; /* I/F bits */
1816 /* send CPSR for desired mode */
1817 xscale_send_u32(target
, tmp_cpsr
);
1819 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1820 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1822 xscale_receive(target
, buffer
, 8);
1823 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1824 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1825 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1829 xscale_receive(target
, buffer
, 7);
1832 /* move data from buffer to register cache */
1833 for (j
= 8; j
<= 14; j
++)
1835 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
, 0, 32, buffer
[j
- 8]);
1836 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1837 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1847 int xscale_restore_context(target_t
*target
)
1849 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1855 if (target
->state
!= TARGET_HALTED
)
1857 LOG_WARNING("target not halted");
1858 return ERROR_TARGET_NOT_HALTED
;
1861 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1862 * we can't enter User mode on an XScale (unpredictable),
1863 * but User shares registers with SYS
1865 for(i
= 1; i
< 7; i
++)
1869 /* check if there are invalid registers in the current mode
1871 for (j
= 8; j
<= 14; j
++)
1873 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
== 1)
1877 /* if not USR/SYS, check if the SPSR needs to be written */
1878 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1880 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
== 1)
1888 /* send banked registers */
1889 xscale_send_u32(target
, 0x1);
1892 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1893 tmp_cpsr
|= 0xc0; /* I/F bits */
1895 /* send CPSR for desired mode */
1896 xscale_send_u32(target
, tmp_cpsr
);
1898 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1899 for (j
= 8; j
<= 14; j
++)
1901 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, j
).value
, 0, 32));
1902 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1905 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1907 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32));
1908 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1916 int xscale_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1918 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1919 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1924 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1926 if (target
->state
!= TARGET_HALTED
)
1928 LOG_WARNING("target not halted");
1929 return ERROR_TARGET_NOT_HALTED
;
1932 /* sanitize arguments */
1933 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1934 return ERROR_INVALID_ARGUMENTS
;
1936 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1937 return ERROR_TARGET_UNALIGNED_ACCESS
;
1939 /* send memory read request (command 0x1n, n: access size) */
1940 if ((retval
=xscale_send_u32(target
, 0x10 | size
))!=ERROR_OK
)
1943 /* send base address for read request */
1944 if ((retval
=xscale_send_u32(target
, address
))!=ERROR_OK
)
1947 /* send number of requested data words */
1948 if ((retval
=xscale_send_u32(target
, count
))!=ERROR_OK
)
1951 /* receive data from target (count times 32-bit words in host endianness) */
1952 buf32
= malloc(4 * count
);
1953 if ((retval
=xscale_receive(target
, buf32
, count
))!=ERROR_OK
)
1956 /* extract data from host-endian buffer into byte stream */
1957 for (i
= 0; i
< count
; i
++)
1962 target_buffer_set_u32(target
, buffer
, buf32
[i
]);
1966 target_buffer_set_u16(target
, buffer
, buf32
[i
] & 0xffff);
1970 *buffer
++ = buf32
[i
] & 0xff;
1973 LOG_ERROR("should never get here");
1980 /* examine DCSR, to see if Sticky Abort (SA) got set */
1981 if ((retval
=xscale_read_dcsr(target
))!=ERROR_OK
)
1983 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1986 if ((retval
=xscale_send_u32(target
, 0x60))!=ERROR_OK
)
1989 return ERROR_TARGET_DATA_ABORT
;
1995 int xscale_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1997 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1998 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2001 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
2003 if (target
->state
!= TARGET_HALTED
)
2005 LOG_WARNING("target not halted");
2006 return ERROR_TARGET_NOT_HALTED
;
2009 /* sanitize arguments */
2010 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
2011 return ERROR_INVALID_ARGUMENTS
;
2013 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2014 return ERROR_TARGET_UNALIGNED_ACCESS
;
2016 /* send memory write request (command 0x2n, n: access size) */
2017 if ((retval
=xscale_send_u32(target
, 0x20 | size
))!=ERROR_OK
)
2020 /* send base address for read request */
2021 if ((retval
=xscale_send_u32(target
, address
))!=ERROR_OK
)
2024 /* send number of requested data words to be written*/
2025 if ((retval
=xscale_send_u32(target
, count
))!=ERROR_OK
)
2028 /* extract data from host-endian buffer into byte stream */
2030 for (i
= 0; i
< count
; i
++)
2035 value
= target_buffer_get_u32(target
, buffer
);
2036 xscale_send_u32(target
, value
);
2040 value
= target_buffer_get_u16(target
, buffer
);
2041 xscale_send_u32(target
, value
);
2046 xscale_send_u32(target
, value
);
2050 LOG_ERROR("should never get here");
2055 if ((retval
=xscale_send(target
, buffer
, count
, size
))!=ERROR_OK
)
2058 /* examine DCSR, to see if Sticky Abort (SA) got set */
2059 if ((retval
=xscale_read_dcsr(target
))!=ERROR_OK
)
2061 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
2064 if ((retval
=xscale_send_u32(target
, 0x60))!=ERROR_OK
)
2067 return ERROR_TARGET_DATA_ABORT
;
2073 int xscale_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
2075 return xscale_write_memory(target
, address
, 4, count
, buffer
);
2078 u32
xscale_get_ttb(target_t
*target
)
2080 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2081 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2084 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_TTB
]);
2085 ttb
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_TTB
].value
, 0, 32);
2090 void xscale_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2092 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2093 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2096 /* read cp15 control register */
2097 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2098 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2101 cp15_control
&= ~0x1U
;
2106 xscale_send_u32(target
, 0x50);
2107 xscale_send_u32(target
, xscale
->cache_clean_address
);
2109 /* invalidate DCache */
2110 xscale_send_u32(target
, 0x51);
2112 cp15_control
&= ~0x4U
;
2117 /* invalidate ICache */
2118 xscale_send_u32(target
, 0x52);
2119 cp15_control
&= ~0x1000U
;
2122 /* write new cp15 control register */
2123 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2125 /* execute cpwait to ensure outstanding operations complete */
2126 xscale_send_u32(target
, 0x53);
2129 void xscale_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2131 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2132 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2135 /* read cp15 control register */
2136 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2137 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2140 cp15_control
|= 0x1U
;
2143 cp15_control
|= 0x4U
;
2146 cp15_control
|= 0x1000U
;
2148 /* write new cp15 control register */
2149 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2151 /* execute cpwait to ensure outstanding operations complete */
2152 xscale_send_u32(target
, 0x53);
2155 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2158 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2159 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2161 if (target
->state
!= TARGET_HALTED
)
2163 LOG_WARNING("target not halted");
2164 return ERROR_TARGET_NOT_HALTED
;
2167 if (breakpoint
->set
)
2169 LOG_WARNING("breakpoint already set");
2173 if (breakpoint
->type
== BKPT_HARD
)
2175 u32 value
= breakpoint
->address
| 1;
2176 if (!xscale
->ibcr0_used
)
2178 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], value
);
2179 xscale
->ibcr0_used
= 1;
2180 breakpoint
->set
= 1; /* breakpoint set on first breakpoint register */
2182 else if (!xscale
->ibcr1_used
)
2184 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], value
);
2185 xscale
->ibcr1_used
= 1;
2186 breakpoint
->set
= 2; /* breakpoint set on second breakpoint register */
2190 LOG_ERROR("BUG: no hardware comparator available");
2194 else if (breakpoint
->type
== BKPT_SOFT
)
2196 if (breakpoint
->length
== 4)
2198 /* keep the original instruction in target endianness */
2199 if((retval
= target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2203 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2204 if((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->arm_bkpt
)) != ERROR_OK
)
2211 /* keep the original instruction in target endianness */
2212 if((retval
= target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2216 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2217 if((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->thumb_bkpt
)) != ERROR_OK
)
2222 breakpoint
->set
= 1;
2228 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2230 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2231 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2233 if (target
->state
!= TARGET_HALTED
)
2235 LOG_WARNING("target not halted");
2236 return ERROR_TARGET_NOT_HALTED
;
2239 if ((breakpoint
->type
== BKPT_HARD
) && (xscale
->ibcr_available
< 1))
2241 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2242 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2245 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
2247 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2248 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2251 if (breakpoint
->type
== BKPT_HARD
)
2253 xscale
->ibcr_available
--;
2259 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2262 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2263 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2265 if (target
->state
!= TARGET_HALTED
)
2267 LOG_WARNING("target not halted");
2268 return ERROR_TARGET_NOT_HALTED
;
2271 if (!breakpoint
->set
)
2273 LOG_WARNING("breakpoint not set");
2277 if (breakpoint
->type
== BKPT_HARD
)
2279 if (breakpoint
->set
== 1)
2281 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], 0x0);
2282 xscale
->ibcr0_used
= 0;
2284 else if (breakpoint
->set
== 2)
2286 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], 0x0);
2287 xscale
->ibcr1_used
= 0;
2289 breakpoint
->set
= 0;
2293 /* restore original instruction (kept in target endianness) */
2294 if (breakpoint
->length
== 4)
2296 if((retval
= target
->type
->write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2303 if((retval
= target
->type
->write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2308 breakpoint
->set
= 0;
2314 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2316 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2317 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2319 if (target
->state
!= TARGET_HALTED
)
2321 LOG_WARNING("target not halted");
2322 return ERROR_TARGET_NOT_HALTED
;
2325 if (breakpoint
->set
)
2327 xscale_unset_breakpoint(target
, breakpoint
);
2330 if (breakpoint
->type
== BKPT_HARD
)
2331 xscale
->ibcr_available
++;
2336 int xscale_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2338 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2339 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2341 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2342 u32 dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2344 if (target
->state
!= TARGET_HALTED
)
2346 LOG_WARNING("target not halted");
2347 return ERROR_TARGET_NOT_HALTED
;
2350 xscale_get_reg(dbcon
);
2352 switch (watchpoint
->rw
)
2364 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2367 if (!xscale
->dbr0_used
)
2369 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR0
], watchpoint
->address
);
2370 dbcon_value
|= enable
;
2371 xscale_set_reg_u32(dbcon
, dbcon_value
);
2372 watchpoint
->set
= 1;
2373 xscale
->dbr0_used
= 1;
2375 else if (!xscale
->dbr1_used
)
2377 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
], watchpoint
->address
);
2378 dbcon_value
|= enable
<< 2;
2379 xscale_set_reg_u32(dbcon
, dbcon_value
);
2380 watchpoint
->set
= 2;
2381 xscale
->dbr1_used
= 1;
2385 LOG_ERROR("BUG: no hardware comparator available");
2392 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2394 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2395 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2397 if (target
->state
!= TARGET_HALTED
)
2399 LOG_WARNING("target not halted");
2400 return ERROR_TARGET_NOT_HALTED
;
2403 if (xscale
->dbr_available
< 1)
2405 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2408 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
2410 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2413 xscale
->dbr_available
--;
2418 int xscale_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2420 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2421 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2422 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2423 u32 dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2425 if (target
->state
!= TARGET_HALTED
)
2427 LOG_WARNING("target not halted");
2428 return ERROR_TARGET_NOT_HALTED
;
2431 if (!watchpoint
->set
)
2433 LOG_WARNING("breakpoint not set");
2437 if (watchpoint
->set
== 1)
2439 dbcon_value
&= ~0x3;
2440 xscale_set_reg_u32(dbcon
, dbcon_value
);
2441 xscale
->dbr0_used
= 0;
2443 else if (watchpoint
->set
== 2)
2445 dbcon_value
&= ~0xc;
2446 xscale_set_reg_u32(dbcon
, dbcon_value
);
2447 xscale
->dbr1_used
= 0;
2449 watchpoint
->set
= 0;
2454 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2456 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2457 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2459 if (target
->state
!= TARGET_HALTED
)
2461 LOG_WARNING("target not halted");
2462 return ERROR_TARGET_NOT_HALTED
;
2465 if (watchpoint
->set
)
2467 xscale_unset_watchpoint(target
, watchpoint
);
2470 xscale
->dbr_available
++;
2475 void xscale_enable_watchpoints(struct target_s
*target
)
2477 watchpoint_t
*watchpoint
= target
->watchpoints
;
2481 if (watchpoint
->set
== 0)
2482 xscale_set_watchpoint(target
, watchpoint
);
2483 watchpoint
= watchpoint
->next
;
2487 void xscale_enable_breakpoints(struct target_s
*target
)
2489 breakpoint_t
*breakpoint
= target
->breakpoints
;
2491 /* set any pending breakpoints */
2494 if (breakpoint
->set
== 0)
2495 xscale_set_breakpoint(target
, breakpoint
);
2496 breakpoint
= breakpoint
->next
;
2500 int xscale_get_reg(reg_t
*reg
)
2502 xscale_reg_t
*arch_info
= reg
->arch_info
;
2503 target_t
*target
= arch_info
->target
;
2504 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2505 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2507 /* DCSR, TX and RX are accessible via JTAG */
2508 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2510 return xscale_read_dcsr(arch_info
->target
);
2512 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2514 /* 1 = consume register content */
2515 return xscale_read_tx(arch_info
->target
, 1);
2517 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2519 /* can't read from RX register (host -> debug handler) */
2522 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2524 /* can't (explicitly) read from TXRXCTRL register */
2527 else /* Other DBG registers have to be transfered by the debug handler */
2529 /* send CP read request (command 0x40) */
2530 xscale_send_u32(target
, 0x40);
2532 /* send CP register number */
2533 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2535 /* read register value */
2536 xscale_read_tx(target
, 1);
2537 buf_cpy(xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
, reg
->value
, 32);
2546 int xscale_set_reg(reg_t
*reg
, u8
* buf
)
2548 xscale_reg_t
*arch_info
= reg
->arch_info
;
2549 target_t
*target
= arch_info
->target
;
2550 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2551 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2552 u32 value
= buf_get_u32(buf
, 0, 32);
2554 /* DCSR, TX and RX are accessible via JTAG */
2555 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2557 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32, value
);
2558 return xscale_write_dcsr(arch_info
->target
, -1, -1);
2560 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2562 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
2563 return xscale_write_rx(arch_info
->target
);
2565 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2567 /* can't write to TX register (debug-handler -> host) */
2570 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2572 /* can't (explicitly) write to TXRXCTRL register */
2575 else /* Other DBG registers have to be transfered by the debug handler */
2577 /* send CP write request (command 0x41) */
2578 xscale_send_u32(target
, 0x41);
2580 /* send CP register number */
2581 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2583 /* send CP register value */
2584 xscale_send_u32(target
, value
);
2585 buf_set_u32(reg
->value
, 0, 32, value
);
2591 /* convenience wrapper to access XScale specific registers */
2592 int xscale_set_reg_u32(reg_t
*reg
, u32 value
)
2596 buf_set_u32(buf
, 0, 32, value
);
2598 return xscale_set_reg(reg
, buf
);
2601 int xscale_write_dcsr_sw(target_t
*target
, u32 value
)
2603 /* get pointers to arch-specific information */
2604 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2605 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2606 reg_t
*dcsr
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
2607 xscale_reg_t
*dcsr_arch_info
= dcsr
->arch_info
;
2609 /* send CP write request (command 0x41) */
2610 xscale_send_u32(target
, 0x41);
2612 /* send CP register number */
2613 xscale_send_u32(target
, dcsr_arch_info
->dbg_handler_number
);
2615 /* send CP register value */
2616 xscale_send_u32(target
, value
);
2617 buf_set_u32(dcsr
->value
, 0, 32, value
);
2622 int xscale_read_trace(target_t
*target
)
2624 /* get pointers to arch-specific information */
2625 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2626 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2627 xscale_trace_data_t
**trace_data_p
;
2629 /* 258 words from debug handler
2630 * 256 trace buffer entries
2631 * 2 checkpoint addresses
2633 u32 trace_buffer
[258];
2634 int is_address
[256];
2637 if (target
->state
!= TARGET_HALTED
)
2639 LOG_WARNING("target must be stopped to read trace data");
2640 return ERROR_TARGET_NOT_HALTED
;
2643 /* send read trace buffer command (command 0x61) */
2644 xscale_send_u32(target
, 0x61);
2646 /* receive trace buffer content */
2647 xscale_receive(target
, trace_buffer
, 258);
2649 /* parse buffer backwards to identify address entries */
2650 for (i
= 255; i
>= 0; i
--)
2653 if (((trace_buffer
[i
] & 0xf0) == 0x90) ||
2654 ((trace_buffer
[i
] & 0xf0) == 0xd0))
2657 is_address
[--i
] = 1;
2659 is_address
[--i
] = 1;
2661 is_address
[--i
] = 1;
2663 is_address
[--i
] = 1;
2668 /* search first non-zero entry */
2669 for (j
= 0; (j
< 256) && (trace_buffer
[j
] == 0) && (!is_address
[j
]); j
++)
2674 LOG_DEBUG("no trace data collected");
2675 return ERROR_XSCALE_NO_TRACE_DATA
;
2678 for (trace_data_p
= &xscale
->trace
.data
; *trace_data_p
; trace_data_p
= &(*trace_data_p
)->next
)
2681 *trace_data_p
= malloc(sizeof(xscale_trace_data_t
));
2682 (*trace_data_p
)->next
= NULL
;
2683 (*trace_data_p
)->chkpt0
= trace_buffer
[256];
2684 (*trace_data_p
)->chkpt1
= trace_buffer
[257];
2685 (*trace_data_p
)->last_instruction
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2686 (*trace_data_p
)->entries
= malloc(sizeof(xscale_trace_entry_t
) * (256 - j
));
2687 (*trace_data_p
)->depth
= 256 - j
;
2689 for (i
= j
; i
< 256; i
++)
2691 (*trace_data_p
)->entries
[i
- j
].data
= trace_buffer
[i
];
2693 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_ADDRESS
;
2695 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_MESSAGE
;
2701 int xscale_read_instruction(target_t
*target
, arm_instruction_t
*instruction
)
2703 /* get pointers to arch-specific information */
2704 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2705 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2712 if (!xscale
->trace
.image
)
2713 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
2715 /* search for the section the current instruction belongs to */
2716 for (i
= 0; i
< xscale
->trace
.image
->num_sections
; i
++)
2718 if ((xscale
->trace
.image
->sections
[i
].base_address
<= xscale
->trace
.current_pc
) &&
2719 (xscale
->trace
.image
->sections
[i
].base_address
+ xscale
->trace
.image
->sections
[i
].size
> xscale
->trace
.current_pc
))
2728 /* current instruction couldn't be found in the image */
2729 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2732 if (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
)
2735 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2736 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2737 4, buf
, &size_read
)) != ERROR_OK
)
2739 LOG_ERROR("error while reading instruction: %i", retval
);
2740 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2742 opcode
= target_buffer_get_u32(target
, buf
);
2743 arm_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2745 else if (xscale
->trace
.core_state
== ARMV4_5_STATE_THUMB
)
2748 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2749 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2750 2, buf
, &size_read
)) != ERROR_OK
)
2752 LOG_ERROR("error while reading instruction: %i", retval
);
2753 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2755 opcode
= target_buffer_get_u16(target
, buf
);
2756 thumb_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2760 LOG_ERROR("BUG: unknown core state encountered");
2767 int xscale_branch_address(xscale_trace_data_t
*trace_data
, int i
, u32
*target
)
2769 /* if there are less than four entries prior to the indirect branch message
2770 * we can't extract the address */
2776 *target
= (trace_data
->entries
[i
-1].data
) | (trace_data
->entries
[i
-2].data
<< 8) |
2777 (trace_data
->entries
[i
-3].data
<< 16) | (trace_data
->entries
[i
-4].data
<< 24);
2782 int xscale_analyze_trace(target_t
*target
, command_context_t
*cmd_ctx
)
2784 /* get pointers to arch-specific information */
2785 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2786 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2789 xscale_trace_data_t
*trace_data
= xscale
->trace
.data
;
2798 xscale
->trace
.core_state
= ARMV4_5_STATE_ARM
;
2803 for (i
= 0; i
< trace_data
->depth
; i
++)
2809 if (trace_data
->entries
[i
].type
== XSCALE_TRACE_ADDRESS
)
2812 switch ((trace_data
->entries
[i
].data
& 0xf0) >> 4)
2814 case 0: /* Exceptions */
2822 exception
= (trace_data
->entries
[i
].data
& 0x70) >> 4;
2824 next_pc
= (trace_data
->entries
[i
].data
& 0xf0) >> 2;
2825 command_print(cmd_ctx
, "--- exception %i ---", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2827 case 8: /* Direct Branch */
2830 case 9: /* Indirect Branch */
2832 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2837 case 13: /* Checkpointed Indirect Branch */
2838 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2841 if (((chkpt
== 0) && (next_pc
!= trace_data
->chkpt0
))
2842 || ((chkpt
== 1) && (next_pc
!= trace_data
->chkpt1
)))
2843 LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2845 /* explicit fall-through */
2846 case 12: /* Checkpointed Direct Branch */
2851 next_pc
= trace_data
->chkpt0
;
2854 else if (chkpt
== 1)
2857 next_pc
= trace_data
->chkpt0
;
2862 LOG_WARNING("more than two checkpointed branches encountered");
2865 case 15: /* Roll-over */
2868 default: /* Reserved */
2869 command_print(cmd_ctx
, "--- reserved trace message ---");
2870 LOG_ERROR("BUG: trace message %i is reserved", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2874 if (xscale
->trace
.pc_ok
)
2876 int executed
= (trace_data
->entries
[i
].data
& 0xf) + rollover
* 16;
2877 arm_instruction_t instruction
;
2879 if ((exception
== 6) || (exception
== 7))
2881 /* IRQ or FIQ exception, no instruction executed */
2885 while (executed
-- >= 0)
2887 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2889 /* can't continue tracing with no image available */
2890 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2894 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2896 /* TODO: handle incomplete images */
2900 /* a precise abort on a load to the PC is included in the incremental
2901 * word count, other instructions causing data aborts are not included
2903 if ((executed
== 0) && (exception
== 4)
2904 && ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDM
)))
2906 if ((instruction
.type
== ARM_LDM
)
2907 && ((instruction
.info
.load_store_multiple
.register_list
& 0x8000) == 0))
2911 else if (((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDRSH
))
2912 && (instruction
.info
.load_store
.Rd
!= 15))
2918 /* only the last instruction executed
2919 * (the one that caused the control flow change)
2920 * could be a taken branch
2922 if (((executed
== -1) && (branch
== 1)) &&
2923 (((instruction
.type
== ARM_B
) ||
2924 (instruction
.type
== ARM_BL
) ||
2925 (instruction
.type
== ARM_BLX
)) &&
2926 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff)))
2928 xscale
->trace
.current_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
2932 xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
2934 command_print(cmd_ctx
, "%s", instruction
.text
);
2942 xscale
->trace
.current_pc
= next_pc
;
2943 xscale
->trace
.pc_ok
= 1;
2947 for (; xscale
->trace
.current_pc
< trace_data
->last_instruction
; xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2)
2949 arm_instruction_t instruction
;
2950 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2952 /* can't continue tracing with no image available */
2953 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2957 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2959 /* TODO: handle incomplete images */
2962 command_print(cmd_ctx
, "%s", instruction
.text
);
2965 trace_data
= trace_data
->next
;
2971 void xscale_build_reg_cache(target_t
*target
)
2973 /* get pointers to arch-specific information */
2974 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2975 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2977 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2978 xscale_reg_t
*arch_info
= malloc(sizeof(xscale_reg_arch_info
));
2980 int num_regs
= sizeof(xscale_reg_arch_info
) / sizeof(xscale_reg_t
);
2982 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
2983 armv4_5
->core_cache
= (*cache_p
);
2985 /* register a register arch-type for XScale dbg registers only once */
2986 if (xscale_reg_arch_type
== -1)
2987 xscale_reg_arch_type
= register_reg_arch_type(xscale_get_reg
, xscale_set_reg
);
2989 (*cache_p
)->next
= malloc(sizeof(reg_cache_t
));
2990 cache_p
= &(*cache_p
)->next
;
2992 /* fill in values for the xscale reg cache */
2993 (*cache_p
)->name
= "XScale registers";
2994 (*cache_p
)->next
= NULL
;
2995 (*cache_p
)->reg_list
= malloc(num_regs
* sizeof(reg_t
));
2996 (*cache_p
)->num_regs
= num_regs
;
2998 for (i
= 0; i
< num_regs
; i
++)
3000 (*cache_p
)->reg_list
[i
].name
= xscale_reg_list
[i
];
3001 (*cache_p
)->reg_list
[i
].value
= calloc(4, 1);
3002 (*cache_p
)->reg_list
[i
].dirty
= 0;
3003 (*cache_p
)->reg_list
[i
].valid
= 0;
3004 (*cache_p
)->reg_list
[i
].size
= 32;
3005 (*cache_p
)->reg_list
[i
].bitfield_desc
= NULL
;
3006 (*cache_p
)->reg_list
[i
].num_bitfields
= 0;
3007 (*cache_p
)->reg_list
[i
].arch_info
= &arch_info
[i
];
3008 (*cache_p
)->reg_list
[i
].arch_type
= xscale_reg_arch_type
;
3009 arch_info
[i
] = xscale_reg_arch_info
[i
];
3010 arch_info
[i
].target
= target
;
3013 xscale
->reg_cache
= (*cache_p
);
3016 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
3021 int xscale_quit(void)
3026 int xscale_init_arch_info(target_t
*target
, xscale_common_t
*xscale
, jtag_tap_t
*tap
, const char *variant
)
3028 armv4_5_common_t
*armv4_5
;
3029 u32 high_reset_branch
, low_reset_branch
;
3032 armv4_5
= &xscale
->armv4_5_common
;
3034 /* store architecture specfic data (none so far) */
3035 xscale
->arch_info
= NULL
;
3036 xscale
->common_magic
= XSCALE_COMMON_MAGIC
;
3038 /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
3039 xscale
->variant
= strdup(variant
);
3041 /* prepare JTAG information for the new target */
3042 xscale
->jtag_info
.tap
= tap
;
3044 xscale
->jtag_info
.dbgrx
= 0x02;
3045 xscale
->jtag_info
.dbgtx
= 0x10;
3046 xscale
->jtag_info
.dcsr
= 0x09;
3047 xscale
->jtag_info
.ldic
= 0x07;
3049 if ((strcmp(xscale
->variant
, "pxa250") == 0) ||
3050 (strcmp(xscale
->variant
, "pxa255") == 0) ||
3051 (strcmp(xscale
->variant
, "pxa26x") == 0))
3053 xscale
->jtag_info
.ir_length
= 5;
3055 else if ((strcmp(xscale
->variant
, "pxa27x") == 0) ||
3056 (strcmp(xscale
->variant
, "ixp42x") == 0) ||
3057 (strcmp(xscale
->variant
, "ixp45x") == 0) ||
3058 (strcmp(xscale
->variant
, "ixp46x") == 0))
3060 xscale
->jtag_info
.ir_length
= 7;
3063 /* the debug handler isn't installed (and thus not running) at this time */
3064 xscale
->handler_installed
= 0;
3065 xscale
->handler_running
= 0;
3066 xscale
->handler_address
= 0xfe000800;
3068 /* clear the vectors we keep locally for reference */
3069 memset(xscale
->low_vectors
, 0, sizeof(xscale
->low_vectors
));
3070 memset(xscale
->high_vectors
, 0, sizeof(xscale
->high_vectors
));
3072 /* no user-specified vectors have been configured yet */
3073 xscale
->static_low_vectors_set
= 0x0;
3074 xscale
->static_high_vectors_set
= 0x0;
3076 /* calculate branches to debug handler */
3077 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
3078 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
3080 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
3081 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
3083 for (i
= 1; i
<= 7; i
++)
3085 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3086 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3089 /* 64kB aligned region used for DCache cleaning */
3090 xscale
->cache_clean_address
= 0xfffe0000;
3092 xscale
->hold_rst
= 0;
3093 xscale
->external_debug_break
= 0;
3095 xscale
->ibcr_available
= 2;
3096 xscale
->ibcr0_used
= 0;
3097 xscale
->ibcr1_used
= 0;
3099 xscale
->dbr_available
= 2;
3100 xscale
->dbr0_used
= 0;
3101 xscale
->dbr1_used
= 0;
3103 xscale
->arm_bkpt
= ARMV5_BKPT(0x0);
3104 xscale
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
3106 xscale
->vector_catch
= 0x1;
3108 xscale
->trace
.capture_status
= TRACE_IDLE
;
3109 xscale
->trace
.data
= NULL
;
3110 xscale
->trace
.image
= NULL
;
3111 xscale
->trace
.buffer_enabled
= 0;
3112 xscale
->trace
.buffer_fill
= 0;
3114 /* prepare ARMv4/5 specific information */
3115 armv4_5
->arch_info
= xscale
;
3116 armv4_5
->read_core_reg
= xscale_read_core_reg
;
3117 armv4_5
->write_core_reg
= xscale_write_core_reg
;
3118 armv4_5
->full_context
= xscale_full_context
;
3120 armv4_5_init_arch_info(target
, armv4_5
);
3122 xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
3123 xscale
->armv4_5_mmu
.get_ttb
= xscale_get_ttb
;
3124 xscale
->armv4_5_mmu
.read_memory
= xscale_read_memory
;
3125 xscale
->armv4_5_mmu
.write_memory
= xscale_write_memory
;
3126 xscale
->armv4_5_mmu
.disable_mmu_caches
= xscale_disable_mmu_caches
;
3127 xscale
->armv4_5_mmu
.enable_mmu_caches
= xscale_enable_mmu_caches
;
3128 xscale
->armv4_5_mmu
.has_tiny_pages
= 1;
3129 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3134 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
3135 int xscale_target_create(struct target_s
*target
, Jim_Interp
*interp
)
3137 xscale_common_t
*xscale
= calloc(1,sizeof(xscale_common_t
));
3139 xscale_init_arch_info(target
, xscale
, target
->tap
, target
->variant
);
3140 xscale_build_reg_cache(target
);
3145 int xscale_handle_debug_handler_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3147 target_t
*target
= NULL
;
3148 armv4_5_common_t
*armv4_5
;
3149 xscale_common_t
*xscale
;
3151 u32 handler_address
;
3155 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3159 if ((target
= get_target_by_num(strtoul(args
[0], NULL
, 0))) == NULL
)
3161 LOG_ERROR("no target '%s' configured", args
[0]);
3165 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3170 handler_address
= strtoul(args
[1], NULL
, 0);
3172 if (((handler_address
>= 0x800) && (handler_address
<= 0x1fef800)) ||
3173 ((handler_address
>= 0xfe000800) && (handler_address
<= 0xfffff800)))
3175 xscale
->handler_address
= handler_address
;
3179 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3186 int xscale_handle_cache_clean_address_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3188 target_t
*target
= NULL
;
3189 armv4_5_common_t
*armv4_5
;
3190 xscale_common_t
*xscale
;
3192 u32 cache_clean_address
;
3196 return ERROR_COMMAND_SYNTAX_ERROR
;
3199 if ((target
= get_target_by_num(strtoul(args
[0], NULL
, 0))) == NULL
)
3201 LOG_ERROR("no target '%s' configured", args
[0]);
3205 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3210 cache_clean_address
= strtoul(args
[1], NULL
, 0);
3212 if (cache_clean_address
& 0xffff)
3214 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3218 xscale
->cache_clean_address
= cache_clean_address
;
3224 int xscale_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3226 target_t
*target
= get_current_target(cmd_ctx
);
3227 armv4_5_common_t
*armv4_5
;
3228 xscale_common_t
*xscale
;
3230 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3235 return armv4_5_handle_cache_info_command(cmd_ctx
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
3238 static int xscale_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
)
3240 armv4_5_common_t
*armv4_5
;
3241 xscale_common_t
*xscale
;
3248 if ((retval
= xscale_get_arch_pointers(target
, &armv4_5
, &xscale
)) != ERROR_OK
)
3252 u32 ret
= armv4_5_mmu_translate_va(target
, &xscale
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
3261 static int xscale_mmu(struct target_s
*target
, int *enabled
)
3263 armv4_5_common_t
*armv4_5
= target
->arch_info
;
3264 xscale_common_t
*xscale
= armv4_5
->arch_info
;
3266 if (target
->state
!= TARGET_HALTED
)
3268 LOG_ERROR("Target not halted");
3269 return ERROR_TARGET_INVALID
;
3271 *enabled
= xscale
->armv4_5_mmu
.mmu_enabled
;
3275 int xscale_handle_mmu_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3277 target_t
*target
= get_current_target(cmd_ctx
);
3278 armv4_5_common_t
*armv4_5
;
3279 xscale_common_t
*xscale
;
3281 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3286 if (target
->state
!= TARGET_HALTED
)
3288 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3294 if (strcmp("enable", args
[0]) == 0)
3296 xscale_enable_mmu_caches(target
, 1, 0, 0);
3297 xscale
->armv4_5_mmu
.mmu_enabled
= 1;
3299 else if (strcmp("disable", args
[0]) == 0)
3301 xscale_disable_mmu_caches(target
, 1, 0, 0);
3302 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3306 command_print(cmd_ctx
, "mmu %s", (xscale
->armv4_5_mmu
.mmu_enabled
) ? "enabled" : "disabled");
3311 int xscale_handle_idcache_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3313 target_t
*target
= get_current_target(cmd_ctx
);
3314 armv4_5_common_t
*armv4_5
;
3315 xscale_common_t
*xscale
;
3316 int icache
= 0, dcache
= 0;
3318 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3323 if (target
->state
!= TARGET_HALTED
)
3325 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3329 if (strcmp(cmd
, "icache") == 0)
3331 else if (strcmp(cmd
, "dcache") == 0)
3336 if (strcmp("enable", args
[0]) == 0)
3338 xscale_enable_mmu_caches(target
, 0, dcache
, icache
);
3341 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 1;
3343 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 1;
3345 else if (strcmp("disable", args
[0]) == 0)
3347 xscale_disable_mmu_caches(target
, 0, dcache
, icache
);
3350 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
3352 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
3357 command_print(cmd_ctx
, "icache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
) ? "enabled" : "disabled");
3360 command_print(cmd_ctx
, "dcache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) ? "enabled" : "disabled");
3365 int xscale_handle_vector_catch_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3367 target_t
*target
= get_current_target(cmd_ctx
);
3368 armv4_5_common_t
*armv4_5
;
3369 xscale_common_t
*xscale
;
3371 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3378 command_print(cmd_ctx
, "usage: xscale vector_catch [mask]");
3382 xscale
->vector_catch
= strtoul(args
[0], NULL
, 0);
3383 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 8, xscale
->vector_catch
);
3384 xscale_write_dcsr(target
, -1, -1);
3387 command_print(cmd_ctx
, "vector catch mask: 0x%2.2x", xscale
->vector_catch
);
3393 int xscale_handle_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3395 target_t
*target
= get_current_target(cmd_ctx
);
3396 armv4_5_common_t
*armv4_5
;
3397 xscale_common_t
*xscale
;
3400 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3405 if (target
->state
!= TARGET_HALTED
)
3407 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3411 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
3413 xscale_trace_data_t
*td
, *next_td
;
3414 xscale
->trace
.buffer_enabled
= 1;
3416 /* free old trace data */
3417 td
= xscale
->trace
.data
;
3427 xscale
->trace
.data
= NULL
;
3429 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
3431 xscale
->trace
.buffer_enabled
= 0;
3434 if ((argc
>= 2) && (strcmp("fill", args
[1]) == 0))
3437 xscale
->trace
.buffer_fill
= strtoul(args
[2], NULL
, 0);
3439 xscale
->trace
.buffer_fill
= 1;
3441 else if ((argc
>= 2) && (strcmp("wrap", args
[1]) == 0))
3443 xscale
->trace
.buffer_fill
= -1;
3446 if (xscale
->trace
.buffer_enabled
)
3448 /* if we enable the trace buffer in fill-once
3449 * mode we know the address of the first instruction */
3450 xscale
->trace
.pc_ok
= 1;
3451 xscale
->trace
.current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
3455 /* otherwise the address is unknown, and we have no known good PC */
3456 xscale
->trace
.pc_ok
= 0;
3459 command_print(cmd_ctx
, "trace buffer %s (%s)",
3460 (xscale
->trace
.buffer_enabled
) ? "enabled" : "disabled",
3461 (xscale
->trace
.buffer_fill
> 0) ? "fill" : "wrap");
3463 dcsr_value
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32);
3464 if (xscale
->trace
.buffer_fill
>= 0)
3465 xscale_write_dcsr_sw(target
, (dcsr_value
& 0xfffffffc) | 2);
3467 xscale_write_dcsr_sw(target
, dcsr_value
& 0xfffffffc);
3472 int xscale_handle_trace_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3475 armv4_5_common_t
*armv4_5
;
3476 xscale_common_t
*xscale
;
3480 command_print(cmd_ctx
, "usage: xscale trace_image <file> [base address] [type]");
3484 target
= get_current_target(cmd_ctx
);
3486 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3491 if (xscale
->trace
.image
)
3493 image_close(xscale
->trace
.image
);
3494 free(xscale
->trace
.image
);
3495 command_print(cmd_ctx
, "previously loaded image found and closed");
3498 xscale
->trace
.image
= malloc(sizeof(image_t
));
3499 xscale
->trace
.image
->base_address_set
= 0;
3500 xscale
->trace
.image
->start_address_set
= 0;
3502 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3505 xscale
->trace
.image
->base_address_set
= 1;
3506 xscale
->trace
.image
->base_address
= strtoul(args
[1], NULL
, 0);
3510 xscale
->trace
.image
->base_address_set
= 0;
3513 if (image_open(xscale
->trace
.image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
3515 free(xscale
->trace
.image
);
3516 xscale
->trace
.image
= NULL
;
3523 int xscale_handle_dump_trace_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3525 target_t
*target
= get_current_target(cmd_ctx
);
3526 armv4_5_common_t
*armv4_5
;
3527 xscale_common_t
*xscale
;
3528 xscale_trace_data_t
*trace_data
;
3531 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3536 if (target
->state
!= TARGET_HALTED
)
3538 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3544 command_print(cmd_ctx
, "usage: xscale dump_trace <file>");
3548 trace_data
= xscale
->trace
.data
;
3552 command_print(cmd_ctx
, "no trace data collected");
3556 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
3565 fileio_write_u32(&file
, trace_data
->chkpt0
);
3566 fileio_write_u32(&file
, trace_data
->chkpt1
);
3567 fileio_write_u32(&file
, trace_data
->last_instruction
);
3568 fileio_write_u32(&file
, trace_data
->depth
);
3570 for (i
= 0; i
< trace_data
->depth
; i
++)
3571 fileio_write_u32(&file
, trace_data
->entries
[i
].data
| ((trace_data
->entries
[i
].type
& 0xffff) << 16));
3573 trace_data
= trace_data
->next
;
3576 fileio_close(&file
);
3581 int xscale_handle_analyze_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3583 target_t
*target
= get_current_target(cmd_ctx
);
3584 armv4_5_common_t
*armv4_5
;
3585 xscale_common_t
*xscale
;
3587 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3592 xscale_analyze_trace(target
, cmd_ctx
);
3597 int xscale_handle_cp15(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3599 target_t
*target
= get_current_target(cmd_ctx
);
3600 armv4_5_common_t
*armv4_5
;
3601 xscale_common_t
*xscale
;
3603 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3608 if (target
->state
!= TARGET_HALTED
)
3610 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3617 reg_no
= strtoul(args
[0], NULL
, 0);
3618 /*translate from xscale cp15 register no to openocd register*/
3622 reg_no
= XSCALE_MAINID
;
3625 reg_no
= XSCALE_CTRL
;
3628 reg_no
= XSCALE_TTB
;
3631 reg_no
= XSCALE_DAC
;
3634 reg_no
= XSCALE_FSR
;
3637 reg_no
= XSCALE_FAR
;
3640 reg_no
= XSCALE_PID
;
3643 reg_no
= XSCALE_CPACCESS
;
3646 command_print(cmd_ctx
, "invalid register number");
3647 return ERROR_INVALID_ARGUMENTS
;
3649 reg
= &xscale
->reg_cache
->reg_list
[reg_no
];
3656 /* read cp15 control register */
3657 xscale_get_reg(reg
);
3658 value
= buf_get_u32(reg
->value
, 0, 32);
3659 command_print(cmd_ctx
, "%s (/%i): 0x%x", reg
->name
, reg
->size
, value
);
3664 u32 value
= strtoul(args
[1], NULL
, 0);
3666 /* send CP write request (command 0x41) */
3667 xscale_send_u32(target
, 0x41);
3669 /* send CP register number */
3670 xscale_send_u32(target
, reg_no
);
3672 /* send CP register value */
3673 xscale_send_u32(target
, value
);
3675 /* execute cpwait to ensure outstanding operations complete */
3676 xscale_send_u32(target
, 0x53);
3680 command_print(cmd_ctx
, "usage: cp15 [register]<, [value]>");
3686 int xscale_register_commands(struct command_context_s
*cmd_ctx
)
3688 command_t
*xscale_cmd
;
3690 xscale_cmd
= register_command(cmd_ctx
, NULL
, "xscale", NULL
, COMMAND_ANY
, "xscale specific commands");
3692 register_command(cmd_ctx
, xscale_cmd
, "debug_handler", xscale_handle_debug_handler_command
, COMMAND_ANY
, "'xscale debug_handler <target#> <address>' command takes two required operands");
3693 register_command(cmd_ctx
, xscale_cmd
, "cache_clean_address", xscale_handle_cache_clean_address_command
, COMMAND_ANY
, NULL
);
3695 register_command(cmd_ctx
, xscale_cmd
, "cache_info", xscale_handle_cache_info_command
, COMMAND_EXEC
, NULL
);
3696 register_command(cmd_ctx
, xscale_cmd
, "mmu", xscale_handle_mmu_command
, COMMAND_EXEC
, "['enable'|'disable'] the MMU");
3697 register_command(cmd_ctx
, xscale_cmd
, "icache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the ICache");
3698 register_command(cmd_ctx
, xscale_cmd
, "dcache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the DCache");
3700 register_command(cmd_ctx
, xscale_cmd
, "vector_catch", xscale_handle_vector_catch_command
, COMMAND_EXEC
, "<mask> of vectors that should be catched");
3702 register_command(cmd_ctx
, xscale_cmd
, "trace_buffer", xscale_handle_trace_buffer_command
, COMMAND_EXEC
, "<enable|disable> ['fill' [n]|'wrap']");
3704 register_command(cmd_ctx
, xscale_cmd
, "dump_trace", xscale_handle_dump_trace_command
, COMMAND_EXEC
, "dump content of trace buffer to <file>");
3705 register_command(cmd_ctx
, xscale_cmd
, "analyze_trace", xscale_handle_analyze_trace_buffer_command
, COMMAND_EXEC
, "analyze content of trace buffer");
3706 register_command(cmd_ctx
, xscale_cmd
, "trace_image", xscale_handle_trace_image_command
,
3707 COMMAND_EXEC
, "load image from <file> [base address]");
3709 register_command(cmd_ctx
, xscale_cmd
, "cp15", xscale_handle_cp15
, COMMAND_EXEC
, "access coproc 15 <register> [value]");
3711 armv4_5_register_commands(cmd_ctx
);
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