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[openocd.git] / src / target / xscale.c
1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "replacements.h"
28
29 #include "xscale.h"
30
31 #include "arm7_9_common.h"
32 #include "register.h"
33 #include "target.h"
34 #include "armv4_5.h"
35 #include "arm_simulator.h"
36 #include "arm_disassembler.h"
37 #include "log.h"
38 #include "jtag.h"
39 #include "binarybuffer.h"
40 #include "time_support.h"
41 #include "breakpoints.h"
42 #include "fileio.h"
43
44 #include <stdlib.h>
45 #include <string.h>
46
47 #include <sys/types.h>
48 #include <unistd.h>
49 #include <errno.h>
50
51
52 /* cli handling */
53 int xscale_register_commands(struct command_context_s *cmd_ctx);
54
55 /* forward declarations */
56 int xscale_target_create(struct target_s *target, Jim_Interp *interp);
57 int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
58 int xscale_quit(void);
59
60 int xscale_arch_state(struct target_s *target);
61 int xscale_poll(target_t *target);
62 int xscale_halt(target_t *target);
63 int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
64 int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
65 int xscale_debug_entry(target_t *target);
66 int xscale_restore_context(target_t *target);
67
68 int xscale_assert_reset(target_t *target);
69 int xscale_deassert_reset(target_t *target);
70 int xscale_soft_reset_halt(struct target_s *target);
71
72 int xscale_set_reg_u32(reg_t *reg, u32 value);
73
74 int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
75 int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value);
76
77 int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
78 int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
79 int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
80
81 int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
82 int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
83 int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
84 int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
85 int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
86 int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
87 void xscale_enable_watchpoints(struct target_s *target);
88 void xscale_enable_breakpoints(struct target_s *target);
89 static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
90 static int xscale_mmu(struct target_s *target, int *enabled);
91
92 int xscale_read_trace(target_t *target);
93
94 target_type_t xscale_target =
95 {
96 .name = "xscale",
97
98 .poll = xscale_poll,
99 .arch_state = xscale_arch_state,
100
101 .target_request_data = NULL,
102
103 .halt = xscale_halt,
104 .resume = xscale_resume,
105 .step = xscale_step,
106
107 .assert_reset = xscale_assert_reset,
108 .deassert_reset = xscale_deassert_reset,
109 .soft_reset_halt = xscale_soft_reset_halt,
110
111 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
112
113 .read_memory = xscale_read_memory,
114 .write_memory = xscale_write_memory,
115 .bulk_write_memory = xscale_bulk_write_memory,
116 .checksum_memory = arm7_9_checksum_memory,
117 .blank_check_memory = arm7_9_blank_check_memory,
118
119 .run_algorithm = armv4_5_run_algorithm,
120
121 .add_breakpoint = xscale_add_breakpoint,
122 .remove_breakpoint = xscale_remove_breakpoint,
123 .add_watchpoint = xscale_add_watchpoint,
124 .remove_watchpoint = xscale_remove_watchpoint,
125
126 .register_commands = xscale_register_commands,
127 .target_create = xscale_target_create,
128 .init_target = xscale_init_target,
129 .quit = xscale_quit,
130
131 .virt2phys = xscale_virt2phys,
132 .mmu = xscale_mmu
133 };
134
135 char* xscale_reg_list[] =
136 {
137 "XSCALE_MAINID", /* 0 */
138 "XSCALE_CACHETYPE",
139 "XSCALE_CTRL",
140 "XSCALE_AUXCTRL",
141 "XSCALE_TTB",
142 "XSCALE_DAC",
143 "XSCALE_FSR",
144 "XSCALE_FAR",
145 "XSCALE_PID",
146 "XSCALE_CPACCESS",
147 "XSCALE_IBCR0", /* 10 */
148 "XSCALE_IBCR1",
149 "XSCALE_DBR0",
150 "XSCALE_DBR1",
151 "XSCALE_DBCON",
152 "XSCALE_TBREG",
153 "XSCALE_CHKPT0",
154 "XSCALE_CHKPT1",
155 "XSCALE_DCSR",
156 "XSCALE_TX",
157 "XSCALE_RX", /* 20 */
158 "XSCALE_TXRXCTRL",
159 };
160
161 xscale_reg_t xscale_reg_arch_info[] =
162 {
163 {XSCALE_MAINID, NULL},
164 {XSCALE_CACHETYPE, NULL},
165 {XSCALE_CTRL, NULL},
166 {XSCALE_AUXCTRL, NULL},
167 {XSCALE_TTB, NULL},
168 {XSCALE_DAC, NULL},
169 {XSCALE_FSR, NULL},
170 {XSCALE_FAR, NULL},
171 {XSCALE_PID, NULL},
172 {XSCALE_CPACCESS, NULL},
173 {XSCALE_IBCR0, NULL},
174 {XSCALE_IBCR1, NULL},
175 {XSCALE_DBR0, NULL},
176 {XSCALE_DBR1, NULL},
177 {XSCALE_DBCON, NULL},
178 {XSCALE_TBREG, NULL},
179 {XSCALE_CHKPT0, NULL},
180 {XSCALE_CHKPT1, NULL},
181 {XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */
182 {-1, NULL}, /* TX accessed via JTAG */
183 {-1, NULL}, /* RX accessed via JTAG */
184 {-1, NULL}, /* TXRXCTRL implicit access via JTAG */
185 };
186
187 int xscale_reg_arch_type = -1;
188
189 int xscale_get_reg(reg_t *reg);
190 int xscale_set_reg(reg_t *reg, u8 *buf);
191
192 int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p)
193 {
194 armv4_5_common_t *armv4_5 = target->arch_info;
195 xscale_common_t *xscale = armv4_5->arch_info;
196
197 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
198 {
199 LOG_ERROR("target isn't an XScale target");
200 return -1;
201 }
202
203 if (xscale->common_magic != XSCALE_COMMON_MAGIC)
204 {
205 LOG_ERROR("target isn't an XScale target");
206 return -1;
207 }
208
209 *armv4_5_p = armv4_5;
210 *xscale_p = xscale;
211
212 return ERROR_OK;
213 }
214
215 int xscale_jtag_set_instr(int chain_pos, u32 new_instr)
216 {
217 jtag_device_t *device = jtag_get_device(chain_pos);
218
219 if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
220 {
221 scan_field_t field;
222
223 field.device = chain_pos;
224 field.num_bits = device->ir_length;
225 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
226 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
227 field.out_mask = NULL;
228 field.in_value = NULL;
229 jtag_set_check_value(&field, device->expected, device->expected_mask, NULL);
230
231 jtag_add_ir_scan(1, &field, -1);
232
233 free(field.out_value);
234 }
235
236 return ERROR_OK;
237 }
238
239 int xscale_read_dcsr(target_t *target)
240 {
241 armv4_5_common_t *armv4_5 = target->arch_info;
242 xscale_common_t *xscale = armv4_5->arch_info;
243
244 int retval;
245
246 scan_field_t fields[3];
247 u8 field0 = 0x0;
248 u8 field0_check_value = 0x2;
249 u8 field0_check_mask = 0x7;
250 u8 field2 = 0x0;
251 u8 field2_check_value = 0x0;
252 u8 field2_check_mask = 0x1;
253
254 jtag_add_end_state(TAP_PD);
255 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
256
257 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
258 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
259
260 fields[0].device = xscale->jtag_info.chain_pos;
261 fields[0].num_bits = 3;
262 fields[0].out_value = &field0;
263 fields[0].out_mask = NULL;
264 fields[0].in_value = NULL;
265 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
266
267 fields[1].device = xscale->jtag_info.chain_pos;
268 fields[1].num_bits = 32;
269 fields[1].out_value = NULL;
270 fields[1].out_mask = NULL;
271 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
272 fields[1].in_handler = NULL;
273 fields[1].in_handler_priv = NULL;
274 fields[1].in_check_value = NULL;
275 fields[1].in_check_mask = NULL;
276
277 fields[2].device = xscale->jtag_info.chain_pos;
278 fields[2].num_bits = 1;
279 fields[2].out_value = &field2;
280 fields[2].out_mask = NULL;
281 fields[2].in_value = NULL;
282 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
283
284 jtag_add_dr_scan(3, fields, -1);
285
286 if ((retval = jtag_execute_queue()) != ERROR_OK)
287 {
288 LOG_ERROR("JTAG error while reading DCSR");
289 return retval;
290 }
291
292 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
293 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
294
295 /* write the register with the value we just read
296 * on this second pass, only the first bit of field0 is guaranteed to be 0)
297 */
298 field0_check_mask = 0x1;
299 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
300 fields[1].in_value = NULL;
301
302 jtag_add_end_state(TAP_RTI);
303
304 jtag_add_dr_scan(3, fields, -1);
305
306 /* DANGER!!! this must be here. It will make sure that the arguments
307 * to jtag_set_check_value() does not go out of scope! */
308 return jtag_execute_queue();
309 }
310
311 int xscale_receive(target_t *target, u32 *buffer, int num_words)
312 {
313 if (num_words==0)
314 return ERROR_INVALID_ARGUMENTS;
315
316 int retval=ERROR_OK;
317 armv4_5_common_t *armv4_5 = target->arch_info;
318 xscale_common_t *xscale = armv4_5->arch_info;
319
320 enum tap_state path[3];
321 scan_field_t fields[3];
322
323 u8 *field0 = malloc(num_words * 1);
324 u8 field0_check_value = 0x2;
325 u8 field0_check_mask = 0x6;
326 u32 *field1 = malloc(num_words * 4);
327 u8 field2_check_value = 0x0;
328 u8 field2_check_mask = 0x1;
329 int words_done = 0;
330 int words_scheduled = 0;
331
332 int i;
333
334 path[0] = TAP_SDS;
335 path[1] = TAP_CD;
336 path[2] = TAP_SD;
337
338 fields[0].device = xscale->jtag_info.chain_pos;
339 fields[0].num_bits = 3;
340 fields[0].out_value = NULL;
341 fields[0].out_mask = NULL;
342 fields[0].in_value = NULL;
343 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
344
345 fields[1].device = xscale->jtag_info.chain_pos;
346 fields[1].num_bits = 32;
347 fields[1].out_value = NULL;
348 fields[1].out_mask = NULL;
349 fields[1].in_value = NULL;
350 fields[1].in_handler = NULL;
351 fields[1].in_handler_priv = NULL;
352 fields[1].in_check_value = NULL;
353 fields[1].in_check_mask = NULL;
354
355
356
357 fields[2].device = xscale->jtag_info.chain_pos;
358 fields[2].num_bits = 1;
359 fields[2].out_value = NULL;
360 fields[2].out_mask = NULL;
361 fields[2].in_value = NULL;
362 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
363
364 jtag_add_end_state(TAP_RTI);
365 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
366 jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
367
368 /* repeat until all words have been collected */
369 int attempts=0;
370 while (words_done < num_words)
371 {
372 /* schedule reads */
373 words_scheduled = 0;
374 for (i = words_done; i < num_words; i++)
375 {
376 fields[0].in_value = &field0[i];
377 fields[1].in_handler = buf_to_u32_handler;
378 fields[1].in_handler_priv = (u8*)&field1[i];
379
380 jtag_add_pathmove(3, path);
381 jtag_add_dr_scan(3, fields, TAP_RTI);
382 words_scheduled++;
383 }
384
385 if ((retval = jtag_execute_queue()) != ERROR_OK)
386 {
387 LOG_ERROR("JTAG error while receiving data from debug handler");
388 break;
389 }
390
391 /* examine results */
392 for (i = words_done; i < num_words; i++)
393 {
394 if (!(field0[0] & 1))
395 {
396 /* move backwards if necessary */
397 int j;
398 for (j = i; j < num_words - 1; j++)
399 {
400 field0[j] = field0[j+1];
401 field1[j] = field1[j+1];
402 }
403 words_scheduled--;
404 }
405 }
406 if (words_scheduled==0)
407 {
408 if (attempts++==1000)
409 {
410 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
411 retval=ERROR_TARGET_TIMEOUT;
412 break;
413 }
414 }
415
416 words_done += words_scheduled;
417 }
418
419 for (i = 0; i < num_words; i++)
420 *(buffer++) = buf_get_u32((u8*)&field1[i], 0, 32);
421
422 free(field1);
423
424 return retval;
425 }
426
427 int xscale_read_tx(target_t *target, int consume)
428 {
429 armv4_5_common_t *armv4_5 = target->arch_info;
430 xscale_common_t *xscale = armv4_5->arch_info;
431 enum tap_state path[3];
432 enum tap_state noconsume_path[6];
433
434 int retval;
435 struct timeval timeout, now;
436
437 scan_field_t fields[3];
438 u8 field0_in = 0x0;
439 u8 field0_check_value = 0x2;
440 u8 field0_check_mask = 0x6;
441 u8 field2_check_value = 0x0;
442 u8 field2_check_mask = 0x1;
443
444 jtag_add_end_state(TAP_RTI);
445
446 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
447
448 path[0] = TAP_SDS;
449 path[1] = TAP_CD;
450 path[2] = TAP_SD;
451
452 noconsume_path[0] = TAP_SDS;
453 noconsume_path[1] = TAP_CD;
454 noconsume_path[2] = TAP_E1D;
455 noconsume_path[3] = TAP_PD;
456 noconsume_path[4] = TAP_E2D;
457 noconsume_path[5] = TAP_SD;
458
459 fields[0].device = xscale->jtag_info.chain_pos;
460 fields[0].num_bits = 3;
461 fields[0].out_value = NULL;
462 fields[0].out_mask = NULL;
463 fields[0].in_value = &field0_in;
464 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
465
466 fields[1].device = xscale->jtag_info.chain_pos;
467 fields[1].num_bits = 32;
468 fields[1].out_value = NULL;
469 fields[1].out_mask = NULL;
470 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
471 fields[1].in_handler = NULL;
472 fields[1].in_handler_priv = NULL;
473 fields[1].in_check_value = NULL;
474 fields[1].in_check_mask = NULL;
475
476
477
478 fields[2].device = xscale->jtag_info.chain_pos;
479 fields[2].num_bits = 1;
480 fields[2].out_value = NULL;
481 fields[2].out_mask = NULL;
482 fields[2].in_value = NULL;
483 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
484
485 gettimeofday(&timeout, NULL);
486 timeval_add_time(&timeout, 1, 0);
487
488 for (;;)
489 {
490 /* if we want to consume the register content (i.e. clear TX_READY),
491 * we have to go straight from Capture-DR to Shift-DR
492 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
493 */
494 if (consume)
495 jtag_add_pathmove(3, path);
496 else
497 {
498 jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
499 }
500
501 jtag_add_dr_scan(3, fields, TAP_RTI);
502
503 if ((retval = jtag_execute_queue()) != ERROR_OK)
504 {
505 LOG_ERROR("JTAG error while reading TX");
506 return ERROR_TARGET_TIMEOUT;
507 }
508
509 gettimeofday(&now, NULL);
510 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
511 {
512 LOG_ERROR("time out reading TX register");
513 return ERROR_TARGET_TIMEOUT;
514 }
515 if (!((!(field0_in & 1)) && consume))
516 {
517 goto done;
518 }
519 if (debug_level>=3)
520 {
521 LOG_DEBUG("waiting 100ms");
522 alive_sleep(100); /* avoid flooding the logs */
523 } else
524 {
525 keep_alive();
526 }
527 }
528 done:
529
530 if (!(field0_in & 1))
531 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
532
533 return ERROR_OK;
534 }
535
536 int xscale_write_rx(target_t *target)
537 {
538 armv4_5_common_t *armv4_5 = target->arch_info;
539 xscale_common_t *xscale = armv4_5->arch_info;
540
541 int retval;
542 struct timeval timeout, now;
543
544 scan_field_t fields[3];
545 u8 field0_out = 0x0;
546 u8 field0_in = 0x0;
547 u8 field0_check_value = 0x2;
548 u8 field0_check_mask = 0x6;
549 u8 field2 = 0x0;
550 u8 field2_check_value = 0x0;
551 u8 field2_check_mask = 0x1;
552
553 jtag_add_end_state(TAP_RTI);
554
555 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
556
557 fields[0].device = xscale->jtag_info.chain_pos;
558 fields[0].num_bits = 3;
559 fields[0].out_value = &field0_out;
560 fields[0].out_mask = NULL;
561 fields[0].in_value = &field0_in;
562 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
563
564 fields[1].device = xscale->jtag_info.chain_pos;
565 fields[1].num_bits = 32;
566 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
567 fields[1].out_mask = NULL;
568 fields[1].in_value = NULL;
569 fields[1].in_handler = NULL;
570 fields[1].in_handler_priv = NULL;
571 fields[1].in_check_value = NULL;
572 fields[1].in_check_mask = NULL;
573
574
575
576 fields[2].device = xscale->jtag_info.chain_pos;
577 fields[2].num_bits = 1;
578 fields[2].out_value = &field2;
579 fields[2].out_mask = NULL;
580 fields[2].in_value = NULL;
581 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
582
583 gettimeofday(&timeout, NULL);
584 timeval_add_time(&timeout, 1, 0);
585
586 /* poll until rx_read is low */
587 LOG_DEBUG("polling RX");
588 for (;;)
589 {
590 jtag_add_dr_scan(3, fields, TAP_RTI);
591
592 if ((retval = jtag_execute_queue()) != ERROR_OK)
593 {
594 LOG_ERROR("JTAG error while writing RX");
595 return retval;
596 }
597
598 gettimeofday(&now, NULL);
599 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
600 {
601 LOG_ERROR("time out writing RX register");
602 return ERROR_TARGET_TIMEOUT;
603 }
604 if (!(field0_in & 1))
605 goto done;
606 if (debug_level>=3)
607 {
608 LOG_DEBUG("waiting 100ms");
609 alive_sleep(100); /* avoid flooding the logs */
610 } else
611 {
612 keep_alive();
613 }
614 }
615 done:
616
617 /* set rx_valid */
618 field2 = 0x1;
619 jtag_add_dr_scan(3, fields, TAP_RTI);
620
621 if ((retval = jtag_execute_queue()) != ERROR_OK)
622 {
623 LOG_ERROR("JTAG error while writing RX");
624 return retval;
625 }
626
627 return ERROR_OK;
628 }
629
630 /* send count elements of size byte to the debug handler */
631 int xscale_send(target_t *target, u8 *buffer, int count, int size)
632 {
633 armv4_5_common_t *armv4_5 = target->arch_info;
634 xscale_common_t *xscale = armv4_5->arch_info;
635 u32 t[3];
636 int bits[3];
637
638 int retval;
639
640 int done_count = 0;
641
642 jtag_add_end_state(TAP_RTI);
643
644 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
645
646 bits[0]=3;
647 t[0]=0;
648 bits[1]=32;
649 t[2]=1;
650 bits[2]=1;
651 int endianness = target->endianness;
652 while (done_count++ < count)
653 {
654 switch (size)
655 {
656 case 4:
657 if (endianness == TARGET_LITTLE_ENDIAN)
658 {
659 t[1]=le_to_h_u32(buffer);
660 } else
661 {
662 t[1]=be_to_h_u32(buffer);
663 }
664 break;
665 case 2:
666 if (endianness == TARGET_LITTLE_ENDIAN)
667 {
668 t[1]=le_to_h_u16(buffer);
669 } else
670 {
671 t[1]=be_to_h_u16(buffer);
672 }
673 break;
674 case 1:
675 t[1]=buffer[0];
676 break;
677 default:
678 LOG_ERROR("BUG: size neither 4, 2 nor 1");
679 exit(-1);
680 }
681 jtag_add_dr_out(xscale->jtag_info.chain_pos,
682 3,
683 bits,
684 t,
685 TAP_RTI);
686 buffer += size;
687 }
688
689 if ((retval = jtag_execute_queue()) != ERROR_OK)
690 {
691 LOG_ERROR("JTAG error while sending data to debug handler");
692 return retval;
693 }
694
695 return ERROR_OK;
696 }
697
698 int xscale_send_u32(target_t *target, u32 value)
699 {
700 armv4_5_common_t *armv4_5 = target->arch_info;
701 xscale_common_t *xscale = armv4_5->arch_info;
702
703 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
704 return xscale_write_rx(target);
705 }
706
707 int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
708 {
709 armv4_5_common_t *armv4_5 = target->arch_info;
710 xscale_common_t *xscale = armv4_5->arch_info;
711
712 int retval;
713
714 scan_field_t fields[3];
715 u8 field0 = 0x0;
716 u8 field0_check_value = 0x2;
717 u8 field0_check_mask = 0x7;
718 u8 field2 = 0x0;
719 u8 field2_check_value = 0x0;
720 u8 field2_check_mask = 0x1;
721
722 if (hold_rst != -1)
723 xscale->hold_rst = hold_rst;
724
725 if (ext_dbg_brk != -1)
726 xscale->external_debug_break = ext_dbg_brk;
727
728 jtag_add_end_state(TAP_RTI);
729 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
730
731 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
732 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
733
734 fields[0].device = xscale->jtag_info.chain_pos;
735 fields[0].num_bits = 3;
736 fields[0].out_value = &field0;
737 fields[0].out_mask = NULL;
738 fields[0].in_value = NULL;
739 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
740
741 fields[1].device = xscale->jtag_info.chain_pos;
742 fields[1].num_bits = 32;
743 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
744 fields[1].out_mask = NULL;
745 fields[1].in_value = NULL;
746 fields[1].in_handler = NULL;
747 fields[1].in_handler_priv = NULL;
748 fields[1].in_check_value = NULL;
749 fields[1].in_check_mask = NULL;
750
751
752
753 fields[2].device = xscale->jtag_info.chain_pos;
754 fields[2].num_bits = 1;
755 fields[2].out_value = &field2;
756 fields[2].out_mask = NULL;
757 fields[2].in_value = NULL;
758 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
759
760 jtag_add_dr_scan(3, fields, -1);
761
762 if ((retval = jtag_execute_queue()) != ERROR_OK)
763 {
764 LOG_ERROR("JTAG error while writing DCSR");
765 return retval;
766 }
767
768 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
769 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
770
771 return ERROR_OK;
772 }
773
774 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
775 unsigned int parity (unsigned int v)
776 {
777 unsigned int ov = v;
778 v ^= v >> 16;
779 v ^= v >> 8;
780 v ^= v >> 4;
781 v &= 0xf;
782 LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
783 return (0x6996 >> v) & 1;
784 }
785
786 int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
787 {
788 armv4_5_common_t *armv4_5 = target->arch_info;
789 xscale_common_t *xscale = armv4_5->arch_info;
790 u8 packet[4];
791 u8 cmd;
792 int word;
793
794 scan_field_t fields[2];
795
796 LOG_DEBUG("loading miniIC at 0x%8.8x", va);
797
798 jtag_add_end_state(TAP_RTI);
799 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
800
801 /* CMD is b010 for Main IC and b011 for Mini IC */
802 if (mini)
803 buf_set_u32(&cmd, 0, 3, 0x3);
804 else
805 buf_set_u32(&cmd, 0, 3, 0x2);
806
807 buf_set_u32(&cmd, 3, 3, 0x0);
808
809 /* virtual address of desired cache line */
810 buf_set_u32(packet, 0, 27, va >> 5);
811
812 fields[0].device = xscale->jtag_info.chain_pos;
813 fields[0].num_bits = 6;
814 fields[0].out_value = &cmd;
815 fields[0].out_mask = NULL;
816 fields[0].in_value = NULL;
817 fields[0].in_check_value = NULL;
818 fields[0].in_check_mask = NULL;
819 fields[0].in_handler = NULL;
820 fields[0].in_handler_priv = NULL;
821
822 fields[1].device = xscale->jtag_info.chain_pos;
823 fields[1].num_bits = 27;
824 fields[1].out_value = packet;
825 fields[1].out_mask = NULL;
826 fields[1].in_value = NULL;
827 fields[1].in_check_value = NULL;
828 fields[1].in_check_mask = NULL;
829 fields[1].in_handler = NULL;
830 fields[1].in_handler_priv = NULL;
831
832 jtag_add_dr_scan(2, fields, -1);
833
834 fields[0].num_bits = 32;
835 fields[0].out_value = packet;
836
837 fields[1].num_bits = 1;
838 fields[1].out_value = &cmd;
839
840 for (word = 0; word < 8; word++)
841 {
842 buf_set_u32(packet, 0, 32, buffer[word]);
843 cmd = parity(*((u32*)packet));
844 jtag_add_dr_scan(2, fields, -1);
845 }
846
847 jtag_execute_queue();
848
849 return ERROR_OK;
850 }
851
852 int xscale_invalidate_ic_line(target_t *target, u32 va)
853 {
854 armv4_5_common_t *armv4_5 = target->arch_info;
855 xscale_common_t *xscale = armv4_5->arch_info;
856 u8 packet[4];
857 u8 cmd;
858
859 scan_field_t fields[2];
860
861 jtag_add_end_state(TAP_RTI);
862 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
863
864 /* CMD for invalidate IC line b000, bits [6:4] b000 */
865 buf_set_u32(&cmd, 0, 6, 0x0);
866
867 /* virtual address of desired cache line */
868 buf_set_u32(packet, 0, 27, va >> 5);
869
870 fields[0].device = xscale->jtag_info.chain_pos;
871 fields[0].num_bits = 6;
872 fields[0].out_value = &cmd;
873 fields[0].out_mask = NULL;
874 fields[0].in_value = NULL;
875 fields[0].in_check_value = NULL;
876 fields[0].in_check_mask = NULL;
877 fields[0].in_handler = NULL;
878 fields[0].in_handler_priv = NULL;
879
880 fields[1].device = xscale->jtag_info.chain_pos;
881 fields[1].num_bits = 27;
882 fields[1].out_value = packet;
883 fields[1].out_mask = NULL;
884 fields[1].in_value = NULL;
885 fields[1].in_check_value = NULL;
886 fields[1].in_check_mask = NULL;
887 fields[1].in_handler = NULL;
888 fields[1].in_handler_priv = NULL;
889
890 jtag_add_dr_scan(2, fields, -1);
891
892 return ERROR_OK;
893 }
894
895 int xscale_update_vectors(target_t *target)
896 {
897 armv4_5_common_t *armv4_5 = target->arch_info;
898 xscale_common_t *xscale = armv4_5->arch_info;
899 int i;
900 int retval;
901
902 u32 low_reset_branch, high_reset_branch;
903
904 for (i = 1; i < 8; i++)
905 {
906 /* if there's a static vector specified for this exception, override */
907 if (xscale->static_high_vectors_set & (1 << i))
908 {
909 xscale->high_vectors[i] = xscale->static_high_vectors[i];
910 }
911 else
912 {
913 retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
914 if (retval == ERROR_TARGET_TIMEOUT)
915 return retval;
916 if (retval!=ERROR_OK)
917 {
918 /* Some of these reads will fail as part of normal execution */
919 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
920 }
921 }
922 }
923
924 for (i = 1; i < 8; i++)
925 {
926 if (xscale->static_low_vectors_set & (1 << i))
927 {
928 xscale->low_vectors[i] = xscale->static_low_vectors[i];
929 }
930 else
931 {
932 retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
933 if (retval == ERROR_TARGET_TIMEOUT)
934 return retval;
935 if (retval!=ERROR_OK)
936 {
937 /* Some of these reads will fail as part of normal execution */
938 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
939 }
940 }
941 }
942
943 /* calculate branches to debug handler */
944 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
945 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
946
947 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
948 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
949
950 /* invalidate and load exception vectors in mini i-cache */
951 xscale_invalidate_ic_line(target, 0x0);
952 xscale_invalidate_ic_line(target, 0xffff0000);
953
954 xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
955 xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
956
957 return ERROR_OK;
958 }
959
960 int xscale_arch_state(struct target_s *target)
961 {
962 armv4_5_common_t *armv4_5 = target->arch_info;
963 xscale_common_t *xscale = armv4_5->arch_info;
964
965 char *state[] =
966 {
967 "disabled", "enabled"
968 };
969
970 char *arch_dbg_reason[] =
971 {
972 "", "\n(processor reset)", "\n(trace buffer full)"
973 };
974
975 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
976 {
977 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
978 exit(-1);
979 }
980
981 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
982 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
983 "MMU: %s, D-Cache: %s, I-Cache: %s"
984 "%s",
985 armv4_5_state_strings[armv4_5->core_state],
986 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
987 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
988 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
989 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
990 state[xscale->armv4_5_mmu.mmu_enabled],
991 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
992 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
993 arch_dbg_reason[xscale->arch_debug_reason]);
994
995 return ERROR_OK;
996 }
997
998 int xscale_poll(target_t *target)
999 {
1000 int retval=ERROR_OK;
1001 armv4_5_common_t *armv4_5 = target->arch_info;
1002 xscale_common_t *xscale = armv4_5->arch_info;
1003
1004 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
1005 {
1006 enum target_state previous_state = target->state;
1007 if ((retval = xscale_read_tx(target, 0)) == ERROR_OK)
1008 {
1009
1010 /* there's data to read from the tx register, we entered debug state */
1011 xscale->handler_running = 1;
1012
1013 target->state = TARGET_HALTED;
1014
1015 /* process debug entry, fetching current mode regs */
1016 retval = xscale_debug_entry(target);
1017 }
1018 else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1019 {
1020 LOG_USER("error while polling TX register, reset CPU");
1021 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
1022 target->state = TARGET_HALTED;
1023 }
1024
1025 /* debug_entry could have overwritten target state (i.e. immediate resume)
1026 * don't signal event handlers in that case
1027 */
1028 if (target->state != TARGET_HALTED)
1029 return ERROR_OK;
1030
1031 /* if target was running, signal that we halted
1032 * otherwise we reentered from debug execution */
1033 if (previous_state == TARGET_RUNNING)
1034 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1035 else
1036 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
1037 }
1038
1039 return retval;
1040 }
1041
1042 int xscale_debug_entry(target_t *target)
1043 {
1044 armv4_5_common_t *armv4_5 = target->arch_info;
1045 xscale_common_t *xscale = armv4_5->arch_info;
1046 u32 pc;
1047 u32 buffer[10];
1048 int i;
1049 int retval;
1050
1051 u32 moe;
1052
1053 /* clear external dbg break (will be written on next DCSR read) */
1054 xscale->external_debug_break = 0;
1055 if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
1056 return retval;
1057
1058 /* get r0, pc, r1 to r7 and cpsr */
1059 if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK)
1060 return retval;
1061
1062 /* move r0 from buffer to register cache */
1063 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
1064 armv4_5->core_cache->reg_list[15].dirty = 1;
1065 armv4_5->core_cache->reg_list[15].valid = 1;
1066 LOG_DEBUG("r0: 0x%8.8x", buffer[0]);
1067
1068 /* move pc from buffer to register cache */
1069 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]);
1070 armv4_5->core_cache->reg_list[15].dirty = 1;
1071 armv4_5->core_cache->reg_list[15].valid = 1;
1072 LOG_DEBUG("pc: 0x%8.8x", buffer[1]);
1073
1074 /* move data from buffer to register cache */
1075 for (i = 1; i <= 7; i++)
1076 {
1077 buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
1078 armv4_5->core_cache->reg_list[i].dirty = 1;
1079 armv4_5->core_cache->reg_list[i].valid = 1;
1080 LOG_DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]);
1081 }
1082
1083 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
1084 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
1085 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1086 LOG_DEBUG("cpsr: 0x%8.8x", buffer[9]);
1087
1088 armv4_5->core_mode = buffer[9] & 0x1f;
1089 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1090 {
1091 target->state = TARGET_UNKNOWN;
1092 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1093 return ERROR_TARGET_FAILURE;
1094 }
1095 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1096
1097 if (buffer[9] & 0x20)
1098 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1099 else
1100 armv4_5->core_state = ARMV4_5_STATE_ARM;
1101
1102
1103 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1104 return ERROR_FAIL;
1105
1106 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1107 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1108 {
1109 xscale_receive(target, buffer, 8);
1110 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
1111 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1112 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1113 }
1114 else
1115 {
1116 /* r8 to r14, but no spsr */
1117 xscale_receive(target, buffer, 7);
1118 }
1119
1120 /* move data from buffer to register cache */
1121 for (i = 8; i <= 14; i++)
1122 {
1123 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, buffer[i - 8]);
1124 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1125 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1126 }
1127
1128 /* examine debug reason */
1129 xscale_read_dcsr(target);
1130 moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
1131
1132 /* stored PC (for calculating fixup) */
1133 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1134
1135 switch (moe)
1136 {
1137 case 0x0: /* Processor reset */
1138 target->debug_reason = DBG_REASON_DBGRQ;
1139 xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
1140 pc -= 4;
1141 break;
1142 case 0x1: /* Instruction breakpoint hit */
1143 target->debug_reason = DBG_REASON_BREAKPOINT;
1144 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1145 pc -= 4;
1146 break;
1147 case 0x2: /* Data breakpoint hit */
1148 target->debug_reason = DBG_REASON_WATCHPOINT;
1149 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1150 pc -= 4;
1151 break;
1152 case 0x3: /* BKPT instruction executed */
1153 target->debug_reason = DBG_REASON_BREAKPOINT;
1154 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1155 pc -= 4;
1156 break;
1157 case 0x4: /* Ext. debug event */
1158 target->debug_reason = DBG_REASON_DBGRQ;
1159 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1160 pc -= 4;
1161 break;
1162 case 0x5: /* Vector trap occured */
1163 target->debug_reason = DBG_REASON_BREAKPOINT;
1164 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1165 pc -= 4;
1166 break;
1167 case 0x6: /* Trace buffer full break */
1168 target->debug_reason = DBG_REASON_DBGRQ;
1169 xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
1170 pc -= 4;
1171 break;
1172 case 0x7: /* Reserved */
1173 default:
1174 LOG_ERROR("Method of Entry is 'Reserved'");
1175 exit(-1);
1176 break;
1177 }
1178
1179 /* apply PC fixup */
1180 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
1181
1182 /* on the first debug entry, identify cache type */
1183 if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
1184 {
1185 u32 cache_type_reg;
1186
1187 /* read cp15 cache type register */
1188 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
1189 cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value, 0, 32);
1190
1191 armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
1192 }
1193
1194 /* examine MMU and Cache settings */
1195 /* read cp15 control register */
1196 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
1197 xscale->cp15_control_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
1198 xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
1199 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
1200 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
1201
1202 /* tracing enabled, read collected trace data */
1203 if (xscale->trace.buffer_enabled)
1204 {
1205 xscale_read_trace(target);
1206 xscale->trace.buffer_fill--;
1207
1208 /* resume if we're still collecting trace data */
1209 if ((xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL)
1210 && (xscale->trace.buffer_fill > 0))
1211 {
1212 xscale_resume(target, 1, 0x0, 1, 0);
1213 }
1214 else
1215 {
1216 xscale->trace.buffer_enabled = 0;
1217 }
1218 }
1219
1220 return ERROR_OK;
1221 }
1222
1223 int xscale_halt(target_t *target)
1224 {
1225 armv4_5_common_t *armv4_5 = target->arch_info;
1226 xscale_common_t *xscale = armv4_5->arch_info;
1227
1228 LOG_DEBUG("target->state: %s",
1229 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
1230
1231 if (target->state == TARGET_HALTED)
1232 {
1233 LOG_DEBUG("target was already halted");
1234 return ERROR_OK;
1235 }
1236 else if (target->state == TARGET_UNKNOWN)
1237 {
1238 /* this must not happen for a xscale target */
1239 LOG_ERROR("target was in unknown state when halt was requested");
1240 return ERROR_TARGET_INVALID;
1241 }
1242 else if (target->state == TARGET_RESET)
1243 {
1244 LOG_DEBUG("target->state == TARGET_RESET");
1245 }
1246 else
1247 {
1248 /* assert external dbg break */
1249 xscale->external_debug_break = 1;
1250 xscale_read_dcsr(target);
1251
1252 target->debug_reason = DBG_REASON_DBGRQ;
1253 }
1254
1255 return ERROR_OK;
1256 }
1257
1258 int xscale_enable_single_step(struct target_s *target, u32 next_pc)
1259 {
1260 armv4_5_common_t *armv4_5 = target->arch_info;
1261 xscale_common_t *xscale= armv4_5->arch_info;
1262 reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1263
1264 if (xscale->ibcr0_used)
1265 {
1266 breakpoint_t *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
1267
1268 if (ibcr0_bp)
1269 {
1270 xscale_unset_breakpoint(target, ibcr0_bp);
1271 }
1272 else
1273 {
1274 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1275 exit(-1);
1276 }
1277 }
1278
1279 xscale_set_reg_u32(ibcr0, next_pc | 0x1);
1280
1281 return ERROR_OK;
1282 }
1283
1284 int xscale_disable_single_step(struct target_s *target)
1285 {
1286 armv4_5_common_t *armv4_5 = target->arch_info;
1287 xscale_common_t *xscale= armv4_5->arch_info;
1288 reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1289
1290 xscale_set_reg_u32(ibcr0, 0x0);
1291
1292 return ERROR_OK;
1293 }
1294
1295 int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1296 {
1297 armv4_5_common_t *armv4_5 = target->arch_info;
1298 xscale_common_t *xscale= armv4_5->arch_info;
1299 breakpoint_t *breakpoint = target->breakpoints;
1300
1301 u32 current_pc;
1302
1303 int retval;
1304 int i;
1305
1306 LOG_DEBUG("-");
1307
1308 if (target->state != TARGET_HALTED)
1309 {
1310 LOG_WARNING("target not halted");
1311 return ERROR_TARGET_NOT_HALTED;
1312 }
1313
1314 if (!debug_execution)
1315 {
1316 target_free_all_working_areas(target);
1317 }
1318
1319 /* update vector tables */
1320 if ((retval=xscale_update_vectors(target))!=ERROR_OK)
1321 return retval;
1322
1323 /* current = 1: continue on current pc, otherwise continue at <address> */
1324 if (!current)
1325 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1326
1327 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1328
1329 /* if we're at the reset vector, we have to simulate the branch */
1330 if (current_pc == 0x0)
1331 {
1332 arm_simulate_step(target, NULL);
1333 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1334 }
1335
1336 /* the front-end may request us not to handle breakpoints */
1337 if (handle_breakpoints)
1338 {
1339 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1340 {
1341 u32 next_pc;
1342
1343 /* there's a breakpoint at the current PC, we have to step over it */
1344 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1345 xscale_unset_breakpoint(target, breakpoint);
1346
1347 /* calculate PC of next instruction */
1348 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1349 {
1350 u32 current_opcode;
1351 target_read_u32(target, current_pc, &current_opcode);
1352 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
1353 }
1354
1355 LOG_DEBUG("enable single-step");
1356 xscale_enable_single_step(target, next_pc);
1357
1358 /* restore banked registers */
1359 xscale_restore_context(target);
1360
1361 /* send resume request (command 0x30 or 0x31)
1362 * clean the trace buffer if it is to be enabled (0x62) */
1363 if (xscale->trace.buffer_enabled)
1364 {
1365 xscale_send_u32(target, 0x62);
1366 xscale_send_u32(target, 0x31);
1367 }
1368 else
1369 xscale_send_u32(target, 0x30);
1370
1371 /* send CPSR */
1372 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1373 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1374
1375 for (i = 7; i >= 0; i--)
1376 {
1377 /* send register */
1378 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1379 LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1380 }
1381
1382 /* send PC */
1383 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1384 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1385
1386 /* wait for and process debug entry */
1387 xscale_debug_entry(target);
1388
1389 LOG_DEBUG("disable single-step");
1390 xscale_disable_single_step(target);
1391
1392 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1393 xscale_set_breakpoint(target, breakpoint);
1394 }
1395 }
1396
1397 /* enable any pending breakpoints and watchpoints */
1398 xscale_enable_breakpoints(target);
1399 xscale_enable_watchpoints(target);
1400
1401 /* restore banked registers */
1402 xscale_restore_context(target);
1403
1404 /* send resume request (command 0x30 or 0x31)
1405 * clean the trace buffer if it is to be enabled (0x62) */
1406 if (xscale->trace.buffer_enabled)
1407 {
1408 xscale_send_u32(target, 0x62);
1409 xscale_send_u32(target, 0x31);
1410 }
1411 else
1412 xscale_send_u32(target, 0x30);
1413
1414 /* send CPSR */
1415 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1416 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1417
1418 for (i = 7; i >= 0; i--)
1419 {
1420 /* send register */
1421 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1422 LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1423 }
1424
1425 /* send PC */
1426 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1427 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1428
1429 target->debug_reason = DBG_REASON_NOTHALTED;
1430
1431 if (!debug_execution)
1432 {
1433 /* registers are now invalid */
1434 armv4_5_invalidate_core_regs(target);
1435 target->state = TARGET_RUNNING;
1436 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1437 }
1438 else
1439 {
1440 target->state = TARGET_DEBUG_RUNNING;
1441 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1442 }
1443
1444 LOG_DEBUG("target resumed");
1445
1446 xscale->handler_running = 1;
1447
1448 return ERROR_OK;
1449 }
1450
1451 int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1452 {
1453 armv4_5_common_t *armv4_5 = target->arch_info;
1454 xscale_common_t *xscale = armv4_5->arch_info;
1455 breakpoint_t *breakpoint = target->breakpoints;
1456
1457 u32 current_pc, next_pc;
1458 int i;
1459 int retval;
1460
1461 if (target->state != TARGET_HALTED)
1462 {
1463 LOG_WARNING("target not halted");
1464 return ERROR_TARGET_NOT_HALTED;
1465 }
1466
1467 /* current = 1: continue on current pc, otherwise continue at <address> */
1468 if (!current)
1469 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1470
1471 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1472
1473 /* if we're at the reset vector, we have to simulate the step */
1474 if (current_pc == 0x0)
1475 {
1476 arm_simulate_step(target, NULL);
1477 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1478
1479 target->debug_reason = DBG_REASON_SINGLESTEP;
1480 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1481
1482 return ERROR_OK;
1483 }
1484
1485 /* the front-end may request us not to handle breakpoints */
1486 if (handle_breakpoints)
1487 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1488 {
1489 xscale_unset_breakpoint(target, breakpoint);
1490 }
1491
1492 target->debug_reason = DBG_REASON_SINGLESTEP;
1493
1494 /* calculate PC of next instruction */
1495 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1496 {
1497 u32 current_opcode;
1498 target_read_u32(target, current_pc, &current_opcode);
1499 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
1500 }
1501
1502 LOG_DEBUG("enable single-step");
1503 xscale_enable_single_step(target, next_pc);
1504
1505 /* restore banked registers */
1506 xscale_restore_context(target);
1507
1508 /* send resume request (command 0x30 or 0x31)
1509 * clean the trace buffer if it is to be enabled (0x62) */
1510 if (xscale->trace.buffer_enabled)
1511 {
1512 xscale_send_u32(target, 0x62);
1513 xscale_send_u32(target, 0x31);
1514 }
1515 else
1516 xscale_send_u32(target, 0x30);
1517
1518 /* send CPSR */
1519 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1520 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1521
1522 for (i = 7; i >= 0; i--)
1523 {
1524 /* send register */
1525 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1526 LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1527 }
1528
1529 /* send PC */
1530 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1531 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1532
1533 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1534
1535 /* registers are now invalid */
1536 armv4_5_invalidate_core_regs(target);
1537
1538 /* wait for and process debug entry */
1539 xscale_debug_entry(target);
1540
1541 LOG_DEBUG("disable single-step");
1542 xscale_disable_single_step(target);
1543
1544 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1545
1546 if (breakpoint)
1547 {
1548 xscale_set_breakpoint(target, breakpoint);
1549 }
1550
1551 LOG_DEBUG("target stepped");
1552
1553 return ERROR_OK;
1554
1555 }
1556
1557 int xscale_assert_reset(target_t *target)
1558 {
1559 armv4_5_common_t *armv4_5 = target->arch_info;
1560 xscale_common_t *xscale = armv4_5->arch_info;
1561
1562 LOG_DEBUG("target->state: %s",
1563 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
1564
1565 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1566 * end up in T-L-R, which would reset JTAG
1567 */
1568 jtag_add_end_state(TAP_RTI);
1569 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
1570
1571 /* set Hold reset, Halt mode and Trap Reset */
1572 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1573 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1574 xscale_write_dcsr(target, 1, 0);
1575
1576 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1577 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, 0x7f);
1578 jtag_execute_queue();
1579
1580 /* assert reset */
1581 jtag_add_reset(0, 1);
1582
1583 /* sleep 1ms, to be sure we fulfill any requirements */
1584 jtag_add_sleep(1000);
1585 jtag_execute_queue();
1586
1587 target->state = TARGET_RESET;
1588
1589 if (target->reset_halt)
1590 {
1591 int retval;
1592 if ((retval = target_halt(target))!=ERROR_OK)
1593 return retval;
1594 }
1595
1596 return ERROR_OK;
1597 }
1598
1599 int xscale_deassert_reset(target_t *target)
1600 {
1601 armv4_5_common_t *armv4_5 = target->arch_info;
1602 xscale_common_t *xscale = armv4_5->arch_info;
1603
1604 fileio_t debug_handler;
1605 u32 address;
1606 u32 binary_size;
1607
1608 u32 buf_cnt;
1609 int i;
1610 int retval;
1611
1612 breakpoint_t *breakpoint = target->breakpoints;
1613
1614 LOG_DEBUG("-");
1615
1616 xscale->ibcr_available = 2;
1617 xscale->ibcr0_used = 0;
1618 xscale->ibcr1_used = 0;
1619
1620 xscale->dbr_available = 2;
1621 xscale->dbr0_used = 0;
1622 xscale->dbr1_used = 0;
1623
1624 /* mark all hardware breakpoints as unset */
1625 while (breakpoint)
1626 {
1627 if (breakpoint->type == BKPT_HARD)
1628 {
1629 breakpoint->set = 0;
1630 }
1631 breakpoint = breakpoint->next;
1632 }
1633
1634 if (!xscale->handler_installed)
1635 {
1636 /* release SRST */
1637 jtag_add_reset(0, 0);
1638
1639 /* wait 300ms; 150 and 100ms were not enough */
1640 jtag_add_sleep(300*1000);
1641
1642 jtag_add_runtest(2030, TAP_RTI);
1643 jtag_execute_queue();
1644
1645 /* set Hold reset, Halt mode and Trap Reset */
1646 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1647 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1648 xscale_write_dcsr(target, 1, 0);
1649
1650 /* Load debug handler */
1651 if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1652 {
1653 return ERROR_OK;
1654 }
1655
1656 if ((binary_size = debug_handler.size) % 4)
1657 {
1658 LOG_ERROR("debug_handler.bin: size not a multiple of 4");
1659 exit(-1);
1660 }
1661
1662 if (binary_size > 0x800)
1663 {
1664 LOG_ERROR("debug_handler.bin: larger than 2kb");
1665 exit(-1);
1666 }
1667
1668 binary_size = CEIL(binary_size, 32) * 32;
1669
1670 address = xscale->handler_address;
1671 while (binary_size > 0)
1672 {
1673 u32 cache_line[8];
1674 u8 buffer[32];
1675
1676 if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK)
1677 {
1678
1679 }
1680
1681 for (i = 0; i < buf_cnt; i += 4)
1682 {
1683 /* convert LE buffer to host-endian u32 */
1684 cache_line[i / 4] = le_to_h_u32(&buffer[i]);
1685 }
1686
1687 for (; buf_cnt < 32; buf_cnt += 4)
1688 {
1689 cache_line[buf_cnt / 4] = 0xe1a08008;
1690 }
1691
1692 /* only load addresses other than the reset vectors */
1693 if ((address % 0x400) != 0x0)
1694 {
1695 xscale_load_ic(target, 1, address, cache_line);
1696 }
1697
1698 address += buf_cnt;
1699 binary_size -= buf_cnt;
1700 };
1701
1702 xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
1703 xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
1704
1705 jtag_add_runtest(30, TAP_RTI);
1706
1707 jtag_add_sleep(100000);
1708
1709 /* set Hold reset, Halt mode and Trap Reset */
1710 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1711 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1712 xscale_write_dcsr(target, 1, 0);
1713
1714 /* clear Hold reset to let the target run (should enter debug handler) */
1715 xscale_write_dcsr(target, 0, 1);
1716 target->state = TARGET_RUNNING;
1717
1718 if (!target->reset_halt)
1719 {
1720 jtag_add_sleep(10000);
1721
1722 /* we should have entered debug now */
1723 xscale_debug_entry(target);
1724 target->state = TARGET_HALTED;
1725
1726 /* resume the target */
1727 xscale_resume(target, 1, 0x0, 1, 0);
1728 }
1729
1730 fileio_close(&debug_handler);
1731 }
1732 else
1733 {
1734 jtag_add_reset(0, 0);
1735 }
1736
1737
1738 return ERROR_OK;
1739 }
1740
1741 int xscale_soft_reset_halt(struct target_s *target)
1742 {
1743
1744 return ERROR_OK;
1745 }
1746
1747 int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1748 {
1749
1750 return ERROR_OK;
1751 }
1752
1753 int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1754 {
1755
1756 return ERROR_OK;
1757 }
1758
1759 int xscale_full_context(target_t *target)
1760 {
1761 armv4_5_common_t *armv4_5 = target->arch_info;
1762
1763 u32 *buffer;
1764
1765 int i, j;
1766
1767 LOG_DEBUG("-");
1768
1769 if (target->state != TARGET_HALTED)
1770 {
1771 LOG_WARNING("target not halted");
1772 return ERROR_TARGET_NOT_HALTED;
1773 }
1774
1775 buffer = malloc(4 * 8);
1776
1777 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1778 * we can't enter User mode on an XScale (unpredictable),
1779 * but User shares registers with SYS
1780 */
1781 for(i = 1; i < 7; i++)
1782 {
1783 int valid = 1;
1784
1785 /* check if there are invalid registers in the current mode
1786 */
1787 for (j = 0; j <= 16; j++)
1788 {
1789 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1790 valid = 0;
1791 }
1792
1793 if (!valid)
1794 {
1795 u32 tmp_cpsr;
1796
1797 /* request banked registers */
1798 xscale_send_u32(target, 0x0);
1799
1800 tmp_cpsr = 0x0;
1801 tmp_cpsr |= armv4_5_number_to_mode(i);
1802 tmp_cpsr |= 0xc0; /* I/F bits */
1803
1804 /* send CPSR for desired mode */
1805 xscale_send_u32(target, tmp_cpsr);
1806
1807 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1808 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1809 {
1810 xscale_receive(target, buffer, 8);
1811 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
1812 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1813 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1814 }
1815 else
1816 {
1817 xscale_receive(target, buffer, 7);
1818 }
1819
1820 /* move data from buffer to register cache */
1821 for (j = 8; j <= 14; j++)
1822 {
1823 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value, 0, 32, buffer[j - 8]);
1824 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1825 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1826 }
1827 }
1828 }
1829
1830 free(buffer);
1831
1832 return ERROR_OK;
1833 }
1834
1835 int xscale_restore_context(target_t *target)
1836 {
1837 armv4_5_common_t *armv4_5 = target->arch_info;
1838
1839 int i, j;
1840
1841 LOG_DEBUG("-");
1842
1843 if (target->state != TARGET_HALTED)
1844 {
1845 LOG_WARNING("target not halted");
1846 return ERROR_TARGET_NOT_HALTED;
1847 }
1848
1849 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1850 * we can't enter User mode on an XScale (unpredictable),
1851 * but User shares registers with SYS
1852 */
1853 for(i = 1; i < 7; i++)
1854 {
1855 int dirty = 0;
1856
1857 /* check if there are invalid registers in the current mode
1858 */
1859 for (j = 8; j <= 14; j++)
1860 {
1861 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty == 1)
1862 dirty = 1;
1863 }
1864
1865 /* if not USR/SYS, check if the SPSR needs to be written */
1866 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1867 {
1868 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty == 1)
1869 dirty = 1;
1870 }
1871
1872 if (dirty)
1873 {
1874 u32 tmp_cpsr;
1875
1876 /* send banked registers */
1877 xscale_send_u32(target, 0x1);
1878
1879 tmp_cpsr = 0x0;
1880 tmp_cpsr |= armv4_5_number_to_mode(i);
1881 tmp_cpsr |= 0xc0; /* I/F bits */
1882
1883 /* send CPSR for desired mode */
1884 xscale_send_u32(target, tmp_cpsr);
1885
1886 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1887 for (j = 8; j <= 14; j++)
1888 {
1889 xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, j).value, 0, 32));
1890 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1891 }
1892
1893 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1894 {
1895 xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32));
1896 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1897 }
1898 }
1899 }
1900
1901 return ERROR_OK;
1902 }
1903
1904 int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1905 {
1906 armv4_5_common_t *armv4_5 = target->arch_info;
1907 xscale_common_t *xscale = armv4_5->arch_info;
1908 u32 *buf32;
1909 int i;
1910 int retval;
1911
1912 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1913
1914 if (target->state != TARGET_HALTED)
1915 {
1916 LOG_WARNING("target not halted");
1917 return ERROR_TARGET_NOT_HALTED;
1918 }
1919
1920 /* sanitize arguments */
1921 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1922 return ERROR_INVALID_ARGUMENTS;
1923
1924 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1925 return ERROR_TARGET_UNALIGNED_ACCESS;
1926
1927 /* send memory read request (command 0x1n, n: access size) */
1928 if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK)
1929 return retval;
1930
1931 /* send base address for read request */
1932 if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
1933 return retval;
1934
1935 /* send number of requested data words */
1936 if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
1937 return retval;
1938
1939 /* receive data from target (count times 32-bit words in host endianness) */
1940 buf32 = malloc(4 * count);
1941 if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK)
1942 return retval;
1943
1944 /* extract data from host-endian buffer into byte stream */
1945 for (i = 0; i < count; i++)
1946 {
1947 switch (size)
1948 {
1949 case 4:
1950 target_buffer_set_u32(target, buffer, buf32[i]);
1951 buffer += 4;
1952 break;
1953 case 2:
1954 target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
1955 buffer += 2;
1956 break;
1957 case 1:
1958 *buffer++ = buf32[i] & 0xff;
1959 break;
1960 default:
1961 LOG_ERROR("should never get here");
1962 exit(-1);
1963 }
1964 }
1965
1966 free(buf32);
1967
1968 /* examine DCSR, to see if Sticky Abort (SA) got set */
1969 if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
1970 return retval;
1971 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1972 {
1973 /* clear SA bit */
1974 if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
1975 return retval;
1976
1977 return ERROR_TARGET_DATA_ABORT;
1978 }
1979
1980 return ERROR_OK;
1981 }
1982
1983 int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1984 {
1985 armv4_5_common_t *armv4_5 = target->arch_info;
1986 xscale_common_t *xscale = armv4_5->arch_info;
1987 int retval;
1988
1989 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1990
1991 if (target->state != TARGET_HALTED)
1992 {
1993 LOG_WARNING("target not halted");
1994 return ERROR_TARGET_NOT_HALTED;
1995 }
1996
1997 /* sanitize arguments */
1998 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1999 return ERROR_INVALID_ARGUMENTS;
2000
2001 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2002 return ERROR_TARGET_UNALIGNED_ACCESS;
2003
2004 /* send memory write request (command 0x2n, n: access size) */
2005 if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK)
2006 return retval;
2007
2008 /* send base address for read request */
2009 if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
2010 return retval;
2011
2012 /* send number of requested data words to be written*/
2013 if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
2014 return retval;
2015
2016 /* extract data from host-endian buffer into byte stream */
2017 #if 0
2018 for (i = 0; i < count; i++)
2019 {
2020 switch (size)
2021 {
2022 case 4:
2023 value = target_buffer_get_u32(target, buffer);
2024 xscale_send_u32(target, value);
2025 buffer += 4;
2026 break;
2027 case 2:
2028 value = target_buffer_get_u16(target, buffer);
2029 xscale_send_u32(target, value);
2030 buffer += 2;
2031 break;
2032 case 1:
2033 value = *buffer;
2034 xscale_send_u32(target, value);
2035 buffer += 1;
2036 break;
2037 default:
2038 LOG_ERROR("should never get here");
2039 exit(-1);
2040 }
2041 }
2042 #endif
2043 if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK)
2044 return retval;
2045
2046 /* examine DCSR, to see if Sticky Abort (SA) got set */
2047 if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
2048 return retval;
2049 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
2050 {
2051 /* clear SA bit */
2052 if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
2053 return retval;
2054
2055 return ERROR_TARGET_DATA_ABORT;
2056 }
2057
2058 return ERROR_OK;
2059 }
2060
2061 int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2062 {
2063 return xscale_write_memory(target, address, 4, count, buffer);
2064 }
2065
2066 u32 xscale_get_ttb(target_t *target)
2067 {
2068 armv4_5_common_t *armv4_5 = target->arch_info;
2069 xscale_common_t *xscale = armv4_5->arch_info;
2070 u32 ttb;
2071
2072 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
2073 ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
2074
2075 return ttb;
2076 }
2077
2078 void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
2079 {
2080 armv4_5_common_t *armv4_5 = target->arch_info;
2081 xscale_common_t *xscale = armv4_5->arch_info;
2082 u32 cp15_control;
2083
2084 /* read cp15 control register */
2085 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2086 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2087
2088 if (mmu)
2089 cp15_control &= ~0x1U;
2090
2091 if (d_u_cache)
2092 {
2093 /* clean DCache */
2094 xscale_send_u32(target, 0x50);
2095 xscale_send_u32(target, xscale->cache_clean_address);
2096
2097 /* invalidate DCache */
2098 xscale_send_u32(target, 0x51);
2099
2100 cp15_control &= ~0x4U;
2101 }
2102
2103 if (i_cache)
2104 {
2105 /* invalidate ICache */
2106 xscale_send_u32(target, 0x52);
2107 cp15_control &= ~0x1000U;
2108 }
2109
2110 /* write new cp15 control register */
2111 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2112
2113 /* execute cpwait to ensure outstanding operations complete */
2114 xscale_send_u32(target, 0x53);
2115 }
2116
2117 void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
2118 {
2119 armv4_5_common_t *armv4_5 = target->arch_info;
2120 xscale_common_t *xscale = armv4_5->arch_info;
2121 u32 cp15_control;
2122
2123 /* read cp15 control register */
2124 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2125 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2126
2127 if (mmu)
2128 cp15_control |= 0x1U;
2129
2130 if (d_u_cache)
2131 cp15_control |= 0x4U;
2132
2133 if (i_cache)
2134 cp15_control |= 0x1000U;
2135
2136 /* write new cp15 control register */
2137 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2138
2139 /* execute cpwait to ensure outstanding operations complete */
2140 xscale_send_u32(target, 0x53);
2141 }
2142
2143 int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2144 {
2145 armv4_5_common_t *armv4_5 = target->arch_info;
2146 xscale_common_t *xscale = armv4_5->arch_info;
2147
2148 if (target->state != TARGET_HALTED)
2149 {
2150 LOG_WARNING("target not halted");
2151 return ERROR_TARGET_NOT_HALTED;
2152 }
2153
2154 if (xscale->force_hw_bkpts)
2155 breakpoint->type = BKPT_HARD;
2156
2157 if (breakpoint->set)
2158 {
2159 LOG_WARNING("breakpoint already set");
2160 return ERROR_OK;
2161 }
2162
2163 if (breakpoint->type == BKPT_HARD)
2164 {
2165 u32 value = breakpoint->address | 1;
2166 if (!xscale->ibcr0_used)
2167 {
2168 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
2169 xscale->ibcr0_used = 1;
2170 breakpoint->set = 1; /* breakpoint set on first breakpoint register */
2171 }
2172 else if (!xscale->ibcr1_used)
2173 {
2174 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
2175 xscale->ibcr1_used = 1;
2176 breakpoint->set = 2; /* breakpoint set on second breakpoint register */
2177 }
2178 else
2179 {
2180 LOG_ERROR("BUG: no hardware comparator available");
2181 return ERROR_OK;
2182 }
2183 }
2184 else if (breakpoint->type == BKPT_SOFT)
2185 {
2186 if (breakpoint->length == 4)
2187 {
2188 /* keep the original instruction in target endianness */
2189 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
2190 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2191 target_write_u32(target, breakpoint->address, xscale->arm_bkpt);
2192 }
2193 else
2194 {
2195 /* keep the original instruction in target endianness */
2196 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
2197 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2198 target_write_u32(target, breakpoint->address, xscale->thumb_bkpt);
2199 }
2200 breakpoint->set = 1;
2201 }
2202
2203 return ERROR_OK;
2204
2205 }
2206
2207 int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2208 {
2209 armv4_5_common_t *armv4_5 = target->arch_info;
2210 xscale_common_t *xscale = armv4_5->arch_info;
2211
2212 if (target->state != TARGET_HALTED)
2213 {
2214 LOG_WARNING("target not halted");
2215 return ERROR_TARGET_NOT_HALTED;
2216 }
2217
2218 if (xscale->force_hw_bkpts)
2219 {
2220 LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
2221 breakpoint->type = BKPT_HARD;
2222 }
2223
2224 if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
2225 {
2226 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2227 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2228 }
2229 else
2230 {
2231 xscale->ibcr_available--;
2232 }
2233
2234 if ((breakpoint->length != 2) && (breakpoint->length != 4))
2235 {
2236 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2237 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2238 }
2239
2240 return ERROR_OK;
2241 }
2242
2243 int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2244 {
2245 armv4_5_common_t *armv4_5 = target->arch_info;
2246 xscale_common_t *xscale = armv4_5->arch_info;
2247
2248 if (target->state != TARGET_HALTED)
2249 {
2250 LOG_WARNING("target not halted");
2251 return ERROR_TARGET_NOT_HALTED;
2252 }
2253
2254 if (!breakpoint->set)
2255 {
2256 LOG_WARNING("breakpoint not set");
2257 return ERROR_OK;
2258 }
2259
2260 if (breakpoint->type == BKPT_HARD)
2261 {
2262 if (breakpoint->set == 1)
2263 {
2264 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
2265 xscale->ibcr0_used = 0;
2266 }
2267 else if (breakpoint->set == 2)
2268 {
2269 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
2270 xscale->ibcr1_used = 0;
2271 }
2272 breakpoint->set = 0;
2273 }
2274 else
2275 {
2276 /* restore original instruction (kept in target endianness) */
2277 if (breakpoint->length == 4)
2278 {
2279 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
2280 }
2281 else
2282 {
2283 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
2284 }
2285 breakpoint->set = 0;
2286 }
2287
2288 return ERROR_OK;
2289 }
2290
2291 int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2292 {
2293 armv4_5_common_t *armv4_5 = target->arch_info;
2294 xscale_common_t *xscale = armv4_5->arch_info;
2295
2296 if (target->state != TARGET_HALTED)
2297 {
2298 LOG_WARNING("target not halted");
2299 return ERROR_TARGET_NOT_HALTED;
2300 }
2301
2302 if (breakpoint->set)
2303 {
2304 xscale_unset_breakpoint(target, breakpoint);
2305 }
2306
2307 if (breakpoint->type == BKPT_HARD)
2308 xscale->ibcr_available++;
2309
2310 return ERROR_OK;
2311 }
2312
2313 int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2314 {
2315 armv4_5_common_t *armv4_5 = target->arch_info;
2316 xscale_common_t *xscale = armv4_5->arch_info;
2317 u8 enable=0;
2318 reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2319 u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2320
2321 if (target->state != TARGET_HALTED)
2322 {
2323 LOG_WARNING("target not halted");
2324 return ERROR_TARGET_NOT_HALTED;
2325 }
2326
2327 xscale_get_reg(dbcon);
2328
2329 switch (watchpoint->rw)
2330 {
2331 case WPT_READ:
2332 enable = 0x3;
2333 break;
2334 case WPT_ACCESS:
2335 enable = 0x2;
2336 break;
2337 case WPT_WRITE:
2338 enable = 0x1;
2339 break;
2340 default:
2341 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2342 }
2343
2344 if (!xscale->dbr0_used)
2345 {
2346 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
2347 dbcon_value |= enable;
2348 xscale_set_reg_u32(dbcon, dbcon_value);
2349 watchpoint->set = 1;
2350 xscale->dbr0_used = 1;
2351 }
2352 else if (!xscale->dbr1_used)
2353 {
2354 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
2355 dbcon_value |= enable << 2;
2356 xscale_set_reg_u32(dbcon, dbcon_value);
2357 watchpoint->set = 2;
2358 xscale->dbr1_used = 1;
2359 }
2360 else
2361 {
2362 LOG_ERROR("BUG: no hardware comparator available");
2363 return ERROR_OK;
2364 }
2365
2366 return ERROR_OK;
2367 }
2368
2369 int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2370 {
2371 armv4_5_common_t *armv4_5 = target->arch_info;
2372 xscale_common_t *xscale = armv4_5->arch_info;
2373
2374 if (target->state != TARGET_HALTED)
2375 {
2376 LOG_WARNING("target not halted");
2377 return ERROR_TARGET_NOT_HALTED;
2378 }
2379
2380 if (xscale->dbr_available < 1)
2381 {
2382 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2383 }
2384
2385 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
2386 {
2387 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2388 }
2389
2390 xscale->dbr_available--;
2391
2392 return ERROR_OK;
2393 }
2394
2395 int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2396 {
2397 armv4_5_common_t *armv4_5 = target->arch_info;
2398 xscale_common_t *xscale = armv4_5->arch_info;
2399 reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2400 u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2401
2402 if (target->state != TARGET_HALTED)
2403 {
2404 LOG_WARNING("target not halted");
2405 return ERROR_TARGET_NOT_HALTED;
2406 }
2407
2408 if (!watchpoint->set)
2409 {
2410 LOG_WARNING("breakpoint not set");
2411 return ERROR_OK;
2412 }
2413
2414 if (watchpoint->set == 1)
2415 {
2416 dbcon_value &= ~0x3;
2417 xscale_set_reg_u32(dbcon, dbcon_value);
2418 xscale->dbr0_used = 0;
2419 }
2420 else if (watchpoint->set == 2)
2421 {
2422 dbcon_value &= ~0xc;
2423 xscale_set_reg_u32(dbcon, dbcon_value);
2424 xscale->dbr1_used = 0;
2425 }
2426 watchpoint->set = 0;
2427
2428 return ERROR_OK;
2429 }
2430
2431 int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2432 {
2433 armv4_5_common_t *armv4_5 = target->arch_info;
2434 xscale_common_t *xscale = armv4_5->arch_info;
2435
2436 if (target->state != TARGET_HALTED)
2437 {
2438 LOG_WARNING("target not halted");
2439 return ERROR_TARGET_NOT_HALTED;
2440 }
2441
2442 if (watchpoint->set)
2443 {
2444 xscale_unset_watchpoint(target, watchpoint);
2445 }
2446
2447 xscale->dbr_available++;
2448
2449 return ERROR_OK;
2450 }
2451
2452 void xscale_enable_watchpoints(struct target_s *target)
2453 {
2454 watchpoint_t *watchpoint = target->watchpoints;
2455
2456 while (watchpoint)
2457 {
2458 if (watchpoint->set == 0)
2459 xscale_set_watchpoint(target, watchpoint);
2460 watchpoint = watchpoint->next;
2461 }
2462 }
2463
2464 void xscale_enable_breakpoints(struct target_s *target)
2465 {
2466 breakpoint_t *breakpoint = target->breakpoints;
2467
2468 /* set any pending breakpoints */
2469 while (breakpoint)
2470 {
2471 if (breakpoint->set == 0)
2472 xscale_set_breakpoint(target, breakpoint);
2473 breakpoint = breakpoint->next;
2474 }
2475 }
2476
2477 int xscale_get_reg(reg_t *reg)
2478 {
2479 xscale_reg_t *arch_info = reg->arch_info;
2480 target_t *target = arch_info->target;
2481 armv4_5_common_t *armv4_5 = target->arch_info;
2482 xscale_common_t *xscale = armv4_5->arch_info;
2483
2484 /* DCSR, TX and RX are accessible via JTAG */
2485 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2486 {
2487 return xscale_read_dcsr(arch_info->target);
2488 }
2489 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2490 {
2491 /* 1 = consume register content */
2492 return xscale_read_tx(arch_info->target, 1);
2493 }
2494 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2495 {
2496 /* can't read from RX register (host -> debug handler) */
2497 return ERROR_OK;
2498 }
2499 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2500 {
2501 /* can't (explicitly) read from TXRXCTRL register */
2502 return ERROR_OK;
2503 }
2504 else /* Other DBG registers have to be transfered by the debug handler */
2505 {
2506 /* send CP read request (command 0x40) */
2507 xscale_send_u32(target, 0x40);
2508
2509 /* send CP register number */
2510 xscale_send_u32(target, arch_info->dbg_handler_number);
2511
2512 /* read register value */
2513 xscale_read_tx(target, 1);
2514 buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
2515
2516 reg->dirty = 0;
2517 reg->valid = 1;
2518 }
2519
2520 return ERROR_OK;
2521 }
2522
2523 int xscale_set_reg(reg_t *reg, u8* buf)
2524 {
2525 xscale_reg_t *arch_info = reg->arch_info;
2526 target_t *target = arch_info->target;
2527 armv4_5_common_t *armv4_5 = target->arch_info;
2528 xscale_common_t *xscale = armv4_5->arch_info;
2529 u32 value = buf_get_u32(buf, 0, 32);
2530
2531 /* DCSR, TX and RX are accessible via JTAG */
2532 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2533 {
2534 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
2535 return xscale_write_dcsr(arch_info->target, -1, -1);
2536 }
2537 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2538 {
2539 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
2540 return xscale_write_rx(arch_info->target);
2541 }
2542 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2543 {
2544 /* can't write to TX register (debug-handler -> host) */
2545 return ERROR_OK;
2546 }
2547 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2548 {
2549 /* can't (explicitly) write to TXRXCTRL register */
2550 return ERROR_OK;
2551 }
2552 else /* Other DBG registers have to be transfered by the debug handler */
2553 {
2554 /* send CP write request (command 0x41) */
2555 xscale_send_u32(target, 0x41);
2556
2557 /* send CP register number */
2558 xscale_send_u32(target, arch_info->dbg_handler_number);
2559
2560 /* send CP register value */
2561 xscale_send_u32(target, value);
2562 buf_set_u32(reg->value, 0, 32, value);
2563 }
2564
2565 return ERROR_OK;
2566 }
2567
2568 /* convenience wrapper to access XScale specific registers */
2569 int xscale_set_reg_u32(reg_t *reg, u32 value)
2570 {
2571 u8 buf[4];
2572
2573 buf_set_u32(buf, 0, 32, value);
2574
2575 return xscale_set_reg(reg, buf);
2576 }
2577
2578 int xscale_write_dcsr_sw(target_t *target, u32 value)
2579 {
2580 /* get pointers to arch-specific information */
2581 armv4_5_common_t *armv4_5 = target->arch_info;
2582 xscale_common_t *xscale = armv4_5->arch_info;
2583 reg_t *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
2584 xscale_reg_t *dcsr_arch_info = dcsr->arch_info;
2585
2586 /* send CP write request (command 0x41) */
2587 xscale_send_u32(target, 0x41);
2588
2589 /* send CP register number */
2590 xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
2591
2592 /* send CP register value */
2593 xscale_send_u32(target, value);
2594 buf_set_u32(dcsr->value, 0, 32, value);
2595
2596 return ERROR_OK;
2597 }
2598
2599 int xscale_read_trace(target_t *target)
2600 {
2601 /* get pointers to arch-specific information */
2602 armv4_5_common_t *armv4_5 = target->arch_info;
2603 xscale_common_t *xscale = armv4_5->arch_info;
2604 xscale_trace_data_t **trace_data_p;
2605
2606 /* 258 words from debug handler
2607 * 256 trace buffer entries
2608 * 2 checkpoint addresses
2609 */
2610 u32 trace_buffer[258];
2611 int is_address[256];
2612 int i, j;
2613
2614 if (target->state != TARGET_HALTED)
2615 {
2616 LOG_WARNING("target must be stopped to read trace data");
2617 return ERROR_TARGET_NOT_HALTED;
2618 }
2619
2620 /* send read trace buffer command (command 0x61) */
2621 xscale_send_u32(target, 0x61);
2622
2623 /* receive trace buffer content */
2624 xscale_receive(target, trace_buffer, 258);
2625
2626 /* parse buffer backwards to identify address entries */
2627 for (i = 255; i >= 0; i--)
2628 {
2629 is_address[i] = 0;
2630 if (((trace_buffer[i] & 0xf0) == 0x90) ||
2631 ((trace_buffer[i] & 0xf0) == 0xd0))
2632 {
2633 if (i >= 3)
2634 is_address[--i] = 1;
2635 if (i >= 2)
2636 is_address[--i] = 1;
2637 if (i >= 1)
2638 is_address[--i] = 1;
2639 if (i >= 0)
2640 is_address[--i] = 1;
2641 }
2642 }
2643
2644
2645 /* search first non-zero entry */
2646 for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
2647 ;
2648
2649 if (j == 256)
2650 {
2651 LOG_DEBUG("no trace data collected");
2652 return ERROR_XSCALE_NO_TRACE_DATA;
2653 }
2654
2655 for (trace_data_p = &xscale->trace.data; *trace_data_p; trace_data_p = &(*trace_data_p)->next)
2656 ;
2657
2658 *trace_data_p = malloc(sizeof(xscale_trace_data_t));
2659 (*trace_data_p)->next = NULL;
2660 (*trace_data_p)->chkpt0 = trace_buffer[256];
2661 (*trace_data_p)->chkpt1 = trace_buffer[257];
2662 (*trace_data_p)->last_instruction = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2663 (*trace_data_p)->entries = malloc(sizeof(xscale_trace_entry_t) * (256 - j));
2664 (*trace_data_p)->depth = 256 - j;
2665
2666 for (i = j; i < 256; i++)
2667 {
2668 (*trace_data_p)->entries[i - j].data = trace_buffer[i];
2669 if (is_address[i])
2670 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
2671 else
2672 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
2673 }
2674
2675 return ERROR_OK;
2676 }
2677
2678 int xscale_read_instruction(target_t *target, arm_instruction_t *instruction)
2679 {
2680 /* get pointers to arch-specific information */
2681 armv4_5_common_t *armv4_5 = target->arch_info;
2682 xscale_common_t *xscale = armv4_5->arch_info;
2683 int i;
2684 int section = -1;
2685 u32 size_read;
2686 u32 opcode;
2687 int retval;
2688
2689 if (!xscale->trace.image)
2690 return ERROR_TRACE_IMAGE_UNAVAILABLE;
2691
2692 /* search for the section the current instruction belongs to */
2693 for (i = 0; i < xscale->trace.image->num_sections; i++)
2694 {
2695 if ((xscale->trace.image->sections[i].base_address <= xscale->trace.current_pc) &&
2696 (xscale->trace.image->sections[i].base_address + xscale->trace.image->sections[i].size > xscale->trace.current_pc))
2697 {
2698 section = i;
2699 break;
2700 }
2701 }
2702
2703 if (section == -1)
2704 {
2705 /* current instruction couldn't be found in the image */
2706 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2707 }
2708
2709 if (xscale->trace.core_state == ARMV4_5_STATE_ARM)
2710 {
2711 u8 buf[4];
2712 if ((retval = image_read_section(xscale->trace.image, section,
2713 xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
2714 4, buf, &size_read)) != ERROR_OK)
2715 {
2716 LOG_ERROR("error while reading instruction: %i", retval);
2717 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2718 }
2719 opcode = target_buffer_get_u32(target, buf);
2720 arm_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
2721 }
2722 else if (xscale->trace.core_state == ARMV4_5_STATE_THUMB)
2723 {
2724 u8 buf[2];
2725 if ((retval = image_read_section(xscale->trace.image, section,
2726 xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
2727 2, buf, &size_read)) != ERROR_OK)
2728 {
2729 LOG_ERROR("error while reading instruction: %i", retval);
2730 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2731 }
2732 opcode = target_buffer_get_u16(target, buf);
2733 thumb_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
2734 }
2735 else
2736 {
2737 LOG_ERROR("BUG: unknown core state encountered");
2738 exit(-1);
2739 }
2740
2741 return ERROR_OK;
2742 }
2743
2744 int xscale_branch_address(xscale_trace_data_t *trace_data, int i, u32 *target)
2745 {
2746 /* if there are less than four entries prior to the indirect branch message
2747 * we can't extract the address */
2748 if (i < 4)
2749 {
2750 return -1;
2751 }
2752
2753 *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
2754 (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
2755
2756 return 0;
2757 }
2758
2759 int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
2760 {
2761 /* get pointers to arch-specific information */
2762 armv4_5_common_t *armv4_5 = target->arch_info;
2763 xscale_common_t *xscale = armv4_5->arch_info;
2764 int next_pc_ok = 0;
2765 u32 next_pc = 0x0;
2766 xscale_trace_data_t *trace_data = xscale->trace.data;
2767 int retval;
2768
2769 while (trace_data)
2770 {
2771 int i, chkpt;
2772 int rollover;
2773 int branch;
2774 int exception;
2775 xscale->trace.core_state = ARMV4_5_STATE_ARM;
2776
2777 chkpt = 0;
2778 rollover = 0;
2779
2780 for (i = 0; i < trace_data->depth; i++)
2781 {
2782 next_pc_ok = 0;
2783 branch = 0;
2784 exception = 0;
2785
2786 if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
2787 continue;
2788
2789 switch ((trace_data->entries[i].data & 0xf0) >> 4)
2790 {
2791 case 0: /* Exceptions */
2792 case 1:
2793 case 2:
2794 case 3:
2795 case 4:
2796 case 5:
2797 case 6:
2798 case 7:
2799 exception = (trace_data->entries[i].data & 0x70) >> 4;
2800 next_pc_ok = 1;
2801 next_pc = (trace_data->entries[i].data & 0xf0) >> 2;
2802 command_print(cmd_ctx, "--- exception %i ---", (trace_data->entries[i].data & 0xf0) >> 4);
2803 break;
2804 case 8: /* Direct Branch */
2805 branch = 1;
2806 break;
2807 case 9: /* Indirect Branch */
2808 branch = 1;
2809 if (xscale_branch_address(trace_data, i, &next_pc) == 0)
2810 {
2811 next_pc_ok = 1;
2812 }
2813 break;
2814 case 13: /* Checkpointed Indirect Branch */
2815 if (xscale_branch_address(trace_data, i, &next_pc) == 0)
2816 {
2817 next_pc_ok = 1;
2818 if (((chkpt == 0) && (next_pc != trace_data->chkpt0))
2819 || ((chkpt == 1) && (next_pc != trace_data->chkpt1)))
2820 LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2821 }
2822 /* explicit fall-through */
2823 case 12: /* Checkpointed Direct Branch */
2824 branch = 1;
2825 if (chkpt == 0)
2826 {
2827 next_pc_ok = 1;
2828 next_pc = trace_data->chkpt0;
2829 chkpt++;
2830 }
2831 else if (chkpt == 1)
2832 {
2833 next_pc_ok = 1;
2834 next_pc = trace_data->chkpt0;
2835 chkpt++;
2836 }
2837 else
2838 {
2839 LOG_WARNING("more than two checkpointed branches encountered");
2840 }
2841 break;
2842 case 15: /* Roll-over */
2843 rollover++;
2844 continue;
2845 default: /* Reserved */
2846 command_print(cmd_ctx, "--- reserved trace message ---");
2847 LOG_ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4);
2848 return ERROR_OK;
2849 }
2850
2851 if (xscale->trace.pc_ok)
2852 {
2853 int executed = (trace_data->entries[i].data & 0xf) + rollover * 16;
2854 arm_instruction_t instruction;
2855
2856 if ((exception == 6) || (exception == 7))
2857 {
2858 /* IRQ or FIQ exception, no instruction executed */
2859 executed -= 1;
2860 }
2861
2862 while (executed-- >= 0)
2863 {
2864 if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
2865 {
2866 /* can't continue tracing with no image available */
2867 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
2868 {
2869 return retval;
2870 }
2871 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
2872 {
2873 /* TODO: handle incomplete images */
2874 }
2875 }
2876
2877 /* a precise abort on a load to the PC is included in the incremental
2878 * word count, other instructions causing data aborts are not included
2879 */
2880 if ((executed == 0) && (exception == 4)
2881 && ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDM)))
2882 {
2883 if ((instruction.type == ARM_LDM)
2884 && ((instruction.info.load_store_multiple.register_list & 0x8000) == 0))
2885 {
2886 executed--;
2887 }
2888 else if (((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
2889 && (instruction.info.load_store.Rd != 15))
2890 {
2891 executed--;
2892 }
2893 }
2894
2895 /* only the last instruction executed
2896 * (the one that caused the control flow change)
2897 * could be a taken branch
2898 */
2899 if (((executed == -1) && (branch == 1)) &&
2900 (((instruction.type == ARM_B) ||
2901 (instruction.type == ARM_BL) ||
2902 (instruction.type == ARM_BLX)) &&
2903 (instruction.info.b_bl_bx_blx.target_address != -1)))
2904 {
2905 xscale->trace.current_pc = instruction.info.b_bl_bx_blx.target_address;
2906 }
2907 else
2908 {
2909 xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
2910 }
2911 command_print(cmd_ctx, "%s", instruction.text);
2912 }
2913
2914 rollover = 0;
2915 }
2916
2917 if (next_pc_ok)
2918 {
2919 xscale->trace.current_pc = next_pc;
2920 xscale->trace.pc_ok = 1;
2921 }
2922 }
2923
2924 for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2)
2925 {
2926 arm_instruction_t instruction;
2927 if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
2928 {
2929 /* can't continue tracing with no image available */
2930 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
2931 {
2932 return retval;
2933 }
2934 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
2935 {
2936 /* TODO: handle incomplete images */
2937 }
2938 }
2939 command_print(cmd_ctx, "%s", instruction.text);
2940 }
2941
2942 trace_data = trace_data->next;
2943 }
2944
2945 return ERROR_OK;
2946 }
2947
2948 void xscale_build_reg_cache(target_t *target)
2949 {
2950 /* get pointers to arch-specific information */
2951 armv4_5_common_t *armv4_5 = target->arch_info;
2952 xscale_common_t *xscale = armv4_5->arch_info;
2953
2954 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
2955 xscale_reg_t *arch_info = malloc(sizeof(xscale_reg_arch_info));
2956 int i;
2957 int num_regs = sizeof(xscale_reg_arch_info) / sizeof(xscale_reg_t);
2958
2959 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
2960 armv4_5->core_cache = (*cache_p);
2961
2962 /* register a register arch-type for XScale dbg registers only once */
2963 if (xscale_reg_arch_type == -1)
2964 xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg);
2965
2966 (*cache_p)->next = malloc(sizeof(reg_cache_t));
2967 cache_p = &(*cache_p)->next;
2968
2969 /* fill in values for the xscale reg cache */
2970 (*cache_p)->name = "XScale registers";
2971 (*cache_p)->next = NULL;
2972 (*cache_p)->reg_list = malloc(num_regs * sizeof(reg_t));
2973 (*cache_p)->num_regs = num_regs;
2974
2975 for (i = 0; i < num_regs; i++)
2976 {
2977 (*cache_p)->reg_list[i].name = xscale_reg_list[i];
2978 (*cache_p)->reg_list[i].value = calloc(4, 1);
2979 (*cache_p)->reg_list[i].dirty = 0;
2980 (*cache_p)->reg_list[i].valid = 0;
2981 (*cache_p)->reg_list[i].size = 32;
2982 (*cache_p)->reg_list[i].bitfield_desc = NULL;
2983 (*cache_p)->reg_list[i].num_bitfields = 0;
2984 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
2985 (*cache_p)->reg_list[i].arch_type = xscale_reg_arch_type;
2986 arch_info[i] = xscale_reg_arch_info[i];
2987 arch_info[i].target = target;
2988 }
2989
2990 xscale->reg_cache = (*cache_p);
2991 }
2992
2993 int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
2994 {
2995 return ERROR_OK;
2996 }
2997
2998 int xscale_quit(void)
2999 {
3000
3001 return ERROR_OK;
3002 }
3003
3004 int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_pos, const char *variant)
3005 {
3006 armv4_5_common_t *armv4_5;
3007 u32 high_reset_branch, low_reset_branch;
3008 int i;
3009
3010 armv4_5 = &xscale->armv4_5_common;
3011
3012 /* store architecture specfic data (none so far) */
3013 xscale->arch_info = NULL;
3014 xscale->common_magic = XSCALE_COMMON_MAGIC;
3015
3016 /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
3017 xscale->variant = strdup(variant);
3018
3019 /* prepare JTAG information for the new target */
3020 xscale->jtag_info.chain_pos = chain_pos;
3021
3022 xscale->jtag_info.dbgrx = 0x02;
3023 xscale->jtag_info.dbgtx = 0x10;
3024 xscale->jtag_info.dcsr = 0x09;
3025 xscale->jtag_info.ldic = 0x07;
3026
3027 if ((strcmp(xscale->variant, "pxa250") == 0) ||
3028 (strcmp(xscale->variant, "pxa255") == 0) ||
3029 (strcmp(xscale->variant, "pxa26x") == 0))
3030 {
3031 xscale->jtag_info.ir_length = 5;
3032 }
3033 else if ((strcmp(xscale->variant, "pxa27x") == 0) ||
3034 (strcmp(xscale->variant, "ixp42x") == 0) ||
3035 (strcmp(xscale->variant, "ixp45x") == 0) ||
3036 (strcmp(xscale->variant, "ixp46x") == 0))
3037 {
3038 xscale->jtag_info.ir_length = 7;
3039 }
3040
3041 /* the debug handler isn't installed (and thus not running) at this time */
3042 xscale->handler_installed = 0;
3043 xscale->handler_running = 0;
3044 xscale->handler_address = 0xfe000800;
3045
3046 /* clear the vectors we keep locally for reference */
3047 memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
3048 memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
3049
3050 /* no user-specified vectors have been configured yet */
3051 xscale->static_low_vectors_set = 0x0;
3052 xscale->static_high_vectors_set = 0x0;
3053
3054 /* calculate branches to debug handler */
3055 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
3056 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
3057
3058 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
3059 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
3060
3061 for (i = 1; i <= 7; i++)
3062 {
3063 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3064 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3065 }
3066
3067 /* 64kB aligned region used for DCache cleaning */
3068 xscale->cache_clean_address = 0xfffe0000;
3069
3070 xscale->hold_rst = 0;
3071 xscale->external_debug_break = 0;
3072
3073 xscale->force_hw_bkpts = 1;
3074
3075 xscale->ibcr_available = 2;
3076 xscale->ibcr0_used = 0;
3077 xscale->ibcr1_used = 0;
3078
3079 xscale->dbr_available = 2;
3080 xscale->dbr0_used = 0;
3081 xscale->dbr1_used = 0;
3082
3083 xscale->arm_bkpt = ARMV5_BKPT(0x0);
3084 xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
3085
3086 xscale->vector_catch = 0x1;
3087
3088 xscale->trace.capture_status = TRACE_IDLE;
3089 xscale->trace.data = NULL;
3090 xscale->trace.image = NULL;
3091 xscale->trace.buffer_enabled = 0;
3092 xscale->trace.buffer_fill = 0;
3093
3094 /* prepare ARMv4/5 specific information */
3095 armv4_5->arch_info = xscale;
3096 armv4_5->read_core_reg = xscale_read_core_reg;
3097 armv4_5->write_core_reg = xscale_write_core_reg;
3098 armv4_5->full_context = xscale_full_context;
3099
3100 armv4_5_init_arch_info(target, armv4_5);
3101
3102 xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
3103 xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
3104 xscale->armv4_5_mmu.read_memory = xscale_read_memory;
3105 xscale->armv4_5_mmu.write_memory = xscale_write_memory;
3106 xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
3107 xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
3108 xscale->armv4_5_mmu.has_tiny_pages = 1;
3109 xscale->armv4_5_mmu.mmu_enabled = 0;
3110
3111 return ERROR_OK;
3112 }
3113
3114 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
3115 int xscale_target_create(struct target_s *target, Jim_Interp *interp)
3116 {
3117 xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t));
3118
3119 xscale_init_arch_info(target, xscale, target->chain_position, target->variant);
3120 xscale_build_reg_cache(target);
3121
3122 return ERROR_OK;
3123 }
3124
3125 int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3126 {
3127 target_t *target = NULL;
3128 armv4_5_common_t *armv4_5;
3129 xscale_common_t *xscale;
3130
3131 u32 handler_address;
3132
3133 if (argc < 2)
3134 {
3135 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3136 return ERROR_OK;
3137 }
3138
3139 if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
3140 {
3141 LOG_ERROR("no target '%s' configured", args[0]);
3142 return ERROR_OK;
3143 }
3144
3145 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3146 {
3147 return ERROR_OK;
3148 }
3149
3150 handler_address = strtoul(args[1], NULL, 0);
3151
3152 if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
3153 ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
3154 {
3155 xscale->handler_address = handler_address;
3156 }
3157 else
3158 {
3159 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3160 }
3161
3162 return ERROR_OK;
3163 }
3164
3165 int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3166 {
3167 target_t *target = NULL;
3168 armv4_5_common_t *armv4_5;
3169 xscale_common_t *xscale;
3170
3171 u32 cache_clean_address;
3172
3173 if (argc < 2)
3174 {
3175 LOG_ERROR("'xscale cache_clean_address <target#> <address>' command takes two required operands");
3176 return ERROR_OK;
3177 }
3178
3179 if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
3180 {
3181 LOG_ERROR("no target '%s' configured", args[0]);
3182 return ERROR_OK;
3183 }
3184
3185 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3186 {
3187 return ERROR_OK;
3188 }
3189
3190 cache_clean_address = strtoul(args[1], NULL, 0);
3191
3192 if (cache_clean_address & 0xffff)
3193 {
3194 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3195 }
3196 else
3197 {
3198 xscale->cache_clean_address = cache_clean_address;
3199 }
3200
3201 return ERROR_OK;
3202 }
3203
3204 int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3205 {
3206 target_t *target = get_current_target(cmd_ctx);
3207 armv4_5_common_t *armv4_5;
3208 xscale_common_t *xscale;
3209
3210 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3211 {
3212 return ERROR_OK;
3213 }
3214
3215 return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache);
3216 }
3217
3218 static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
3219 {
3220 armv4_5_common_t *armv4_5;
3221 xscale_common_t *xscale;
3222 int retval;
3223 int type;
3224 u32 cb;
3225 int domain;
3226 u32 ap;
3227
3228
3229 if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK)
3230 {
3231 return retval;
3232 }
3233 u32 ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
3234 if (type == -1)
3235 {
3236 return ret;
3237 }
3238 *physical = ret;
3239 return ERROR_OK;
3240 }
3241
3242 static int xscale_mmu(struct target_s *target, int *enabled)
3243 {
3244 armv4_5_common_t *armv4_5 = target->arch_info;
3245 xscale_common_t *xscale = armv4_5->arch_info;
3246
3247 if (target->state != TARGET_HALTED)
3248 {
3249 LOG_ERROR("Target not halted");
3250 return ERROR_TARGET_INVALID;
3251 }
3252 *enabled = xscale->armv4_5_mmu.mmu_enabled;
3253 return ERROR_OK;
3254 }
3255
3256
3257 int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3258 {
3259 target_t *target = get_current_target(cmd_ctx);
3260 armv4_5_common_t *armv4_5;
3261 xscale_common_t *xscale;
3262
3263 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3264 {
3265 return ERROR_OK;
3266 }
3267
3268 if (target->state != TARGET_HALTED)
3269 {
3270 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3271 return ERROR_OK;
3272 }
3273
3274 if (argc >= 1)
3275 {
3276 if (strcmp("enable", args[0]) == 0)
3277 {
3278 xscale_enable_mmu_caches(target, 1, 0, 0);
3279 xscale->armv4_5_mmu.mmu_enabled = 1;
3280 }
3281 else if (strcmp("disable", args[0]) == 0)
3282 {
3283 xscale_disable_mmu_caches(target, 1, 0, 0);
3284 xscale->armv4_5_mmu.mmu_enabled = 0;
3285 }
3286 }
3287
3288 command_print(cmd_ctx, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
3289
3290 return ERROR_OK;
3291 }
3292
3293 int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3294 {
3295 target_t *target = get_current_target(cmd_ctx);
3296 armv4_5_common_t *armv4_5;
3297 xscale_common_t *xscale;
3298 int icache = 0, dcache = 0;
3299
3300 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3301 {
3302 return ERROR_OK;
3303 }
3304
3305 if (target->state != TARGET_HALTED)
3306 {
3307 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3308 return ERROR_OK;
3309 }
3310
3311 if (strcmp(cmd, "icache") == 0)
3312 icache = 1;
3313 else if (strcmp(cmd, "dcache") == 0)
3314 dcache = 1;
3315
3316 if (argc >= 1)
3317 {
3318 if (strcmp("enable", args[0]) == 0)
3319 {
3320 xscale_enable_mmu_caches(target, 0, dcache, icache);
3321
3322 if (icache)
3323 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1;
3324 else if (dcache)
3325 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
3326 }
3327 else if (strcmp("disable", args[0]) == 0)
3328 {
3329 xscale_disable_mmu_caches(target, 0, dcache, icache);
3330
3331 if (icache)
3332 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
3333 else if (dcache)
3334 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
3335 }
3336 }
3337
3338 if (icache)
3339 command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
3340
3341 if (dcache)
3342 command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
3343
3344 return ERROR_OK;
3345 }
3346
3347 int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3348 {
3349 target_t *target = get_current_target(cmd_ctx);
3350 armv4_5_common_t *armv4_5;
3351 xscale_common_t *xscale;
3352
3353 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3354 {
3355 return ERROR_OK;
3356 }
3357
3358 if (argc < 1)
3359 {
3360 command_print(cmd_ctx, "usage: xscale vector_catch [mask]");
3361 }
3362 else
3363 {
3364 xscale->vector_catch = strtoul(args[0], NULL, 0);
3365 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch);
3366 xscale_write_dcsr(target, -1, -1);
3367 }
3368
3369 command_print(cmd_ctx, "vector catch mask: 0x%2.2x", xscale->vector_catch);
3370
3371 return ERROR_OK;
3372 }
3373
3374 int xscale_handle_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3375 {
3376 target_t *target = get_current_target(cmd_ctx);
3377 armv4_5_common_t *armv4_5;
3378 xscale_common_t *xscale;
3379
3380 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3381 {
3382 return ERROR_OK;
3383 }
3384
3385 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
3386 {
3387 xscale->force_hw_bkpts = 1;
3388 }
3389 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
3390 {
3391 xscale->force_hw_bkpts = 0;
3392 }
3393 else
3394 {
3395 command_print(cmd_ctx, "usage: xscale force_hw_bkpts <enable|disable>");
3396 }
3397
3398 command_print(cmd_ctx, "force hardware breakpoints %s", (xscale->force_hw_bkpts) ? "enabled" : "disabled");
3399
3400 return ERROR_OK;
3401 }
3402
3403 int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3404 {
3405 target_t *target = get_current_target(cmd_ctx);
3406 armv4_5_common_t *armv4_5;
3407 xscale_common_t *xscale;
3408 u32 dcsr_value;
3409
3410 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3411 {
3412 return ERROR_OK;
3413 }
3414
3415 if (target->state != TARGET_HALTED)
3416 {
3417 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3418 return ERROR_OK;
3419 }
3420
3421 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
3422 {
3423 xscale_trace_data_t *td, *next_td;
3424 xscale->trace.buffer_enabled = 1;
3425
3426 /* free old trace data */
3427 td = xscale->trace.data;
3428 while (td)
3429 {
3430 next_td = td->next;
3431
3432 if (td->entries)
3433 free(td->entries);
3434 free(td);
3435 td = next_td;
3436 }
3437 xscale->trace.data = NULL;
3438 }
3439 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
3440 {
3441 xscale->trace.buffer_enabled = 0;
3442 }
3443
3444 if ((argc >= 2) && (strcmp("fill", args[1]) == 0))
3445 {
3446 if (argc >= 3)
3447 xscale->trace.buffer_fill = strtoul(args[2], NULL, 0);
3448 else
3449 xscale->trace.buffer_fill = 1;
3450 }
3451 else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0))
3452 {
3453 xscale->trace.buffer_fill = -1;
3454 }
3455
3456 if (xscale->trace.buffer_enabled)
3457 {
3458 /* if we enable the trace buffer in fill-once
3459 * mode we know the address of the first instruction */
3460 xscale->trace.pc_ok = 1;
3461 xscale->trace.current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
3462 }
3463 else
3464 {
3465 /* otherwise the address is unknown, and we have no known good PC */
3466 xscale->trace.pc_ok = 0;
3467 }
3468
3469 command_print(cmd_ctx, "trace buffer %s (%s)",
3470 (xscale->trace.buffer_enabled) ? "enabled" : "disabled",
3471 (xscale->trace.buffer_fill > 0) ? "fill" : "wrap");
3472
3473 dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
3474 if (xscale->trace.buffer_fill >= 0)
3475 xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
3476 else
3477 xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
3478
3479 return ERROR_OK;
3480 }
3481
3482 int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3483 {
3484 target_t *target;
3485 armv4_5_common_t *armv4_5;
3486 xscale_common_t *xscale;
3487
3488 if (argc < 1)
3489 {
3490 command_print(cmd_ctx, "usage: xscale trace_image <file> [base address] [type]");
3491 return ERROR_OK;
3492 }
3493
3494 target = get_current_target(cmd_ctx);
3495
3496 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3497 {
3498 return ERROR_OK;
3499 }
3500
3501 if (xscale->trace.image)
3502 {
3503 image_close(xscale->trace.image);
3504 free(xscale->trace.image);
3505 command_print(cmd_ctx, "previously loaded image found and closed");
3506 }
3507
3508 xscale->trace.image = malloc(sizeof(image_t));
3509 xscale->trace.image->base_address_set = 0;
3510 xscale->trace.image->start_address_set = 0;
3511
3512 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3513 if (argc >= 2)
3514 {
3515 xscale->trace.image->base_address_set = 1;
3516 xscale->trace.image->base_address = strtoul(args[1], NULL, 0);
3517 }
3518 else
3519 {
3520 xscale->trace.image->base_address_set = 0;
3521 }
3522
3523 if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
3524 {
3525 free(xscale->trace.image);
3526 xscale->trace.image = NULL;
3527 return ERROR_OK;
3528 }
3529
3530 return ERROR_OK;
3531 }
3532
3533 int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3534 {
3535 target_t *target = get_current_target(cmd_ctx);
3536 armv4_5_common_t *armv4_5;
3537 xscale_common_t *xscale;
3538 xscale_trace_data_t *trace_data;
3539 fileio_t file;
3540
3541 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3542 {
3543 return ERROR_OK;
3544 }
3545
3546 if (target->state != TARGET_HALTED)
3547 {
3548 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3549 return ERROR_OK;
3550 }
3551
3552 if (argc < 1)
3553 {
3554 command_print(cmd_ctx, "usage: xscale dump_trace <file>");
3555 return ERROR_OK;
3556 }
3557
3558 trace_data = xscale->trace.data;
3559
3560 if (!trace_data)
3561 {
3562 command_print(cmd_ctx, "no trace data collected");
3563 return ERROR_OK;
3564 }
3565
3566 if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
3567 {
3568 return ERROR_OK;
3569 }
3570
3571 while (trace_data)
3572 {
3573 int i;
3574
3575 fileio_write_u32(&file, trace_data->chkpt0);
3576 fileio_write_u32(&file, trace_data->chkpt1);
3577 fileio_write_u32(&file, trace_data->last_instruction);
3578 fileio_write_u32(&file, trace_data->depth);
3579
3580 for (i = 0; i < trace_data->depth; i++)
3581 fileio_write_u32(&file, trace_data->entries[i].data | ((trace_data->entries[i].type & 0xffff) << 16));
3582
3583 trace_data = trace_data->next;
3584 }
3585
3586 fileio_close(&file);
3587
3588 return ERROR_OK;
3589 }
3590
3591 int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3592 {
3593 target_t *target = get_current_target(cmd_ctx);
3594 armv4_5_common_t *armv4_5;
3595 xscale_common_t *xscale;
3596
3597 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3598 {
3599 return ERROR_OK;
3600 }
3601
3602 xscale_analyze_trace(target, cmd_ctx);
3603
3604 return ERROR_OK;
3605 }
3606
3607 int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3608 {
3609 target_t *target = get_current_target(cmd_ctx);
3610 armv4_5_common_t *armv4_5;
3611 xscale_common_t *xscale;
3612
3613 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3614 {
3615 return ERROR_OK;
3616 }
3617
3618 if (target->state != TARGET_HALTED)
3619 {
3620 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3621 return ERROR_OK;
3622 }
3623 u32 reg_no = 0;
3624 reg_t *reg = NULL;
3625 if(argc > 0)
3626 {
3627 reg_no = strtoul(args[0], NULL, 0);
3628 /*translate from xscale cp15 register no to openocd register*/
3629 switch(reg_no)
3630 {
3631 case 0:
3632 reg_no = XSCALE_MAINID;
3633 break;
3634 case 1:
3635 reg_no = XSCALE_CTRL;
3636 break;
3637 case 2:
3638 reg_no = XSCALE_TTB;
3639 break;
3640 case 3:
3641 reg_no = XSCALE_DAC;
3642 break;
3643 case 5:
3644 reg_no = XSCALE_FSR;
3645 break;
3646 case 6:
3647 reg_no = XSCALE_FAR;
3648 break;
3649 case 13:
3650 reg_no = XSCALE_PID;
3651 break;
3652 case 15:
3653 reg_no = XSCALE_CPACCESS;
3654 break;
3655 default:
3656 command_print(cmd_ctx, "invalid register number");
3657 return ERROR_INVALID_ARGUMENTS;
3658 }
3659 reg = &xscale->reg_cache->reg_list[reg_no];
3660
3661 }
3662 if(argc == 1)
3663 {
3664 u32 value;
3665
3666 /* read cp15 control register */
3667 xscale_get_reg(reg);
3668 value = buf_get_u32(reg->value, 0, 32);
3669 command_print(cmd_ctx, "%s (/%i): 0x%x", reg->name, reg->size, value);
3670 }
3671 else if(argc == 2)
3672 {
3673
3674 u32 value = strtoul(args[1], NULL, 0);
3675
3676 /* send CP write request (command 0x41) */
3677 xscale_send_u32(target, 0x41);
3678
3679 /* send CP register number */
3680 xscale_send_u32(target, reg_no);
3681
3682 /* send CP register value */
3683 xscale_send_u32(target, value);
3684
3685 /* execute cpwait to ensure outstanding operations complete */
3686 xscale_send_u32(target, 0x53);
3687 }
3688 else
3689 {
3690 command_print(cmd_ctx, "usage: cp15 [register]<, [value]>");
3691 }
3692
3693 return ERROR_OK;
3694 }
3695
3696 int xscale_register_commands(struct command_context_s *cmd_ctx)
3697 {
3698 command_t *xscale_cmd;
3699
3700 xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands");
3701
3702 register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler <target#> <address>' command takes two required operands");
3703 register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL);
3704
3705 register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL);
3706 register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU");
3707 register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
3708 register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
3709
3710 register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_idcache_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
3711
3712 register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable|disable> ['fill' [n]|'wrap']");
3713
3714 register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
3715 register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
3716 register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command,
3717 COMMAND_EXEC, "load image from <file> [base address]");
3718
3719 register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 <register> [value]");
3720
3721 armv4_5_register_commands(cmd_ctx);
3722
3723 return ERROR_OK;
3724 }
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