src/target/target/stm32stick.cfg

   1 # Hitex stm32 performance stick
   2
   3 if { [info exists CHIPNAME] } {
   4    set  _CHIPNAME $CHIPNAME
   5 } else {
   6    set  _CHIPNAME stm32_hitex
   7 }
   8
   9 if { [info exists ENDIAN] } {
  10    set  _ENDIAN $ENDIAN
  11 } else {
  12    set  _ENDIAN little
  13 }
  14
  15 # set jtag speed
  16 jtag_khz 500
  17
  18 jtag_nsrst_delay 100
  19 jtag_ntrst_delay 100
  20
  21 #use combined on interfaces or targets that can't set TRST/SRST separately
  22 reset_config trst_and_srst
  23
  24 #jtag scan chain
  25 # The CPU
  26 if { [info exists CPUTAPID ] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29   # See STM Document RM0008
  30   # Section 26.6.3
  31    set _CPUTAPID 0x3ba00477
  32 }
  33 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
  34
  35 # The boundery scan register, leave the "expected-id" undefined.
  36 jtag newtap $_CHIPNAME bs  -irlen 5 -ircapture 0x1 -irmask 0x1e
  37
  38 # What is this? It must be some extra chip on the stm32stick...
  39 jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
  40
  41 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
  42 target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
  43
  44 $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
  45
  46 #
  47 flash bank stm32x 0 0 0 0 0
  48
  49 # For more information about the configuration files, take a look at:
  50 # openocd.texi