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[openocd.git] / src / target / target / stm32.cfg
1 # script for stm32
2
3 # jtag speed
4 jtag_khz 500
5
6 jtag_nsrst_delay 100
7 jtag_ntrst_delay 100
8
9 #use combined on interfaces or targets that can't set TRST/SRST separately
10 reset_config trst_and_srst
11
12 #jtag scan chain
13 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
14 jtag_device 4 0x1 0xf 0xe
15 jtag_device 5 0x1 0x1 0x1e
16
17 #target <type> <startup mode>
18 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
19 target cortex_m3 little 0
20
21
22 working_area 0 0x20000000 16384 nobackup
23
24 #flash bank str7x <base> <size> 0 0 <target#> <variant>
25 flash bank stm32x 0 0 0 0 0
26
27 # For more information about the configuration files, take a look at:
28 # openocd.texi
Open On-Chip Debugger

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