src/target/target/eir-sam7se512.cfg

   1 #use combined on interfaces or targets that can't set TRST/SRST separately
   2 reset_config srst_only srst_pulls_trst
   3
   4 #jtag scan chain
   5 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
   6 jtag_device 4 0x1 0xf 0xe
   7
   8 target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
   9
  10
  11 [new_target_name] configure -event reset-init {
  12         # WDT_MR, disable watchdog
  13         mww 0xFFFFFD44 0x00008000
  14
  15         # RSTC_MR, enable user reset
  16         mww 0xfffffd08 0xa5000001
  17
  18         # CKGR_MOR
  19         mww 0xFFFFFC20 0x00000601
  20         sleep 10
  21
  22         # CKGR_PLLR
  23         mww 0xFFFFFC2C 0x00481c0e
  24         sleep 10
  25
  26         # PMC_MCKR
  27         mww 0xFFFFFC30 0x00000007
  28         sleep 10
  29
  30         # PMC_IER
  31         mww 0xFFFFFF60 0x00480100
  32
  33         #
  34         # Enable SDRAM interface.
  35         #
  36
  37         # Enable SDRAM control at PIO A.
  38         mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
  39         mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
  40
  41         # Enable address bus (A0, A2-A11, A13-A17) at PIO B
  42         mww 0xfffff674 0x0003effd # PIO_BSR_OFF
  43         mww 0xfffff604 0x0003effd # PIO_PDR_OFF
  44
  45         # Enable 16 bit data bus at PIO C
  46         mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
  47         mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
  48
  49         # Enable SDRAM chip select
  50         mww 0xffffff80 0x00000002 # EBI_CSA_OFF
  51
  52         # Set SDRAM characteristics in configuration register.
  53         # Hard coded values for MT48LC32M16A2 with 48MHz CPU.
  54         mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
  55         sleep 10
  56
  57         # Issue 16 bit SDRAM command: NOP
  58         mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
  59         mww 0x20000000 0x00000000
  60
  61         # Issue 16 bit SDRAM command: Precharge all
  62         mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
  63         mww 0x20000000 0x00000000
  64
  65         # Issue 8 auto-refresh cycles
  66         mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  67         mww 0x20000000 0x00000000
  68         mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  69         mww 0x20000000 0x00000000
  70         mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  71         mww 0x20000000 0x00000000
  72         mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  73         mww 0x20000000 0x00000000
  74         mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  75         mww 0x20000000 0x00000000
  76         mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  77         mww 0x20000000 0x00000000
  78         mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  79         mww 0x20000000 0x00000000
  80         mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  81         mww 0x20000000 0x00000000
  82
  83         # Issue 16 bit SDRAM command: Set mode register
  84         mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
  85         mww 0x20000014 0xcafedede
  86
  87         # Set refresh rate count ???
  88         mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
  89
  90         # Issue 16 bit SDRAM command: Normal mode
  91         mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
  92         mww 0x20000000 0x00000180
  93
  94         #
  95         # Enable external reset key.
  96         #
  97         mww 0xfffffd08 0xa5000001
  98 }
  99
 100 [new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
 101
 102 #flash bank <driver> <base> <size> <chip_width> <bus_width>
 103 flash bank at91sam7 0 0 0 0 0
 104
 105 # For more information about the configuration files, take a
 106 # look at the "Open On-Chip Debugger (openocd)" documentation.