src/target/target/at91sam9260.cfg

   1 # Thanks to Pieter Conradie for this script!
   2 # Target:    Atmel AT91SAM9260
   3 ######################################
   4
   5 # We add to the minimal configuration.
   6 source [find target/at91sam9260minimal.cfg]
   7
   8 ######################
   9 # Target configuration
  10 ######################
  11
  12 $_TARGET_NAME configure -event reset-init {
  13         # at reset chip runs at 32khz
  14         jtag_khz 8
  15         mww 0xfffffd08 0xa5000501         # RSTC_MR : enable user reset
  16         mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
  17
  18         mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
  19         sleep 20                          # wait 20 ms
  20         mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
  21         sleep 10                          # wait 10 ms
  22         mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198,656MHz
  23         sleep 20                          # wait 20 ms
  24         mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler
  25         sleep 10                          # wait 10 ms
  26         mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected
  27         sleep 10                          # wait 10 ms
  28
  29         # Now run at anything fast... ie: 10mhz!
  30         jtag_khz 10000                    # Increase JTAG Speed to 6 MHz
  31         arm7_9 dcc_downloads enable       # Enable faster DCC downloads
  32
  33         mww 0xffffec00 0x01020102         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
  34         mww 0xffffec04 0x09070806         # SMC_PULSE0
  35         mww 0xffffec08 0x000d000b         # SMC_CYCLE0
  36         mww 0xffffec0c 0x00001003         # SMC_MODE0
  37
  38         flash probe 0                     # Identify flash bank 0
  39
  40         mww 0xfffff870 0xffff0000         # PIO_ASR : Select peripheral function for D15..D31
  41         mww 0xfffff804 0xffff0000         # PIO_PDR : Disable PIO function for D15..D31
  42
  43         mww 0xffffef1c 0x2                # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
  44
  45         #mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
  46         mww 0xffffea08 0x85227254         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
  47
  48         mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
  49         mww 0x20000000 0
  50         mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
  51         mww 0x20000000 0
  52         mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
  53         mww 0x20000000 0
  54         mww 0xffffea00 0x4
  55         mww 0x20000000 0
  56         mww 0xffffea00 0x4
  57         mww 0x20000000 0
  58         mww 0xffffea00 0x4
  59         mww 0x20000000 0
  60         mww 0xffffea00 0x4
  61         mww 0x20000000 0
  62         mww 0xffffea00 0x4
  63         mww 0x20000000 0
  64         mww 0xffffea00 0x4
  65         mww 0x20000000 0
  66         mww 0xffffea00 0x4
  67         mww 0x20000000 0
  68         mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
  69         mww 0x20000000 0
  70         mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
  71         mww 0x20000000 0
  72         mww 0xffffea04 0x5d2              # SDRAMC_TR : Set refresh timer count to 15us
  73 }
  74
  75
  76 #####################
  77 # Flash configuration
  78 #####################
  79
  80 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
  81 flash bank cfi 0x10000000 0x01000000 2 2 0
  82