1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2018 by Liviu Ionescu *
7 * Copyright (C) 2009 by Marvell Technology Group Ltd. *
8 * Written by Nicolas Pitre <nico@marvell.com> *
10 * Copyright (C) 2010 by Spencer Oliver *
11 * spen@spen-soft.co.uk *
13 * Copyright (C) 2016 by Square, Inc. *
14 * Steven Stallion <stallion@squareup.com> *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
32 * Hold RISC-V semihosting support.
34 * The RISC-V code is inspired from ARM semihosting.
36 * Details can be found in chapter 8 of DUI0203I_rvct_developer_guide.pdf
46 #include "target/target.h"
47 #include "target/semihosting_common.h"
50 static int riscv_semihosting_setup(struct target
*target
, int enable
);
51 static int riscv_semihosting_post_result(struct target
*target
);
54 * Initialize RISC-V semihosting. Use common ARM code.
56 void riscv_semihosting_init(struct target
*target
)
58 semihosting_common_init(target
, riscv_semihosting_setup
,
59 riscv_semihosting_post_result
);
63 * Check for and process a semihosting request using the ARM protocol). This
64 * is meant to be called when the target is stopped due to a debug mode entry.
66 * @param target Pointer to the target to process.
67 * @param retval Pointer to a location where the return code will be stored
68 * @return non-zero value if a request was processed or an error encountered
70 semihosting_result_t
riscv_semihosting(struct target
*target
, int *retval
)
72 struct semihosting
*semihosting
= target
->semihosting
;
74 LOG_DEBUG(" -> NONE (!semihosting)");
78 if (!semihosting
->is_active
) {
79 LOG_DEBUG(" -> NONE (!semihosting->is_active)");
84 int result
= riscv_get_register(target
, &pc
, GDB_REGNO_PC
);
85 if (result
!= ERROR_OK
)
90 /* Read the current instruction, including the bracketing */
91 *retval
= target_read_memory(target
, pc
- 4, 2, 6, tmp
);
92 if (*retval
!= ERROR_OK
)
96 * The instructions that trigger a semihosting call,
97 * always uncompressed, should look like:
99 * 01f01013 slli zero,zero,0x1f
101 * 40705013 srai zero,zero,0x7
103 uint32_t pre
= target_buffer_get_u32(target
, tmp
);
104 uint32_t ebreak
= target_buffer_get_u32(target
, tmp
+ 4);
105 uint32_t post
= target_buffer_get_u32(target
, tmp
+ 8);
106 LOG_DEBUG("check %08x %08x %08x from 0x%" PRIx64
"-4", pre
, ebreak
, post
, pc
);
108 if (pre
!= 0x01f01013 || ebreak
!= 0x00100073 || post
!= 0x40705013) {
109 /* Not the magic sequence defining semihosting. */
110 LOG_DEBUG(" -> NONE (no magic)");
115 * Perform semihosting call if we are not waiting on a fileio
116 * operation to complete.
118 if (!semihosting
->hit_fileio
) {
119 /* RISC-V uses A0 and A1 to pass function arguments */
123 result
= riscv_get_register(target
, &r0
, GDB_REGNO_A0
);
124 if (result
!= ERROR_OK
) {
125 LOG_DEBUG(" -> ERROR (couldn't read a0)");
129 result
= riscv_get_register(target
, &r1
, GDB_REGNO_A1
);
130 if (result
!= ERROR_OK
) {
131 LOG_DEBUG(" -> ERROR (couldn't read a1)");
135 semihosting
->op
= r0
;
136 semihosting
->param
= r1
;
137 semihosting
->word_size_bytes
= riscv_xlen(target
) / 8;
139 /* Check for ARM operation numbers. */
140 if (0 <= semihosting
->op
&& semihosting
->op
<= 0x31) {
141 *retval
= semihosting_common(target
);
142 if (*retval
!= ERROR_OK
) {
143 LOG_ERROR("Failed semihosting operation");
147 /* Unknown operation number, not a semihosting call. */
148 LOG_DEBUG(" -> NONE (unknown operation number)");
154 * Resume target if we are not waiting on a fileio
155 * operation to complete.
157 if (semihosting
->is_resumable
&& !semihosting
->hit_fileio
) {
158 /* Resume right after the EBREAK 4 bytes instruction. */
159 *retval
= riscv_set_register(target
, GDB_REGNO_PC
, pc
+ 4);
160 if (*retval
!= ERROR_OK
)
163 LOG_DEBUG(" -> HANDLED");
167 LOG_DEBUG(" -> WAITING");
171 /* -------------------------------------------------------------------------
172 * Local functions. */
175 * Called via semihosting->setup() later, after the target is known,
176 * usually on the first semihosting command.
178 static int riscv_semihosting_setup(struct target
*target
, int enable
)
180 LOG_DEBUG("[%s] enable=%d", target_name(target
), enable
);
182 struct semihosting
*semihosting
= target
->semihosting
;
184 semihosting
->setup_time
= clock();
189 static int riscv_semihosting_post_result(struct target
*target
)
191 struct semihosting
*semihosting
= target
->semihosting
;
193 /* If not enabled, silently ignored. */
197 LOG_DEBUG("0x%" PRIx64
, semihosting
->result
);
198 riscv_set_register(target
, GDB_REGNO_A0
, semihosting
->result
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)