31f3cf63c47dd36ad03d52091f871e555ed97a7d
[openocd.git] / src / target / riscv / riscv.h
1 #ifndef RISCV_H
2 #define RISCV_H
3
4 struct riscv_program;
5
6 #include <stdint.h>
7 #include "opcodes.h"
8 #include "gdb_regs.h"
9
10 /* The register cache is statically allocated. */
11 #define RISCV_MAX_HARTS 32
12 #define RISCV_MAX_REGISTERS 5000
13 #define RISCV_MAX_TRIGGERS 32
14 #define RISCV_MAX_HWBPS 16
15
16 #define DEFAULT_COMMAND_TIMEOUT_SEC 2
17 #define DEFAULT_RESET_TIMEOUT_SEC 30
18
19 extern struct target_type riscv011_target;
20 extern struct target_type riscv013_target;
21
22 /*
23 * Definitions shared by code supporting all RISC-V versions.
24 */
25 typedef uint64_t riscv_reg_t;
26 typedef uint32_t riscv_insn_t;
27 typedef uint64_t riscv_addr_t;
28
29 enum riscv_halt_reason {
30 RISCV_HALT_INTERRUPT,
31 RISCV_HALT_BREAKPOINT,
32 RISCV_HALT_SINGLESTEP,
33 RISCV_HALT_TRIGGER,
34 RISCV_HALT_UNKNOWN,
35 RISCV_HALT_ERROR
36 };
37
38 typedef struct {
39 unsigned dtm_version;
40
41 struct command_context *cmd_ctx;
42 void *version_specific;
43
44 /* The number of harts on this system. */
45 int hart_count;
46
47 /* The hart that the RTOS thinks is currently being debugged. */
48 int rtos_hartid;
49
50 /* The hart that is currently being debugged. Note that this is
51 * different than the hartid that the RTOS is expected to use. This
52 * one will change all the time, it's more of a global argument to
53 * every function than an actual */
54 int current_hartid;
55
56 /* Enough space to store all the registers we might need to save. */
57 /* FIXME: This should probably be a bunch of register caches. */
58 uint64_t saved_registers[RISCV_MAX_HARTS][RISCV_MAX_REGISTERS];
59 bool valid_saved_registers[RISCV_MAX_HARTS][RISCV_MAX_REGISTERS];
60
61 /* OpenOCD's register cache points into here. This is not per-hart because
62 * we just invalidate the entire cache when we change which hart is
63 * selected. */
64 uint64_t reg_cache_values[RISCV_MAX_REGISTERS];
65
66 /* Single buffer that contains all register names, instead of calling
67 * malloc for each register. Needs to be freed when reg_list is freed. */
68 char *reg_names;
69
70 /* It's possible that each core has a different supported ISA set. */
71 int xlen[RISCV_MAX_HARTS];
72 riscv_reg_t misa[RISCV_MAX_HARTS];
73
74 /* The number of triggers per hart. */
75 unsigned trigger_count[RISCV_MAX_HARTS];
76
77 /* For each physical trigger, contains -1 if the hwbp is available, or the
78 * unique_id of the breakpoint/watchpoint that is using it.
79 * Note that in RTOS mode the triggers are the same across all harts the
80 * target controls, while otherwise only a single hart is controlled. */
81 int trigger_unique_id[RISCV_MAX_HWBPS];
82
83 /* The number of entries in the debug buffer. */
84 int debug_buffer_size[RISCV_MAX_HARTS];
85
86 /* This avoids invalidating the register cache too often. */
87 bool registers_initialized;
88
89 /* This hart contains an implicit ebreak at the end of the program buffer. */
90 bool impebreak;
91
92 bool triggers_enumerated;
93
94 /* Helper functions that target the various RISC-V debug spec
95 * implementations. */
96 int (*get_register)(struct target *target,
97 riscv_reg_t *value, int hid, int rid);
98 int (*set_register)(struct target *, int hartid, int regid,
99 uint64_t value);
100 int (*select_current_hart)(struct target *);
101 bool (*is_halted)(struct target *target);
102 int (*halt_current_hart)(struct target *);
103 int (*resume_current_hart)(struct target *target);
104 int (*step_current_hart)(struct target *target);
105 int (*on_halt)(struct target *target);
106 int (*on_resume)(struct target *target);
107 int (*on_step)(struct target *target);
108 enum riscv_halt_reason (*halt_reason)(struct target *target);
109 int (*write_debug_buffer)(struct target *target, unsigned index,
110 riscv_insn_t d);
111 riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned index);
112 int (*execute_debug_buffer)(struct target *target);
113 int (*dmi_write_u64_bits)(struct target *target);
114 void (*fill_dmi_write_u64)(struct target *target, char *buf, int a, uint64_t d);
115 void (*fill_dmi_read_u64)(struct target *target, char *buf, int a);
116 void (*fill_dmi_nop_u64)(struct target *target, char *buf);
117
118 int (*authdata_read)(struct target *target, uint32_t *value);
119 int (*authdata_write)(struct target *target, uint32_t value);
120
121 int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
122 int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
123 } riscv_info_t;
124
125 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
126 extern int riscv_command_timeout_sec;
127
128 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
129 extern int riscv_reset_timeout_sec;
130
131 extern bool riscv_prefer_sba;
132
133 /* Everything needs the RISC-V specific info structure, so here's a nice macro
134 * that provides that. */
135 static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));
136 static inline riscv_info_t *riscv_info(const struct target *target)
137 { return target->arch_info; }
138 #define RISCV_INFO(R) riscv_info_t *R = riscv_info(target);
139
140 extern uint8_t ir_dtmcontrol[1];
141 extern struct scan_field select_dtmcontrol;
142 extern uint8_t ir_dbus[1];
143 extern struct scan_field select_dbus;
144 extern uint8_t ir_idcode[1];
145 extern struct scan_field select_idcode;
146
147 /*** OpenOCD Interface */
148 int riscv_openocd_poll(struct target *target);
149
150 int riscv_openocd_halt(struct target *target);
151
152 int riscv_openocd_resume(
153 struct target *target,
154 int current,
155 target_addr_t address,
156 int handle_breakpoints,
157 int debug_execution
158 );
159
160 int riscv_openocd_step(
161 struct target *target,
162 int current,
163 target_addr_t address,
164 int handle_breakpoints
165 );
166
167 int riscv_openocd_assert_reset(struct target *target);
168 int riscv_openocd_deassert_reset(struct target *target);
169
170 /*** RISC-V Interface ***/
171
172 /* Initializes the shared RISC-V structure. */
173 void riscv_info_init(struct target *target, riscv_info_t *r);
174
175 /* Run control, possibly for multiple harts. The _all_harts versions resume
176 * all the enabled harts, which when running in RTOS mode is all the harts on
177 * the system. */
178 int riscv_halt_all_harts(struct target *target);
179 int riscv_halt_one_hart(struct target *target, int hartid);
180 int riscv_resume_all_harts(struct target *target);
181 int riscv_resume_one_hart(struct target *target, int hartid);
182
183 /* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
184 * then the only hart. */
185 int riscv_step_rtos_hart(struct target *target);
186
187 bool riscv_supports_extension(struct target *target, int hartid, char letter);
188
189 /* Returns XLEN for the given (or current) hart. */
190 int riscv_xlen(const struct target *target);
191 int riscv_xlen_of_hart(const struct target *target, int hartid);
192
193 bool riscv_rtos_enabled(const struct target *target);
194
195 /* Sets the current hart, which is the hart that will actually be used when
196 * issuing debug commands. */
197 int riscv_set_current_hartid(struct target *target, int hartid);
198 int riscv_current_hartid(const struct target *target);
199
200 /*** Support functions for the RISC-V 'RTOS', which provides multihart support
201 * without requiring multiple targets. */
202
203 /* When using the RTOS to debug, this selects the hart that is currently being
204 * debugged. This doesn't propogate to the hardware. */
205 void riscv_set_all_rtos_harts(struct target *target);
206 void riscv_set_rtos_hartid(struct target *target, int hartid);
207
208 /* Lists the number of harts in the system, which are assumed to be
209 * concecutive and start with mhartid=0. */
210 int riscv_count_harts(struct target *target);
211
212 /* Returns TRUE if the target has the given register on the given hart. */
213 bool riscv_has_register(struct target *target, int hartid, int regid);
214
215 /* Returns the value of the given register on the given hart. 32-bit registers
216 * are zero extended to 64 bits. */
217 int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
218 int riscv_set_register_on_hart(struct target *target, int hid, enum gdb_regno rid, uint64_t v);
219 int riscv_get_register(struct target *target, riscv_reg_t *value,
220 enum gdb_regno r);
221 int riscv_get_register_on_hart(struct target *target, riscv_reg_t *value,
222 int hartid, enum gdb_regno regid);
223
224 /* Checks the state of the current hart -- "is_halted" checks the actual
225 * on-device register. */
226 bool riscv_is_halted(struct target *target);
227 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid);
228
229 /* These helper functions let the generic program interface get target-specific
230 * information. */
231 size_t riscv_debug_buffer_size(struct target *target);
232
233 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index);
234 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn);
235 int riscv_execute_debug_buffer(struct target *target);
236
237 void riscv_fill_dmi_nop_u64(struct target *target, char *buf);
238 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d);
239 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a);
240 int riscv_dmi_write_u64_bits(struct target *target);
241
242 /* Invalidates the register cache. */
243 void riscv_invalidate_register_cache(struct target *target);
244
245 /* Returns TRUE when a hart is enabled in this target. */
246 bool riscv_hart_enabled(struct target *target, int hartid);
247
248 int riscv_enumerate_triggers(struct target *target);
249
250 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
251 int riscv_remove_breakpoint(struct target *target,
252 struct breakpoint *breakpoint);
253 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
254 int riscv_remove_watchpoint(struct target *target,
255 struct watchpoint *watchpoint);
256
257 int riscv_init_registers(struct target *target);
258
259 void riscv_semihosting_init(struct target *target);
260 int riscv_semihosting(struct target *target, int *retval);
261
262 #endif