or1k: remove address of the Free Software Foundation
[openocd.git] / src / target / openrisc / or1k.h
1 /***************************************************************************
2 * Copyright (C) 2011 by Julius Baxter *
3 * julius@opencores.org *
4 * *
5 * Copyright (C) 2013 by Marek Czerski *
6 * ma.czerski@gmail.com *
7 * *
8 * Copyright (C) 2013 by Franck Jullien *
9 * elec4fun@gmail.com *
10 * *
11 * *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
16 * *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
21 ***************************************************************************/
22
23 #ifndef OR1K_H
24 #define OR1K_H
25
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include <target/target.h>
31
32 /* SPR groups start address */
33 #define GROUP0 (0 << 11)
34 #define GROUP1 (1 << 11)
35 #define GROUP2 (2 << 11)
36 #define GROUP3 (3 << 11)
37 #define GROUP4 (4 << 11)
38 #define GROUP5 (5 << 11)
39 #define GROUP6 (6 << 11)
40 #define GROUP7 (7 << 11)
41 #define GROUP8 (8 << 11)
42 #define GROUP9 (9 << 11)
43 #define GROUP10 (10 << 11)
44
45 /* OR1K registers */
46 enum or1k_reg_nums {
47 OR1K_REG_R0 = 0,
48 OR1K_REG_R1,
49 OR1K_REG_R2,
50 OR1K_REG_R3,
51 OR1K_REG_R4,
52 OR1K_REG_R5,
53 OR1K_REG_R6,
54 OR1K_REG_R7,
55 OR1K_REG_R8,
56 OR1K_REG_R9,
57 OR1K_REG_R10,
58 OR1K_REG_R11,
59 OR1K_REG_R12,
60 OR1K_REG_R13,
61 OR1K_REG_R14,
62 OR1K_REG_R15,
63 OR1K_REG_R16,
64 OR1K_REG_R17,
65 OR1K_REG_R18,
66 OR1K_REG_R19,
67 OR1K_REG_R20,
68 OR1K_REG_R21,
69 OR1K_REG_R22,
70 OR1K_REG_R23,
71 OR1K_REG_R24,
72 OR1K_REG_R25,
73 OR1K_REG_R26,
74 OR1K_REG_R27,
75 OR1K_REG_R28,
76 OR1K_REG_R29,
77 OR1K_REG_R30,
78 OR1K_REG_R31,
79 OR1K_REG_PPC,
80 OR1K_REG_NPC,
81 OR1K_REG_SR,
82 OR1KNUMCOREREGS
83 };
84
85 struct or1k_jtag {
86 struct jtag_tap *tap;
87 int or1k_jtag_inited;
88 int or1k_jtag_module_selected;
89 uint8_t *current_reg_idx;
90 struct or1k_tap_ip *tap_ip;
91 struct or1k_du *du_core;
92 struct target *target;
93 };
94
95 struct or1k_common {
96 struct or1k_jtag jtag;
97 struct reg_cache *core_cache;
98 uint32_t core_regs[OR1KNUMCOREREGS];
99 int nb_regs;
100 struct or1k_core_reg *arch_info;
101 };
102
103 static inline struct or1k_common *
104 target_to_or1k(struct target *target)
105 {
106 return (struct or1k_common *)target->arch_info;
107 }
108
109 struct or1k_core_reg {
110 const char *name;
111 uint32_t list_num; /* Index in register cache */
112 uint32_t spr_num; /* Number in architecture's SPR space */
113 struct target *target;
114 struct or1k_common *or1k_common;
115 const char *feature; /* feature name in XML tdesc file */
116 const char *group; /* register group in XML tdesc file */
117 };
118
119 struct or1k_core_reg_init {
120 const char *name;
121 uint32_t spr_num; /* Number in architecture's SPR space */
122 const char *feature; /* feature name in XML tdesc file */
123 const char *group; /* register group in XML tdesc file */
124 };
125
126 /* ORBIS32 Trap instruction */
127 #define OR1K_TRAP_INSTR 0x21000001
128
129 enum or1k_debug_reg_nums {
130 OR1K_DEBUG_REG_DMR1 = 0,
131 OR1K_DEBUG_REG_DMR2,
132 OR1K_DEBUG_REG_DCWR0,
133 OR1K_DEBUG_REG_DCWR1,
134 OR1K_DEBUG_REG_DSR,
135 OR1K_DEBUG_REG_DRR,
136 OR1K_DEBUG_REG_NUM
137 };
138
139 #define NO_SINGLE_STEP 0
140 #define SINGLE_STEP 1
141
142 /* OR1K Debug registers and bits needed for resuming */
143 #define OR1K_DEBUG_REG_BASE GROUP6 /* Debug registers Base address */
144 #define OR1K_DMR1_CPU_REG_ADD (OR1K_DEBUG_REG_BASE + 16) /* Debug Mode Register 1 0x3010 */
145 #define OR1K_DMR1_ST 0x00400000 /* Single-step trace */
146 #define OR1K_DMR1_BT 0x00800000 /* Branch trace */
147 #define OR1K_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */
148 #define OR1K_DSR_TE 0x00002000 /* Trap exception */
149
150 /* OR1K Instruction cache registers needed for invalidating instruction
151 * memory during adding and removing breakpoints.
152 */
153 #define OR1K_ICBIR_CPU_REG_ADD ((4 << 11) + 2) /* IC Block Invalidate Register 0x2002 */
154
155 #endif