1 /***************************************************************************
2 * Copyright (C) 2011 by Julius Baxter *
3 * julius@opencores.org *
5 * Copyright (C) 2013 by Marek Czerski *
6 * ma.czerski@gmail.com *
8 * Copyright (C) 2013 by Franck Jullien *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
21 ***************************************************************************/
27 #include <jtag/jtag.h>
28 #include <target/register.h>
29 #include <target/target.h>
30 #include <target/breakpoints.h>
31 #include <target/target_type.h>
32 #include <helper/time_support.h>
33 #include <helper/fileio.h>
41 static int or1k_remove_breakpoint(struct target
*target
,
42 struct breakpoint
*breakpoint
);
44 static int or1k_read_core_reg(struct target
*target
, int num
);
45 static int or1k_write_core_reg(struct target
*target
, int num
);
47 static struct or1k_core_reg
*or1k_core_reg_list_arch_info
;
49 static const struct or1k_core_reg_init or1k_init_reg_list
[] = {
50 {"r0" , GROUP0
+ 1024, "org.gnu.gdb.or1k.group0", NULL
},
51 {"r1" , GROUP0
+ 1025, "org.gnu.gdb.or1k.group0", NULL
},
52 {"r2" , GROUP0
+ 1026, "org.gnu.gdb.or1k.group0", NULL
},
53 {"r3" , GROUP0
+ 1027, "org.gnu.gdb.or1k.group0", NULL
},
54 {"r4" , GROUP0
+ 1028, "org.gnu.gdb.or1k.group0", NULL
},
55 {"r5" , GROUP0
+ 1029, "org.gnu.gdb.or1k.group0", NULL
},
56 {"r6" , GROUP0
+ 1030, "org.gnu.gdb.or1k.group0", NULL
},
57 {"r7" , GROUP0
+ 1031, "org.gnu.gdb.or1k.group0", NULL
},
58 {"r8" , GROUP0
+ 1032, "org.gnu.gdb.or1k.group0", NULL
},
59 {"r9" , GROUP0
+ 1033, "org.gnu.gdb.or1k.group0", NULL
},
60 {"r10" , GROUP0
+ 1034, "org.gnu.gdb.or1k.group0", NULL
},
61 {"r11" , GROUP0
+ 1035, "org.gnu.gdb.or1k.group0", NULL
},
62 {"r12" , GROUP0
+ 1036, "org.gnu.gdb.or1k.group0", NULL
},
63 {"r13" , GROUP0
+ 1037, "org.gnu.gdb.or1k.group0", NULL
},
64 {"r14" , GROUP0
+ 1038, "org.gnu.gdb.or1k.group0", NULL
},
65 {"r15" , GROUP0
+ 1039, "org.gnu.gdb.or1k.group0", NULL
},
66 {"r16" , GROUP0
+ 1040, "org.gnu.gdb.or1k.group0", NULL
},
67 {"r17" , GROUP0
+ 1041, "org.gnu.gdb.or1k.group0", NULL
},
68 {"r18" , GROUP0
+ 1042, "org.gnu.gdb.or1k.group0", NULL
},
69 {"r19" , GROUP0
+ 1043, "org.gnu.gdb.or1k.group0", NULL
},
70 {"r20" , GROUP0
+ 1044, "org.gnu.gdb.or1k.group0", NULL
},
71 {"r21" , GROUP0
+ 1045, "org.gnu.gdb.or1k.group0", NULL
},
72 {"r22" , GROUP0
+ 1046, "org.gnu.gdb.or1k.group0", NULL
},
73 {"r23" , GROUP0
+ 1047, "org.gnu.gdb.or1k.group0", NULL
},
74 {"r24" , GROUP0
+ 1048, "org.gnu.gdb.or1k.group0", NULL
},
75 {"r25" , GROUP0
+ 1049, "org.gnu.gdb.or1k.group0", NULL
},
76 {"r26" , GROUP0
+ 1050, "org.gnu.gdb.or1k.group0", NULL
},
77 {"r27" , GROUP0
+ 1051, "org.gnu.gdb.or1k.group0", NULL
},
78 {"r28" , GROUP0
+ 1052, "org.gnu.gdb.or1k.group0", NULL
},
79 {"r29" , GROUP0
+ 1053, "org.gnu.gdb.or1k.group0", NULL
},
80 {"r30" , GROUP0
+ 1054, "org.gnu.gdb.or1k.group0", NULL
},
81 {"r31" , GROUP0
+ 1055, "org.gnu.gdb.or1k.group0", NULL
},
82 {"ppc" , GROUP0
+ 18, "org.gnu.gdb.or1k.group0", NULL
},
83 {"npc" , GROUP0
+ 16, "org.gnu.gdb.or1k.group0", NULL
},
84 {"sr" , GROUP0
+ 17, "org.gnu.gdb.or1k.group0", NULL
},
85 {"vr" , GROUP0
+ 0, "org.gnu.gdb.or1k.group0", "system"},
86 {"upr" , GROUP0
+ 1, "org.gnu.gdb.or1k.group0", "system"},
87 {"cpucfgr" , GROUP0
+ 2, "org.gnu.gdb.or1k.group0", "system"},
88 {"dmmucfgr" , GROUP0
+ 3, "org.gnu.gdb.or1k.group0", "system"},
89 {"immucfgr" , GROUP0
+ 4, "org.gnu.gdb.or1k.group0", "system"},
90 {"dccfgr" , GROUP0
+ 5, "org.gnu.gdb.or1k.group0", "system"},
91 {"iccfgr" , GROUP0
+ 6, "org.gnu.gdb.or1k.group0", "system"},
92 {"dcfgr" , GROUP0
+ 7, "org.gnu.gdb.or1k.group0", "system"},
93 {"pccfgr" , GROUP0
+ 8, "org.gnu.gdb.or1k.group0", "system"},
94 {"fpcsr" , GROUP0
+ 20, "org.gnu.gdb.or1k.group0", "system"},
95 {"epcr0" , GROUP0
+ 32, "org.gnu.gdb.or1k.group0", "system"},
96 {"epcr1" , GROUP0
+ 33, "org.gnu.gdb.or1k.group0", "system"},
97 {"epcr2" , GROUP0
+ 34, "org.gnu.gdb.or1k.group0", "system"},
98 {"epcr3" , GROUP0
+ 35, "org.gnu.gdb.or1k.group0", "system"},
99 {"epcr4" , GROUP0
+ 36, "org.gnu.gdb.or1k.group0", "system"},
100 {"epcr5" , GROUP0
+ 37, "org.gnu.gdb.or1k.group0", "system"},
101 {"epcr6" , GROUP0
+ 38, "org.gnu.gdb.or1k.group0", "system"},
102 {"epcr7" , GROUP0
+ 39, "org.gnu.gdb.or1k.group0", "system"},
103 {"epcr8" , GROUP0
+ 40, "org.gnu.gdb.or1k.group0", "system"},
104 {"epcr9" , GROUP0
+ 41, "org.gnu.gdb.or1k.group0", "system"},
105 {"epcr10" , GROUP0
+ 42, "org.gnu.gdb.or1k.group0", "system"},
106 {"epcr11" , GROUP0
+ 43, "org.gnu.gdb.or1k.group0", "system"},
107 {"epcr12" , GROUP0
+ 44, "org.gnu.gdb.or1k.group0", "system"},
108 {"epcr13" , GROUP0
+ 45, "org.gnu.gdb.or1k.group0", "system"},
109 {"epcr14" , GROUP0
+ 46, "org.gnu.gdb.or1k.group0", "system"},
110 {"epcr15" , GROUP0
+ 47, "org.gnu.gdb.or1k.group0", "system"},
111 {"eear0" , GROUP0
+ 48, "org.gnu.gdb.or1k.group0", "system"},
112 {"eear1" , GROUP0
+ 49, "org.gnu.gdb.or1k.group0", "system"},
113 {"eear2" , GROUP0
+ 50, "org.gnu.gdb.or1k.group0", "system"},
114 {"eear3" , GROUP0
+ 51, "org.gnu.gdb.or1k.group0", "system"},
115 {"eear4" , GROUP0
+ 52, "org.gnu.gdb.or1k.group0", "system"},
116 {"eear5" , GROUP0
+ 53, "org.gnu.gdb.or1k.group0", "system"},
117 {"eear6" , GROUP0
+ 54, "org.gnu.gdb.or1k.group0", "system"},
118 {"eear7" , GROUP0
+ 55, "org.gnu.gdb.or1k.group0", "system"},
119 {"eear8" , GROUP0
+ 56, "org.gnu.gdb.or1k.group0", "system"},
120 {"eear9" , GROUP0
+ 57, "org.gnu.gdb.or1k.group0", "system"},
121 {"eear10" , GROUP0
+ 58, "org.gnu.gdb.or1k.group0", "system"},
122 {"eear11" , GROUP0
+ 59, "org.gnu.gdb.or1k.group0", "system"},
123 {"eear12" , GROUP0
+ 60, "org.gnu.gdb.or1k.group0", "system"},
124 {"eear13" , GROUP0
+ 61, "org.gnu.gdb.or1k.group0", "system"},
125 {"eear14" , GROUP0
+ 62, "org.gnu.gdb.or1k.group0", "system"},
126 {"eear15" , GROUP0
+ 63, "org.gnu.gdb.or1k.group0", "system"},
127 {"esr0" , GROUP0
+ 64, "org.gnu.gdb.or1k.group0", "system"},
128 {"esr1" , GROUP0
+ 65, "org.gnu.gdb.or1k.group0", "system"},
129 {"esr2" , GROUP0
+ 66, "org.gnu.gdb.or1k.group0", "system"},
130 {"esr3" , GROUP0
+ 67, "org.gnu.gdb.or1k.group0", "system"},
131 {"esr4" , GROUP0
+ 68, "org.gnu.gdb.or1k.group0", "system"},
132 {"esr5" , GROUP0
+ 69, "org.gnu.gdb.or1k.group0", "system"},
133 {"esr6" , GROUP0
+ 70, "org.gnu.gdb.or1k.group0", "system"},
134 {"esr7" , GROUP0
+ 71, "org.gnu.gdb.or1k.group0", "system"},
135 {"esr8" , GROUP0
+ 72, "org.gnu.gdb.or1k.group0", "system"},
136 {"esr9" , GROUP0
+ 73, "org.gnu.gdb.or1k.group0", "system"},
137 {"esr10" , GROUP0
+ 74, "org.gnu.gdb.or1k.group0", "system"},
138 {"esr11" , GROUP0
+ 75, "org.gnu.gdb.or1k.group0", "system"},
139 {"esr12" , GROUP0
+ 76, "org.gnu.gdb.or1k.group0", "system"},
140 {"esr13" , GROUP0
+ 77, "org.gnu.gdb.or1k.group0", "system"},
141 {"esr14" , GROUP0
+ 78, "org.gnu.gdb.or1k.group0", "system"},
142 {"esr15" , GROUP0
+ 79, "org.gnu.gdb.or1k.group0", "system"},
144 {"dmmuucr" , GROUP1
+ 0, "org.gnu.gdb.or1k.group1", "dmmu"},
145 {"dmmuupr" , GROUP1
+ 1, "org.gnu.gdb.or1k.group1", "dmmu"},
146 {"dtlbeir" , GROUP1
+ 2, "org.gnu.gdb.or1k.group1", "dmmu"},
147 {"datbmr0" , GROUP1
+ 4, "org.gnu.gdb.or1k.group1", "dmmu"},
148 {"datbmr1" , GROUP1
+ 5, "org.gnu.gdb.or1k.group1", "dmmu"},
149 {"datbmr2" , GROUP1
+ 6, "org.gnu.gdb.or1k.group1", "dmmu"},
150 {"datbmr3" , GROUP1
+ 7, "org.gnu.gdb.or1k.group1", "dmmu"},
151 {"datbtr0" , GROUP1
+ 8, "org.gnu.gdb.or1k.group1", "dmmu"},
152 {"datbtr1" , GROUP1
+ 9, "org.gnu.gdb.or1k.group1", "dmmu"},
153 {"datbtr2" , GROUP1
+ 10, "org.gnu.gdb.or1k.group1", "dmmu"},
154 {"datbtr3" , GROUP1
+ 11, "org.gnu.gdb.or1k.group1", "dmmu"},
156 {"immucr" , GROUP2
+ 0, "org.gnu.gdb.or1k.group2", "immu"},
157 {"immupr" , GROUP2
+ 1, "org.gnu.gdb.or1k.group2", "immu"},
158 {"itlbeir" , GROUP2
+ 2, "org.gnu.gdb.or1k.group2", "immu"},
159 {"iatbmr0" , GROUP2
+ 4, "org.gnu.gdb.or1k.group2", "immu"},
160 {"iatbmr1" , GROUP2
+ 5, "org.gnu.gdb.or1k.group2", "immu"},
161 {"iatbmr2" , GROUP2
+ 6, "org.gnu.gdb.or1k.group2", "immu"},
162 {"iatbmr3" , GROUP2
+ 7, "org.gnu.gdb.or1k.group2", "immu"},
163 {"iatbtr0" , GROUP2
+ 8, "org.gnu.gdb.or1k.group2", "immu"},
164 {"iatbtr1" , GROUP2
+ 9, "org.gnu.gdb.or1k.group2", "immu"},
165 {"iatbtr2" , GROUP2
+ 10, "org.gnu.gdb.or1k.group2", "immu"},
166 {"iatbtr3" , GROUP2
+ 11, "org.gnu.gdb.or1k.group2", "immu"},
168 {"dccr" , GROUP3
+ 0, "org.gnu.gdb.or1k.group3", "dcache"},
169 {"dcbpr" , GROUP3
+ 1, "org.gnu.gdb.or1k.group3", "dcache"},
170 {"dcbfr" , GROUP3
+ 2, "org.gnu.gdb.or1k.group3", "dcache"},
171 {"dcbir" , GROUP3
+ 3, "org.gnu.gdb.or1k.group3", "dcache"},
172 {"dcbwr" , GROUP3
+ 4, "org.gnu.gdb.or1k.group3", "dcache"},
173 {"dcblr" , GROUP3
+ 5, "org.gnu.gdb.or1k.group3", "dcache"},
175 {"iccr" , GROUP4
+ 0, "org.gnu.gdb.or1k.group4", "icache"},
176 {"icbpr" , GROUP4
+ 1, "org.gnu.gdb.or1k.group4", "icache"},
177 {"icbir" , GROUP4
+ 2, "org.gnu.gdb.or1k.group4", "icache"},
178 {"icblr" , GROUP4
+ 3, "org.gnu.gdb.or1k.group4", "icache"},
180 {"maclo" , GROUP5
+ 0, "org.gnu.gdb.or1k.group5", "mac"},
181 {"machi" , GROUP5
+ 1, "org.gnu.gdb.or1k.group5", "mac"},
183 {"dvr0" , GROUP6
+ 0, "org.gnu.gdb.or1k.group6", "debug"},
184 {"dvr1" , GROUP6
+ 1, "org.gnu.gdb.or1k.group6", "debug"},
185 {"dvr2" , GROUP6
+ 2, "org.gnu.gdb.or1k.group6", "debug"},
186 {"dvr3" , GROUP6
+ 3, "org.gnu.gdb.or1k.group6", "debug"},
187 {"dvr4" , GROUP6
+ 4, "org.gnu.gdb.or1k.group6", "debug"},
188 {"dvr5" , GROUP6
+ 5, "org.gnu.gdb.or1k.group6", "debug"},
189 {"dvr6" , GROUP6
+ 6, "org.gnu.gdb.or1k.group6", "debug"},
190 {"dvr7" , GROUP6
+ 7, "org.gnu.gdb.or1k.group6", "debug"},
191 {"dcr0" , GROUP6
+ 8, "org.gnu.gdb.or1k.group6", "debug"},
192 {"dcr1" , GROUP6
+ 9, "org.gnu.gdb.or1k.group6", "debug"},
193 {"dcr2" , GROUP6
+ 10, "org.gnu.gdb.or1k.group6", "debug"},
194 {"dcr3" , GROUP6
+ 11, "org.gnu.gdb.or1k.group6", "debug"},
195 {"dcr4" , GROUP6
+ 12, "org.gnu.gdb.or1k.group6", "debug"},
196 {"dcr5" , GROUP6
+ 13, "org.gnu.gdb.or1k.group6", "debug"},
197 {"dcr6" , GROUP6
+ 14, "org.gnu.gdb.or1k.group6", "debug"},
198 {"dcr7" , GROUP6
+ 15, "org.gnu.gdb.or1k.group6", "debug"},
199 {"dmr1" , GROUP6
+ 16, "org.gnu.gdb.or1k.group6", "debug"},
200 {"dmr2" , GROUP6
+ 17, "org.gnu.gdb.or1k.group6", "debug"},
201 {"dcwr0" , GROUP6
+ 18, "org.gnu.gdb.or1k.group6", "debug"},
202 {"dcwr1" , GROUP6
+ 19, "org.gnu.gdb.or1k.group6", "debug"},
203 {"dsr" , GROUP6
+ 20, "org.gnu.gdb.or1k.group6", "debug"},
204 {"drr" , GROUP6
+ 21, "org.gnu.gdb.or1k.group6", "debug"},
206 {"pccr0" , GROUP7
+ 0, "org.gnu.gdb.or1k.group7", "perf"},
207 {"pccr1" , GROUP7
+ 1, "org.gnu.gdb.or1k.group7", "perf"},
208 {"pccr2" , GROUP7
+ 2, "org.gnu.gdb.or1k.group7", "perf"},
209 {"pccr3" , GROUP7
+ 3, "org.gnu.gdb.or1k.group7", "perf"},
210 {"pccr4" , GROUP7
+ 4, "org.gnu.gdb.or1k.group7", "perf"},
211 {"pccr5" , GROUP7
+ 5, "org.gnu.gdb.or1k.group7", "perf"},
212 {"pccr6" , GROUP7
+ 6, "org.gnu.gdb.or1k.group7", "perf"},
213 {"pccr7" , GROUP7
+ 7, "org.gnu.gdb.or1k.group7", "perf"},
214 {"pcmr0" , GROUP7
+ 8, "org.gnu.gdb.or1k.group7", "perf"},
215 {"pcmr1" , GROUP7
+ 9, "org.gnu.gdb.or1k.group7", "perf"},
216 {"pcmr2" , GROUP7
+ 10, "org.gnu.gdb.or1k.group7", "perf"},
217 {"pcmr3" , GROUP7
+ 11, "org.gnu.gdb.or1k.group7", "perf"},
218 {"pcmr4" , GROUP7
+ 12, "org.gnu.gdb.or1k.group7", "perf"},
219 {"pcmr5" , GROUP7
+ 13, "org.gnu.gdb.or1k.group7", "perf"},
220 {"pcmr6" , GROUP7
+ 14, "org.gnu.gdb.or1k.group7", "perf"},
221 {"pcmr7" , GROUP7
+ 15, "org.gnu.gdb.or1k.group7", "perf"},
223 {"pmr" , GROUP8
+ 0, "org.gnu.gdb.or1k.group8", "power"},
225 {"picmr" , GROUP9
+ 0, "org.gnu.gdb.or1k.group9", "pic"},
226 {"picsr" , GROUP9
+ 2, "org.gnu.gdb.or1k.group9", "pic"},
228 {"ttmr" , GROUP10
+ 0, "org.gnu.gdb.or1k.group10", "timer"},
229 {"ttcr" , GROUP10
+ 1, "org.gnu.gdb.or1k.group10", "timer"},
232 static int or1k_add_reg(struct target
*target
, struct or1k_core_reg
*new_reg
)
234 struct or1k_common
*or1k
= target_to_or1k(target
);
235 int reg_list_size
= or1k
->nb_regs
* sizeof(struct or1k_core_reg
);
237 or1k_core_reg_list_arch_info
= realloc(or1k_core_reg_list_arch_info
,
238 reg_list_size
+ sizeof(struct or1k_core_reg
));
240 memcpy(&or1k_core_reg_list_arch_info
[or1k
->nb_regs
], new_reg
,
241 sizeof(struct or1k_core_reg
));
243 or1k_core_reg_list_arch_info
[or1k
->nb_regs
].list_num
= or1k
->nb_regs
;
250 static int or1k_create_reg_list(struct target
*target
)
252 struct or1k_common
*or1k
= target_to_or1k(target
);
256 or1k_core_reg_list_arch_info
= malloc(ARRAY_SIZE(or1k_init_reg_list
) *
257 sizeof(struct or1k_core_reg
));
259 for (int i
= 0; i
< (int)ARRAY_SIZE(or1k_init_reg_list
); i
++) {
260 or1k_core_reg_list_arch_info
[i
].name
= or1k_init_reg_list
[i
].name
;
261 or1k_core_reg_list_arch_info
[i
].spr_num
= or1k_init_reg_list
[i
].spr_num
;
262 or1k_core_reg_list_arch_info
[i
].group
= or1k_init_reg_list
[i
].group
;
263 or1k_core_reg_list_arch_info
[i
].feature
= or1k_init_reg_list
[i
].feature
;
264 or1k_core_reg_list_arch_info
[i
].list_num
= i
;
265 or1k_core_reg_list_arch_info
[i
].target
= NULL
;
266 or1k_core_reg_list_arch_info
[i
].or1k_common
= NULL
;
269 or1k
->nb_regs
= ARRAY_SIZE(or1k_init_reg_list
);
271 struct or1k_core_reg new_reg
;
272 new_reg
.target
= NULL
;
273 new_reg
.or1k_common
= NULL
;
276 for (int way
= 0; way
< 4; way
++) {
277 for (int i
= 0; i
< 128; i
++) {
279 sprintf(name
, "dtlbw%dmr%d", way
, i
);
280 new_reg
.name
= strdup(name
);
281 new_reg
.spr_num
= GROUP1
+ 512 + i
+ (way
* 256);
282 new_reg
.feature
= "org.gnu.gdb.or1k.group1";
283 new_reg
.group
= "dmmu";
284 or1k_add_reg(target
, &new_reg
);
286 sprintf(name
, "dtlbw%dtr%d", way
, i
);
287 new_reg
.name
= strdup(name
);
288 new_reg
.spr_num
= GROUP1
+ 640 + i
+ (way
* 256);
289 new_reg
.feature
= "org.gnu.gdb.or1k.group1";
290 new_reg
.group
= "dmmu";
291 or1k_add_reg(target
, &new_reg
);
294 sprintf(name
, "itlbw%dmr%d", way
, i
);
295 new_reg
.name
= strdup(name
);
296 new_reg
.spr_num
= GROUP2
+ 512 + i
+ (way
* 256);
297 new_reg
.feature
= "org.gnu.gdb.or1k.group2";
298 new_reg
.group
= "immu";
299 or1k_add_reg(target
, &new_reg
);
302 sprintf(name
, "itlbw%dtr%d", way
, i
);
303 new_reg
.name
= strdup(name
);
304 new_reg
.spr_num
= GROUP2
+ 640 + i
+ (way
* 256);
305 new_reg
.feature
= "org.gnu.gdb.or1k.group2";
306 new_reg
.group
= "immu";
307 or1k_add_reg(target
, &new_reg
);
315 static int or1k_jtag_read_regs(struct or1k_common
*or1k
, uint32_t *regs
)
317 struct or1k_du
*du_core
= or1k_jtag_to_du(&or1k
->jtag
);
321 return du_core
->or1k_jtag_read_cpu(&or1k
->jtag
,
322 or1k
->arch_info
[OR1K_REG_R0
].spr_num
, OR1K_REG_R31
+ 1,
326 static int or1k_jtag_write_regs(struct or1k_common
*or1k
, uint32_t *regs
)
328 struct or1k_du
*du_core
= or1k_jtag_to_du(&or1k
->jtag
);
332 return du_core
->or1k_jtag_write_cpu(&or1k
->jtag
,
333 or1k
->arch_info
[OR1K_REG_R0
].spr_num
, OR1K_REG_R31
+ 1,
337 static int or1k_save_context(struct target
*target
)
339 struct or1k_common
*or1k
= target_to_or1k(target
);
340 struct or1k_du
*du_core
= or1k_to_du(or1k
);
346 for (int i
= 0; i
< OR1KNUMCOREREGS
; i
++) {
347 if (!or1k
->core_cache
->reg_list
[i
].valid
) {
348 if (i
== OR1K_REG_PPC
|| i
== OR1K_REG_NPC
|| i
== OR1K_REG_SR
) {
349 retval
= du_core
->or1k_jtag_read_cpu(&or1k
->jtag
,
350 or1k
->arch_info
[i
].spr_num
, 1,
351 &or1k
->core_regs
[i
]);
352 if (retval
!= ERROR_OK
)
354 } else if (!regs_read
) {
355 /* read gpr registers at once (but only one time in this loop) */
356 retval
= or1k_jtag_read_regs(or1k
, or1k
->core_regs
);
357 if (retval
!= ERROR_OK
)
359 /* prevent next reads in this loop */
362 /* We've just updated the core_reg[i], now update
364 or1k_read_core_reg(target
, i
);
371 static int or1k_restore_context(struct target
*target
)
373 struct or1k_common
*or1k
= target_to_or1k(target
);
374 struct or1k_du
*du_core
= or1k_to_du(or1k
);
380 for (int i
= 0; i
< OR1KNUMCOREREGS
; i
++) {
381 if (or1k
->core_cache
->reg_list
[i
].dirty
) {
382 or1k_write_core_reg(target
, i
);
384 if (i
== OR1K_REG_PPC
|| i
== OR1K_REG_NPC
|| i
== OR1K_REG_SR
) {
385 retval
= du_core
->or1k_jtag_write_cpu(&or1k
->jtag
,
386 or1k
->arch_info
[i
].spr_num
, 1,
387 &or1k
->core_regs
[i
]);
388 if (retval
!= ERROR_OK
) {
389 LOG_ERROR("Error while restoring context");
398 /* read gpr registers at once (but only one time in this loop) */
399 retval
= or1k_jtag_write_regs(or1k
, or1k
->core_regs
);
400 if (retval
!= ERROR_OK
) {
401 LOG_ERROR("Error while restoring context");
409 static int or1k_read_core_reg(struct target
*target
, int num
)
411 struct or1k_common
*or1k
= target_to_or1k(target
);
412 struct or1k_du
*du_core
= or1k_to_du(or1k
);
417 if ((num
< 0) || (num
>= or1k
->nb_regs
))
418 return ERROR_COMMAND_SYNTAX_ERROR
;
420 if ((num
>= 0) && (num
< OR1KNUMCOREREGS
)) {
421 reg_value
= or1k
->core_regs
[num
];
422 buf_set_u32(or1k
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
423 LOG_DEBUG("Read core reg %i value 0x%08" PRIx32
, num
, reg_value
);
424 or1k
->core_cache
->reg_list
[num
].valid
= 1;
425 or1k
->core_cache
->reg_list
[num
].dirty
= 0;
427 /* This is an spr, always read value from HW */
428 int retval
= du_core
->or1k_jtag_read_cpu(&or1k
->jtag
,
429 or1k
->arch_info
[num
].spr_num
, 1, ®_value
);
430 if (retval
!= ERROR_OK
) {
431 LOG_ERROR("Error while reading spr 0x%08" PRIx32
, or1k
->arch_info
[num
].spr_num
);
434 buf_set_u32(or1k
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
435 LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32
, num
, reg_value
);
441 static int or1k_write_core_reg(struct target
*target
, int num
)
443 struct or1k_common
*or1k
= target_to_or1k(target
);
447 if ((num
< 0) || (num
>= OR1KNUMCOREREGS
))
448 return ERROR_COMMAND_SYNTAX_ERROR
;
450 uint32_t reg_value
= buf_get_u32(or1k
->core_cache
->reg_list
[num
].value
, 0, 32);
451 or1k
->core_regs
[num
] = reg_value
;
452 LOG_DEBUG("Write core reg %i value 0x%08" PRIx32
, num
, reg_value
);
453 or1k
->core_cache
->reg_list
[num
].valid
= 1;
454 or1k
->core_cache
->reg_list
[num
].dirty
= 0;
459 static int or1k_get_core_reg(struct reg
*reg
)
461 struct or1k_core_reg
*or1k_reg
= reg
->arch_info
;
462 struct target
*target
= or1k_reg
->target
;
466 if (target
->state
!= TARGET_HALTED
)
467 return ERROR_TARGET_NOT_HALTED
;
469 return or1k_read_core_reg(target
, or1k_reg
->list_num
);
472 static int or1k_set_core_reg(struct reg
*reg
, uint8_t *buf
)
474 struct or1k_core_reg
*or1k_reg
= reg
->arch_info
;
475 struct target
*target
= or1k_reg
->target
;
476 struct or1k_common
*or1k
= target_to_or1k(target
);
477 struct or1k_du
*du_core
= or1k_to_du(or1k
);
478 uint32_t value
= buf_get_u32(buf
, 0, 32);
482 if (target
->state
!= TARGET_HALTED
)
483 return ERROR_TARGET_NOT_HALTED
;
485 if (or1k_reg
->list_num
< OR1KNUMCOREREGS
) {
486 buf_set_u32(reg
->value
, 0, 32, value
);
490 /* This is an spr, write it to the HW */
491 int retval
= du_core
->or1k_jtag_write_cpu(&or1k
->jtag
,
492 or1k_reg
->spr_num
, 1, &value
);
493 if (retval
!= ERROR_OK
) {
494 LOG_ERROR("Error while writing spr 0x%08" PRIx32
, or1k_reg
->spr_num
);
502 static const struct reg_arch_type or1k_reg_type
= {
503 .get
= or1k_get_core_reg
,
504 .set
= or1k_set_core_reg
,
507 static struct reg_cache
*or1k_build_reg_cache(struct target
*target
)
509 struct or1k_common
*or1k
= target_to_or1k(target
);
510 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
511 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
512 struct reg
*reg_list
= calloc(or1k
->nb_regs
, sizeof(struct reg
));
513 struct or1k_core_reg
*arch_info
=
514 malloc((or1k
->nb_regs
) * sizeof(struct or1k_core_reg
));
515 struct reg_feature
*feature
;
519 /* Build the process context cache */
520 cache
->name
= "OpenRISC 1000 registers";
522 cache
->reg_list
= reg_list
;
523 cache
->num_regs
= or1k
->nb_regs
;
525 or1k
->core_cache
= cache
;
526 or1k
->arch_info
= arch_info
;
528 for (int i
= 0; i
< or1k
->nb_regs
; i
++) {
529 arch_info
[i
] = or1k_core_reg_list_arch_info
[i
];
530 arch_info
[i
].target
= target
;
531 arch_info
[i
].or1k_common
= or1k
;
532 reg_list
[i
].name
= or1k_core_reg_list_arch_info
[i
].name
;
534 feature
= malloc(sizeof(struct reg_feature
));
535 feature
->name
= or1k_core_reg_list_arch_info
[i
].feature
;
536 reg_list
[i
].feature
= feature
;
538 reg_list
[i
].group
= or1k_core_reg_list_arch_info
[i
].group
;
539 reg_list
[i
].size
= 32;
540 reg_list
[i
].value
= calloc(1, 4);
541 reg_list
[i
].dirty
= 0;
542 reg_list
[i
].valid
= 0;
543 reg_list
[i
].type
= &or1k_reg_type
;
544 reg_list
[i
].arch_info
= &arch_info
[i
];
545 reg_list
[i
].number
= i
;
546 reg_list
[i
].exist
= true;
552 static int or1k_debug_entry(struct target
*target
)
556 int retval
= or1k_save_context(target
);
557 if (retval
!= ERROR_OK
) {
558 LOG_ERROR("Error while calling or1k_save_context");
562 struct or1k_common
*or1k
= target_to_or1k(target
);
563 uint32_t addr
= or1k
->core_regs
[OR1K_REG_NPC
];
565 if (breakpoint_find(target
, addr
))
566 /* Halted on a breakpoint, step back to permit executing the instruction there */
567 retval
= or1k_set_core_reg(&or1k
->core_cache
->reg_list
[OR1K_REG_NPC
],
573 static int or1k_halt(struct target
*target
)
575 struct or1k_common
*or1k
= target_to_or1k(target
);
576 struct or1k_du
*du_core
= or1k_to_du(or1k
);
578 LOG_DEBUG("target->state: %s",
579 target_state_name(target
));
581 if (target
->state
== TARGET_HALTED
) {
582 LOG_DEBUG("Target was already halted");
586 if (target
->state
== TARGET_UNKNOWN
)
587 LOG_WARNING("Target was in unknown state when halt was requested");
589 if (target
->state
== TARGET_RESET
) {
590 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) &&
592 LOG_ERROR("Can't request a halt while in reset if nSRST pulls nTRST");
593 return ERROR_TARGET_FAILURE
;
595 target
->debug_reason
= DBG_REASON_DBGRQ
;
600 int retval
= du_core
->or1k_cpu_stall(&or1k
->jtag
, CPU_STALL
);
601 if (retval
!= ERROR_OK
) {
602 LOG_ERROR("Impossible to stall the CPU");
606 target
->debug_reason
= DBG_REASON_DBGRQ
;
611 static int or1k_is_cpu_running(struct target
*target
, int *running
)
613 struct or1k_common
*or1k
= target_to_or1k(target
);
614 struct or1k_du
*du_core
= or1k_to_du(or1k
);
617 const int RETRIES_MAX
= 5;
619 /* Have a retry loop to determine of the CPU is running.
620 If target has been hard reset for any reason, it might take a couple
621 of goes before it's ready again.
623 while (tries
< RETRIES_MAX
) {
627 retval
= du_core
->or1k_is_cpu_running(&or1k
->jtag
, running
);
628 if (retval
!= ERROR_OK
) {
629 LOG_WARNING("Debug IF CPU control reg read failure.");
630 /* Try once to restart the JTAG infrastructure -
631 quite possibly the board has just been reset. */
632 LOG_WARNING("Resetting JTAG TAP state and reconnectiong to debug IF.");
633 du_core
->or1k_jtag_init(&or1k
->jtag
);
635 LOG_WARNING("...attempt %d of %d", tries
, RETRIES_MAX
);
644 LOG_ERROR("Could not re-establish communication with target");
648 static int or1k_poll(struct target
*target
)
653 retval
= or1k_is_cpu_running(target
, &running
);
654 if (retval
!= ERROR_OK
) {
655 LOG_ERROR("Error while calling or1k_is_cpu_running");
659 /* check for processor halted */
661 /* It's actually stalled, so update our software's state */
662 if ((target
->state
== TARGET_RUNNING
) ||
663 (target
->state
== TARGET_RESET
)) {
665 target
->state
= TARGET_HALTED
;
667 retval
= or1k_debug_entry(target
);
668 if (retval
!= ERROR_OK
) {
669 LOG_ERROR("Error while calling or1k_debug_entry");
673 target_call_event_callbacks(target
,
674 TARGET_EVENT_HALTED
);
675 } else if (target
->state
== TARGET_DEBUG_RUNNING
) {
676 target
->state
= TARGET_HALTED
;
678 retval
= or1k_debug_entry(target
);
679 if (retval
!= ERROR_OK
) {
680 LOG_ERROR("Error while calling or1k_debug_entry");
684 target_call_event_callbacks(target
,
685 TARGET_EVENT_DEBUG_HALTED
);
687 } else { /* ... target is running */
689 /* If target was supposed to be stalled, stall it again */
690 if (target
->state
== TARGET_HALTED
) {
692 target
->state
= TARGET_RUNNING
;
694 retval
= or1k_halt(target
);
695 if (retval
!= ERROR_OK
) {
696 LOG_ERROR("Error while calling or1k_halt");
700 retval
= or1k_debug_entry(target
);
701 if (retval
!= ERROR_OK
) {
702 LOG_ERROR("Error while calling or1k_debug_entry");
706 target_call_event_callbacks(target
,
707 TARGET_EVENT_DEBUG_HALTED
);
710 target
->state
= TARGET_RUNNING
;
717 static int or1k_assert_reset(struct target
*target
)
719 struct or1k_common
*or1k
= target_to_or1k(target
);
720 struct or1k_du
*du_core
= or1k_to_du(or1k
);
724 int retval
= du_core
->or1k_cpu_reset(&or1k
->jtag
, CPU_RESET
);
725 if (retval
!= ERROR_OK
) {
726 LOG_ERROR("Error while asserting RESET");
733 static int or1k_deassert_reset(struct target
*target
)
735 struct or1k_common
*or1k
= target_to_or1k(target
);
736 struct or1k_du
*du_core
= or1k_to_du(or1k
);
740 int retval
= du_core
->or1k_cpu_reset(&or1k
->jtag
, CPU_NOT_RESET
);
741 if (retval
!= ERROR_OK
) {
742 LOG_ERROR("Error while desasserting RESET");
749 static int or1k_soft_reset_halt(struct target
*target
)
751 struct or1k_common
*or1k
= target_to_or1k(target
);
752 struct or1k_du
*du_core
= or1k_to_du(or1k
);
756 int retval
= du_core
->or1k_cpu_stall(&or1k
->jtag
, CPU_STALL
);
757 if (retval
!= ERROR_OK
) {
758 LOG_ERROR("Error while stalling the CPU");
762 retval
= or1k_assert_reset(target
);
763 if (retval
!= ERROR_OK
)
766 retval
= or1k_deassert_reset(target
);
767 if (retval
!= ERROR_OK
)
773 static bool is_any_soft_breakpoint(struct target
*target
)
775 struct breakpoint
*breakpoint
= target
->breakpoints
;
780 if (breakpoint
->type
== BKPT_SOFT
)
786 static int or1k_resume_or_step(struct target
*target
, int current
,
787 uint32_t address
, int handle_breakpoints
,
788 int debug_execution
, int step
)
790 struct or1k_common
*or1k
= target_to_or1k(target
);
791 struct or1k_du
*du_core
= or1k_to_du(or1k
);
792 struct breakpoint
*breakpoint
= NULL
;
794 uint32_t debug_reg_list
[OR1K_DEBUG_REG_NUM
];
796 LOG_DEBUG("Addr: 0x%" PRIx32
", stepping: %s, handle breakpoints %s\n",
797 address
, step
? "yes" : "no", handle_breakpoints
? "yes" : "no");
799 if (target
->state
!= TARGET_HALTED
) {
800 LOG_ERROR("Target not halted");
801 return ERROR_TARGET_NOT_HALTED
;
804 if (!debug_execution
)
805 target_free_all_working_areas(target
);
807 /* current ? continue on current pc : continue at <address> */
809 buf_set_u32(or1k
->core_cache
->reg_list
[OR1K_REG_NPC
].value
, 0,
812 int retval
= or1k_restore_context(target
);
813 if (retval
!= ERROR_OK
) {
814 LOG_ERROR("Error while calling or1k_restore_context");
818 /* read debug registers (starting from DMR1 register) */
819 retval
= du_core
->or1k_jtag_read_cpu(&or1k
->jtag
, OR1K_DMR1_CPU_REG_ADD
,
820 OR1K_DEBUG_REG_NUM
, debug_reg_list
);
821 if (retval
!= ERROR_OK
) {
822 LOG_ERROR("Error while reading debug registers");
826 /* Clear Debug Reason Register (DRR) */
827 debug_reg_list
[OR1K_DEBUG_REG_DRR
] = 0;
829 /* Clear watchpoint break generation in Debug Mode Register 2 (DMR2) */
830 debug_reg_list
[OR1K_DEBUG_REG_DMR2
] &= ~OR1K_DMR2_WGB
;
832 /* Set the single step trigger in Debug Mode Register 1 (DMR1) */
833 debug_reg_list
[OR1K_DEBUG_REG_DMR1
] |= OR1K_DMR1_ST
| OR1K_DMR1_BT
;
835 /* Clear the single step trigger in Debug Mode Register 1 (DMR1) */
836 debug_reg_list
[OR1K_DEBUG_REG_DMR1
] &= ~(OR1K_DMR1_ST
| OR1K_DMR1_BT
);
838 /* Set traps to be handled by the debug unit in the Debug Stop
839 Register (DSR). Check if we have any software breakpoints in
840 place before setting this value - the kernel, for instance,
841 relies on l.trap instructions not stalling the processor ! */
842 if (is_any_soft_breakpoint(target
) == true)
843 debug_reg_list
[OR1K_DEBUG_REG_DSR
] |= OR1K_DSR_TE
;
845 /* Write debug registers (starting from DMR1 register) */
846 retval
= du_core
->or1k_jtag_write_cpu(&or1k
->jtag
, OR1K_DMR1_CPU_REG_ADD
,
847 OR1K_DEBUG_REG_NUM
, debug_reg_list
);
848 if (retval
!= ERROR_OK
) {
849 LOG_ERROR("Error while writing back debug registers");
853 resume_pc
= buf_get_u32(or1k
->core_cache
->reg_list
[OR1K_REG_NPC
].value
,
856 /* The front-end may request us not to handle breakpoints */
857 if (handle_breakpoints
) {
858 /* Single step past breakpoint at current address */
859 breakpoint
= breakpoint_find(target
, resume_pc
);
861 LOG_DEBUG("Unset breakpoint at 0x%08" PRIx32
, breakpoint
->address
);
862 retval
= or1k_remove_breakpoint(target
, breakpoint
);
863 if (retval
!= ERROR_OK
)
869 retval
= du_core
->or1k_cpu_stall(&or1k
->jtag
, CPU_UNSTALL
);
870 if (retval
!= ERROR_OK
) {
871 LOG_ERROR("Error while unstalling the CPU");
876 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
878 target
->debug_reason
= DBG_REASON_NOTHALTED
;
880 /* Registers are now invalid */
881 register_cache_invalidate(or1k
->core_cache
);
883 if (!debug_execution
) {
884 target
->state
= TARGET_RUNNING
;
885 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
886 LOG_DEBUG("Target resumed at 0x%08" PRIx32
, resume_pc
);
888 target
->state
= TARGET_DEBUG_RUNNING
;
889 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
890 LOG_DEBUG("Target debug resumed at 0x%08" PRIx32
, resume_pc
);
896 static int or1k_resume(struct target
*target
, int current
,
897 uint32_t address
, int handle_breakpoints
, int debug_execution
)
899 return or1k_resume_or_step(target
, current
, address
,
905 static int or1k_step(struct target
*target
, int current
,
906 uint32_t address
, int handle_breakpoints
)
908 return or1k_resume_or_step(target
, current
, address
,
915 static int or1k_add_breakpoint(struct target
*target
,
916 struct breakpoint
*breakpoint
)
918 struct or1k_common
*or1k
= target_to_or1k(target
);
919 struct or1k_du
*du_core
= or1k_to_du(or1k
);
922 LOG_DEBUG("Adding breakpoint: addr 0x%08" PRIx32
", len %d, type %d, set: %d, id: %" PRId32
,
923 breakpoint
->address
, breakpoint
->length
, breakpoint
->type
,
924 breakpoint
->set
, breakpoint
->unique_id
);
926 /* Only support SW breakpoints for now. */
927 if (breakpoint
->type
== BKPT_HARD
)
928 LOG_ERROR("HW breakpoints not supported for now. Doing SW breakpoint.");
930 /* Read and save the instruction */
931 int retval
= du_core
->or1k_jtag_read_memory(&or1k
->jtag
,
936 if (retval
!= ERROR_OK
) {
937 LOG_ERROR("Error while reading the instruction at 0x%08" PRIx32
,
938 breakpoint
->address
);
942 if (breakpoint
->orig_instr
!= NULL
)
943 free(breakpoint
->orig_instr
);
945 breakpoint
->orig_instr
= malloc(breakpoint
->length
);
946 memcpy(breakpoint
->orig_instr
, &data
, breakpoint
->length
);
948 /* Sub in the OR1K trap instruction */
949 uint8_t or1k_trap_insn
[4];
950 target_buffer_set_u32(target
, or1k_trap_insn
, OR1K_TRAP_INSTR
);
951 retval
= du_core
->or1k_jtag_write_memory(&or1k
->jtag
,
957 if (retval
!= ERROR_OK
) {
958 LOG_ERROR("Error while writing OR1K_TRAP_INSTR at 0x%08" PRIx32
,
959 breakpoint
->address
);
963 /* invalidate instruction cache */
964 retval
= du_core
->or1k_jtag_write_cpu(&or1k
->jtag
,
965 OR1K_ICBIR_CPU_REG_ADD
, 1, &breakpoint
->address
);
966 if (retval
!= ERROR_OK
) {
967 LOG_ERROR("Error while invalidating the ICACHE");
974 static int or1k_remove_breakpoint(struct target
*target
,
975 struct breakpoint
*breakpoint
)
977 struct or1k_common
*or1k
= target_to_or1k(target
);
978 struct or1k_du
*du_core
= or1k_to_du(or1k
);
980 LOG_DEBUG("Removing breakpoint: addr 0x%08" PRIx32
", len %d, type %d, set: %d, id: %" PRId32
,
981 breakpoint
->address
, breakpoint
->length
, breakpoint
->type
,
982 breakpoint
->set
, breakpoint
->unique_id
);
984 /* Only support SW breakpoints for now. */
985 if (breakpoint
->type
== BKPT_HARD
)
986 LOG_ERROR("HW breakpoints not supported for now. Doing SW breakpoint.");
988 /* Replace the removed instruction */
989 int retval
= du_core
->or1k_jtag_write_memory(&or1k
->jtag
,
993 breakpoint
->orig_instr
);
995 if (retval
!= ERROR_OK
) {
996 LOG_ERROR("Error while writing back the instruction at 0x%08" PRIx32
,
997 breakpoint
->address
);
1001 /* invalidate instruction cache */
1002 retval
= du_core
->or1k_jtag_write_cpu(&or1k
->jtag
,
1003 OR1K_ICBIR_CPU_REG_ADD
, 1, &breakpoint
->address
);
1004 if (retval
!= ERROR_OK
) {
1005 LOG_ERROR("Error while invalidating the ICACHE");
1012 static int or1k_add_watchpoint(struct target
*target
,
1013 struct watchpoint
*watchpoint
)
1015 LOG_ERROR("%s: implement me", __func__
);
1019 static int or1k_remove_watchpoint(struct target
*target
,
1020 struct watchpoint
*watchpoint
)
1022 LOG_ERROR("%s: implement me", __func__
);
1026 static int or1k_read_memory(struct target
*target
, uint32_t address
,
1027 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1029 struct or1k_common
*or1k
= target_to_or1k(target
);
1030 struct or1k_du
*du_core
= or1k_to_du(or1k
);
1032 LOG_DEBUG("Read memory at 0x%08" PRIx32
", size: %" PRIu32
", count: 0x%08" PRIx32
, address
, size
, count
);
1034 if (target
->state
!= TARGET_HALTED
) {
1035 LOG_ERROR("Target not halted");
1036 return ERROR_TARGET_NOT_HALTED
;
1039 /* Sanitize arguments */
1040 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !buffer
) {
1041 LOG_ERROR("Bad arguments");
1042 return ERROR_COMMAND_SYNTAX_ERROR
;
1045 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
))) {
1046 LOG_ERROR("Can't handle unaligned memory access");
1047 return ERROR_TARGET_UNALIGNED_ACCESS
;
1050 return du_core
->or1k_jtag_read_memory(&or1k
->jtag
, address
, size
, count
, buffer
);
1053 static int or1k_write_memory(struct target
*target
, uint32_t address
,
1054 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1056 struct or1k_common
*or1k
= target_to_or1k(target
);
1057 struct or1k_du
*du_core
= or1k_to_du(or1k
);
1059 LOG_DEBUG("Write memory at 0x%08" PRIx32
", size: %" PRIu32
", count: 0x%08" PRIx32
, address
, size
, count
);
1061 if (target
->state
!= TARGET_HALTED
) {
1062 LOG_WARNING("Target not halted");
1063 return ERROR_TARGET_NOT_HALTED
;
1066 /* Sanitize arguments */
1067 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !buffer
) {
1068 LOG_ERROR("Bad arguments");
1069 return ERROR_COMMAND_SYNTAX_ERROR
;
1072 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
))) {
1073 LOG_ERROR("Can't handle unaligned memory access");
1074 return ERROR_TARGET_UNALIGNED_ACCESS
;
1077 return du_core
->or1k_jtag_write_memory(&or1k
->jtag
, address
, size
, count
, buffer
);
1080 static int or1k_init_target(struct command_context
*cmd_ctx
,
1081 struct target
*target
)
1083 struct or1k_common
*or1k
= target_to_or1k(target
);
1084 struct or1k_du
*du_core
= or1k_to_du(or1k
);
1085 struct or1k_jtag
*jtag
= &or1k
->jtag
;
1087 if (du_core
== NULL
) {
1088 LOG_ERROR("No debug unit selected");
1092 if (jtag
->tap_ip
== NULL
) {
1093 LOG_ERROR("No tap selected");
1097 or1k
->jtag
.tap
= target
->tap
;
1098 or1k
->jtag
.or1k_jtag_inited
= 0;
1099 or1k
->jtag
.or1k_jtag_module_selected
= -1;
1100 or1k
->jtag
.target
= target
;
1102 or1k_build_reg_cache(target
);
1107 static int or1k_target_create(struct target
*target
, Jim_Interp
*interp
)
1109 if (target
->tap
== NULL
)
1112 struct or1k_common
*or1k
= calloc(1, sizeof(struct or1k_common
));
1114 target
->arch_info
= or1k
;
1116 or1k_create_reg_list(target
);
1118 or1k_tap_vjtag_register();
1119 or1k_tap_xilinx_bscan_register();
1120 or1k_tap_mohor_register();
1122 or1k_du_adv_register();
1127 static int or1k_examine(struct target
*target
)
1129 struct or1k_common
*or1k
= target_to_or1k(target
);
1130 struct or1k_du
*du_core
= or1k_to_du(or1k
);
1132 if (!target_was_examined(target
)) {
1134 target_set_examined(target
);
1138 int retval
= du_core
->or1k_is_cpu_running(&or1k
->jtag
, &running
);
1139 if (retval
!= ERROR_OK
) {
1140 LOG_ERROR("Couldn't read the CPU state");
1144 target
->state
= TARGET_RUNNING
;
1146 LOG_DEBUG("Target is halted");
1148 /* This is the first time we examine the target,
1149 * it is stalled and we don't know why. Let's
1150 * assume this is because of a debug reason.
1152 if (target
->state
== TARGET_UNKNOWN
)
1153 target
->debug_reason
= DBG_REASON_DBGRQ
;
1155 target
->state
= TARGET_HALTED
;
1163 static int or1k_arch_state(struct target
*target
)
1168 static int or1k_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[],
1169 int *reg_list_size
, enum target_register_class reg_class
)
1171 struct or1k_common
*or1k
= target_to_or1k(target
);
1173 if (reg_class
== REG_CLASS_GENERAL
) {
1174 /* We will have this called whenever GDB connects. */
1175 int retval
= or1k_save_context(target
);
1176 if (retval
!= ERROR_OK
) {
1177 LOG_ERROR("Error while calling or1k_save_context");
1180 *reg_list_size
= OR1KNUMCOREREGS
;
1181 /* this is free()'d back in gdb_server.c's gdb_get_register_packet() */
1182 *reg_list
= malloc((*reg_list_size
) * sizeof(struct reg
*));
1184 for (int i
= 0; i
< OR1KNUMCOREREGS
; i
++)
1185 (*reg_list
)[i
] = &or1k
->core_cache
->reg_list
[i
];
1187 *reg_list_size
= or1k
->nb_regs
;
1188 *reg_list
= malloc((*reg_list_size
) * sizeof(struct reg
*));
1190 for (int i
= 0; i
< or1k
->nb_regs
; i
++)
1191 (*reg_list
)[i
] = &or1k
->core_cache
->reg_list
[i
];
1198 int or1k_get_gdb_fileio_info(struct target
*target
, struct gdb_fileio_info
*fileio_info
)
1203 static int or1k_checksum_memory(struct target
*target
, uint32_t address
,
1204 uint32_t count
, uint32_t *checksum
) {
1209 static int or1k_profiling(struct target
*target
, uint32_t *samples
,
1210 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
)
1212 struct timeval timeout
, now
;
1213 struct or1k_common
*or1k
= target_to_or1k(target
);
1214 struct or1k_du
*du_core
= or1k_to_du(or1k
);
1215 int retval
= ERROR_OK
;
1217 gettimeofday(&timeout
, NULL
);
1218 timeval_add_time(&timeout
, seconds
, 0);
1220 LOG_INFO("Starting or1k profiling. Sampling npc as fast as we can...");
1222 /* Make sure the target is running */
1223 target_poll(target
);
1224 if (target
->state
== TARGET_HALTED
)
1225 retval
= target_resume(target
, 1, 0, 0, 0);
1227 if (retval
!= ERROR_OK
) {
1228 LOG_ERROR("Error while resuming target");
1232 uint32_t sample_count
= 0;
1236 retval
= du_core
->or1k_jtag_read_cpu(&or1k
->jtag
, GROUP0
+ 16 /* NPC */, 1, ®_value
);
1237 if (retval
!= ERROR_OK
) {
1238 LOG_ERROR("Error while reading NPC");
1242 samples
[sample_count
++] = reg_value
;
1244 gettimeofday(&now
, NULL
);
1245 if ((sample_count
>= max_num_samples
) ||
1246 ((now
.tv_sec
>= timeout
.tv_sec
) && (now
.tv_usec
>= timeout
.tv_usec
))) {
1247 LOG_INFO("Profiling completed. %" PRIu32
" samples.", sample_count
);
1252 *num_samples
= sample_count
;
1256 COMMAND_HANDLER(or1k_tap_select_command_handler
)
1258 struct target
*target
= get_current_target(CMD_CTX
);
1259 struct or1k_common
*or1k
= target_to_or1k(target
);
1260 struct or1k_jtag
*jtag
= &or1k
->jtag
;
1261 struct or1k_tap_ip
*or1k_tap
;
1264 return ERROR_COMMAND_SYNTAX_ERROR
;
1266 list_for_each_entry(or1k_tap
, &tap_list
, list
) {
1267 if (or1k_tap
->name
) {
1268 if (!strcmp(CMD_ARGV
[0], or1k_tap
->name
)) {
1269 jtag
->tap_ip
= or1k_tap
;
1270 LOG_INFO("%s tap selected", or1k_tap
->name
);
1276 LOG_ERROR("%s unknown, no tap selected", CMD_ARGV
[0]);
1277 return ERROR_COMMAND_SYNTAX_ERROR
;
1280 COMMAND_HANDLER(or1k_tap_list_command_handler
)
1282 struct or1k_tap_ip
*or1k_tap
;
1285 return ERROR_COMMAND_SYNTAX_ERROR
;
1287 list_for_each_entry(or1k_tap
, &tap_list
, list
) {
1289 command_print(CMD_CTX
, "%s", or1k_tap
->name
);
1295 COMMAND_HANDLER(or1k_du_select_command_handler
)
1297 struct target
*target
= get_current_target(CMD_CTX
);
1298 struct or1k_common
*or1k
= target_to_or1k(target
);
1299 struct or1k_jtag
*jtag
= &or1k
->jtag
;
1300 struct or1k_du
*or1k_du
;
1303 return ERROR_COMMAND_SYNTAX_ERROR
;
1305 list_for_each_entry(or1k_du
, &du_list
, list
) {
1306 if (or1k_du
->name
) {
1307 if (!strcmp(CMD_ARGV
[0], or1k_du
->name
)) {
1308 jtag
->du_core
= or1k_du
;
1309 LOG_INFO("%s debug unit selected", or1k_du
->name
);
1311 if (CMD_ARGC
== 2) {
1313 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], options
);
1314 or1k_du
->options
= options
;
1315 LOG_INFO("Option %x is passed to %s debug unit"
1316 , options
, or1k_du
->name
);
1324 LOG_ERROR("%s unknown, no debug unit selected", CMD_ARGV
[0]);
1325 return ERROR_COMMAND_SYNTAX_ERROR
;
1328 COMMAND_HANDLER(or1k_du_list_command_handler
)
1330 struct or1k_du
*or1k_du
;
1333 return ERROR_COMMAND_SYNTAX_ERROR
;
1335 list_for_each_entry(or1k_du
, &du_list
, list
) {
1337 command_print(CMD_CTX
, "%s", or1k_du
->name
);
1343 COMMAND_HANDLER(or1k_addreg_command_handler
)
1345 struct target
*target
= get_current_target(CMD_CTX
);
1346 struct or1k_core_reg new_reg
;
1349 return ERROR_COMMAND_SYNTAX_ERROR
;
1351 new_reg
.target
= NULL
;
1352 new_reg
.or1k_common
= NULL
;
1355 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], addr
);
1357 new_reg
.name
= strdup(CMD_ARGV
[0]);
1358 new_reg
.spr_num
= addr
;
1359 new_reg
.feature
= strdup(CMD_ARGV
[2]);
1360 new_reg
.group
= strdup(CMD_ARGV
[3]);
1362 or1k_add_reg(target
, &new_reg
);
1364 LOG_DEBUG("Add reg \"%s\" @ 0x%08" PRIx32
", group \"%s\", feature \"%s\"",
1365 new_reg
.name
, addr
, new_reg
.group
, new_reg
.feature
);
1370 static const struct command_registration or1k_hw_ip_command_handlers
[] = {
1373 .handler
= or1k_tap_select_command_handler
,
1374 .mode
= COMMAND_ANY
,
1375 .usage
= "tap_select name",
1376 .help
= "Select the TAP core to use",
1380 .handler
= or1k_tap_list_command_handler
,
1381 .mode
= COMMAND_ANY
,
1382 .usage
= "tap_list",
1383 .help
= "Display available TAP core",
1387 .handler
= or1k_du_select_command_handler
,
1388 .mode
= COMMAND_ANY
,
1389 .usage
= "du_select name",
1390 .help
= "Select the Debug Unit core to use",
1394 .handler
= or1k_du_list_command_handler
,
1395 .mode
= COMMAND_ANY
,
1396 .usage
= "select_tap name",
1397 .help
= "Display available Debug Unit core",
1399 COMMAND_REGISTRATION_DONE
1402 static const struct command_registration or1k_reg_command_handlers
[] = {
1405 .handler
= or1k_addreg_command_handler
,
1406 .mode
= COMMAND_ANY
,
1407 .usage
= "addreg name addr feature group",
1408 .help
= "Add a register to the register list",
1410 COMMAND_REGISTRATION_DONE
1413 static const struct command_registration or1k_command_handlers
[] = {
1415 .chain
= or1k_reg_command_handlers
,
1418 .chain
= or1k_hw_ip_command_handlers
,
1420 COMMAND_REGISTRATION_DONE
1424 struct target_type or1k_target
= {
1428 .arch_state
= or1k_arch_state
,
1430 .target_request_data
= NULL
,
1433 .resume
= or1k_resume
,
1436 .assert_reset
= or1k_assert_reset
,
1437 .deassert_reset
= or1k_deassert_reset
,
1438 .soft_reset_halt
= or1k_soft_reset_halt
,
1440 .get_gdb_reg_list
= or1k_get_gdb_reg_list
,
1442 .read_memory
= or1k_read_memory
,
1443 .write_memory
= or1k_write_memory
,
1444 .checksum_memory
= or1k_checksum_memory
,
1446 .commands
= or1k_command_handlers
,
1447 .add_breakpoint
= or1k_add_breakpoint
,
1448 .remove_breakpoint
= or1k_remove_breakpoint
,
1449 .add_watchpoint
= or1k_add_watchpoint
,
1450 .remove_watchpoint
= or1k_remove_watchpoint
,
1452 .target_create
= or1k_target_create
,
1453 .init_target
= or1k_init_target
,
1454 .examine
= or1k_examine
,
1456 .get_gdb_fileio_info
= or1k_get_gdb_fileio_info
,
1458 .profiling
= or1k_profiling
,
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