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nds32: add new target type nds32_v2, nds32_v3, nds32_v3m
[openocd.git] / src / target / nds32_reg.h
1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
20 #ifndef __NDS32_REG_H__
21 #define __NDS32_REG_H__
22
23 #define SRIDX(a, b, c) ((a << 7) | (b << 3) | c)
24 #define NDS32_REGISTER_DISABLE (0x0)
25
26 enum nds32_reg_number_s {
27 R0 = 0, /* general registers */
28 R1,
29 R2,
30 R3,
31 R4,
32 R5,
33 R6,
34 R7,
35 R8,
36 R9,
37 R10,
38 R11,
39 R12,
40 R13,
41 R14,
42 R15,
43 R16,
44 R17,
45 R18,
46 R19,
47 R20,
48 R21,
49 R22,
50 R23,
51 R24,
52 R25,
53 R26,
54 R27,
55 R28,
56 R29,
57 R30,
58 R31,
59 PC,
60 D0LO,
61 D0HI,
62 D1LO,
63 D1HI,
64 ITB,
65 IFC_LP,
66 CR0, /* system registers */
67 CR1,
68 CR2,
69 CR3,
70 CR4,
71 CR5,
72 CR6,
73 IR0,
74 IR1,
75 IR2,
76 IR3,
77 IR4,
78 IR5,
79 IR6,
80 IR7,
81 IR8,
82 IR9,
83 IR10,
84 IR11,
85 IR12,
86 IR13,
87 IR14,
88 IR15,
89 IR16,
90 IR17,
91 IR18,
92 IR19,
93 IR20,
94 IR21,
95 IR22,
96 IR23,
97 IR24,
98 IR25,
99 IR26,
100 IR27,
101 IR28,
102 IR29,
103 IR30,
104 MR0,
105 MR1,
106 MR2,
107 MR3,
108 MR4,
109 MR5,
110 MR6,
111 MR7,
112 MR8,
113 MR9,
114 MR10,
115 MR11,
116 DR0,
117 DR1,
118 DR2,
119 DR3,
120 DR4,
121 DR5,
122 DR6,
123 DR7,
124 DR8,
125 DR9,
126 DR10,
127 DR11,
128 DR12,
129 DR13,
130 DR14,
131 DR15,
132 DR16,
133 DR17,
134 DR18,
135 DR19,
136 DR20,
137 DR21,
138 DR22,
139 DR23,
140 DR24,
141 DR25,
142 DR26,
143 DR27,
144 DR28,
145 DR29,
146 DR30,
147 DR31,
148 DR32,
149 DR33,
150 DR34,
151 DR35,
152 DR36,
153 DR37,
154 DR38,
155 DR39,
156 DR40,
157 DR41,
158 DR42,
159 DR43,
160 DR44,
161 DR45,
162 DR46,
163 DR47,
164 DR48,
165 PFR0,
166 PFR1,
167 PFR2,
168 PFR3,
169 DMAR0,
170 DMAR1,
171 DMAR2,
172 DMAR3,
173 DMAR4,
174 DMAR5,
175 DMAR6,
176 DMAR7,
177 DMAR8,
178 DMAR9,
179 DMAR10,
180 RACR,
181 FUCPR,
182 IDR0,
183 IDR1,
184 SECUR0,
185 D0L24, /* audio registers */
186 D1L24,
187 I0,
188 I1,
189 I2,
190 I3,
191 I4,
192 I5,
193 I6,
194 I7,
195 M1,
196 M2,
197 M3,
198 M5,
199 M6,
200 M7,
201 MOD,
202 LBE,
203 LE,
204 LC,
205 ADM_VBASE,
206 SHFT_CTL0,
207 SHFT_CTL1,
208 CB_CTL,
209 CBB0,
210 CBB1,
211 CBB2,
212 CBB3,
213 CBE0,
214 CBE1,
215 CBE2,
216 CBE3,
217 FPCSR, /* fpu */
218 FPCFG,
219 FS0,
220 FS1,
221 FS2,
222 FS3,
223 FS4,
224 FS5,
225 FS6,
226 FS7,
227 FS8,
228 FS9,
229 FS10,
230 FS11,
231 FS12,
232 FS13,
233 FS14,
234 FS15,
235 FS16,
236 FS17,
237 FS18,
238 FS19,
239 FS20,
240 FS21,
241 FS22,
242 FS23,
243 FS24,
244 FS25,
245 FS26,
246 FS27,
247 FS28,
248 FS29,
249 FS30,
250 FS31,
251 FD0,
252 FD1,
253 FD2,
254 FD3,
255 FD4,
256 FD5,
257 FD6,
258 FD7,
259 FD8,
260 FD9,
261 FD10,
262 FD11,
263 FD12,
264 FD13,
265 FD14,
266 FD15,
267 FD16,
268 FD17,
269 FD18,
270 FD19,
271 FD20,
272 FD21,
273 FD22,
274 FD23,
275 FD24,
276 FD25,
277 FD26,
278 FD27,
279 FD28,
280 FD29,
281 FD30,
282 FD31,
283
284 TOTAL_REG_NUM,
285 };
286
287 enum nds32_reg_type_s {
288 NDS32_REG_TYPE_GPR = 0,
289 NDS32_REG_TYPE_SPR,
290 NDS32_REG_TYPE_CR,
291 NDS32_REG_TYPE_IR,
292 NDS32_REG_TYPE_MR,
293 NDS32_REG_TYPE_DR,
294 NDS32_REG_TYPE_PFR,
295 NDS32_REG_TYPE_DMAR,
296 NDS32_REG_TYPE_RACR,
297 NDS32_REG_TYPE_IDR,
298 NDS32_REG_TYPE_AUMR,
299 NDS32_REG_TYPE_SECURE,
300 NDS32_REG_TYPE_FPU,
301 };
302
303 struct nds32_reg_s {
304 const char *simple_mnemonic;
305 const char *symbolic_mnemonic;
306 uint32_t sr_index;
307 enum nds32_reg_type_s type;
308 uint8_t size;
309 };
310
311 struct nds32_reg_exception_s {
312 uint32_t reg_num;
313 uint32_t ex_value_bit_pos;
314 uint32_t ex_value_mask;
315 uint32_t ex_value;
316 };
317
318 void nds32_reg_init(void);
319 uint32_t nds32_reg_sr_index(uint32_t number);
320 enum nds32_reg_type_s nds32_reg_type(uint32_t number);
321 uint8_t nds32_reg_size(uint32_t number);
322 const char *nds32_reg_simple_name(uint32_t number);
323 const char *nds32_reg_symbolic_name(uint32_t number);
324 bool nds32_reg_exception(uint32_t number, uint32_t value);
325
326 #endif
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