Code Review / openocd.git / blob
? search:


3f243700f0cedaee746fb821c73b80e68bab827d
[openocd.git] / src / target / nds32_cmd.c
1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include <helper/command.h>
26 #include "nds32.h"
27 #include "nds32_aice.h"
28 #include "nds32_disassembler.h"
29
30 extern struct nds32_edm_operation nds32_edm_ops[NDS32_EDM_OPERATION_MAX_NUM];
31 extern uint32_t nds32_edm_ops_num;
32
33 static const char *const NDS_MEMORY_ACCESS_NAME[] = {
34 "BUS",
35 "CPU",
36 };
37
38 static const char *const NDS_MEMORY_SELECT_NAME[] = {
39 "AUTO",
40 "MEM",
41 "ILM",
42 "DLM",
43 };
44
45 COMMAND_HANDLER(handle_nds32_dssim_command)
46 {
47 struct target *target = get_current_target(CMD_CTX);
48 struct nds32 *nds32 = target_to_nds32(target);
49
50 if (!is_nds32(nds32)) {
51 command_print(CMD_CTX, "current target isn't an Andes core");
52 return ERROR_FAIL;
53 }
54
55 if (CMD_ARGC > 0) {
56 if (strcmp(CMD_ARGV[0], "on") == 0)
57 nds32->step_isr_enable = true;
58 if (strcmp(CMD_ARGV[0], "off") == 0)
59 nds32->step_isr_enable = false;
60 }
61
62 command_print(CMD_CTX, "$INT_MASK.DSSIM: %d", nds32->step_isr_enable);
63
64 return ERROR_OK;
65 }
66
67 COMMAND_HANDLER(handle_nds32_memory_access_command)
68 {
69 struct target *target = get_current_target(CMD_CTX);
70 struct nds32 *nds32 = target_to_nds32(target);
71 struct aice_port_s *aice = target_to_aice(target);
72
73 if (!is_nds32(nds32)) {
74 command_print(CMD_CTX, "current target isn't an Andes core");
75 return ERROR_FAIL;
76 }
77
78 if (CMD_ARGC > 0) {
79
80 /* If target has no cache, always use BUS mode
81 * to access memory. */
82 struct nds32_memory *memory = &(nds32->memory);
83
84 if (memory->dcache.line_size == 0) {
85 /* There is no Dcache. */
86 nds32->memory.access_channel = NDS_MEMORY_ACC_BUS;
87 } else if (memory->dcache.enable == false) {
88 /* Dcache is disabled. */
89 nds32->memory.access_channel = NDS_MEMORY_ACC_BUS;
90 } else {
91 /* There is Dcache and Dcache is enabled. */
92 if (strcmp(CMD_ARGV[0], "bus") == 0)
93 nds32->memory.access_channel = NDS_MEMORY_ACC_BUS;
94 else if (strcmp(CMD_ARGV[0], "cpu") == 0)
95 nds32->memory.access_channel = NDS_MEMORY_ACC_CPU;
96 else /* default access channel is NDS_MEMORY_ACC_CPU */
97 nds32->memory.access_channel = NDS_MEMORY_ACC_CPU;
98 }
99
100 aice_memory_access(aice, nds32->memory.access_channel);
101 }
102
103 command_print(CMD_CTX, "memory access channel: %s",
104 NDS_MEMORY_ACCESS_NAME[nds32->memory.access_channel]);
105
106 return ERROR_OK;
107 }
108
109 COMMAND_HANDLER(handle_nds32_memory_mode_command)
110 {
111 struct target *target = get_current_target(CMD_CTX);
112 struct nds32 *nds32 = target_to_nds32(target);
113 struct aice_port_s *aice = target_to_aice(target);
114
115 if (!is_nds32(nds32)) {
116 command_print(CMD_CTX, "current target isn't an Andes core");
117 return ERROR_FAIL;
118 }
119
120 if (CMD_ARGC > 0) {
121
122 if (nds32->edm.access_control == false) {
123 command_print(CMD_CTX, "Target does not support ACC_CTL. "
124 "Set memory mode to MEMORY");
125 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
126 } else if (nds32->edm.direct_access_local_memory == false) {
127 command_print(CMD_CTX, "Target does not support direct access "
128 "local memory. Set memory mode to MEMORY");
129 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
130
131 /* set to ACC_CTL */
132 aice_memory_mode(aice, nds32->memory.mode);
133 } else {
134 if (strcmp(CMD_ARGV[0], "auto") == 0) {
135 nds32->memory.mode = NDS_MEMORY_SELECT_AUTO;
136 } else if (strcmp(CMD_ARGV[0], "mem") == 0) {
137 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
138 } else if (strcmp(CMD_ARGV[0], "ilm") == 0) {
139 if (nds32->memory.ilm_base == 0)
140 command_print(CMD_CTX, "Target does not support ILM");
141 else
142 nds32->memory.mode = NDS_MEMORY_SELECT_ILM;
143 } else if (strcmp(CMD_ARGV[0], "dlm") == 0) {
144 if (nds32->memory.dlm_base == 0)
145 command_print(CMD_CTX, "Target does not support DLM");
146 else
147 nds32->memory.mode = NDS_MEMORY_SELECT_DLM;
148 }
149
150 /* set to ACC_CTL */
151 aice_memory_mode(aice, nds32->memory.mode);
152 }
153 }
154
155 command_print(CMD_CTX, "memory mode: %s",
156 NDS_MEMORY_SELECT_NAME[nds32->memory.mode]);
157
158 return ERROR_OK;
159 }
160
161 COMMAND_HANDLER(handle_nds32_cache_command)
162 {
163 struct target *target = get_current_target(CMD_CTX);
164 struct nds32 *nds32 = target_to_nds32(target);
165 struct aice_port_s *aice = target_to_aice(target);
166 struct nds32_cache *icache = &(nds32->memory.icache);
167 struct nds32_cache *dcache = &(nds32->memory.dcache);
168 int result;
169
170 if (!is_nds32(nds32)) {
171 command_print(CMD_CTX, "current target isn't an Andes core");
172 return ERROR_FAIL;
173 }
174
175 if (CMD_ARGC > 0) {
176
177 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
178 if ((dcache->line_size != 0) && (dcache->enable == true)) {
179 /* D$ write back */
180 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
181 if (result != ERROR_OK) {
182 command_print(CMD_CTX, "Write back data cache...failed");
183 return result;
184 }
185
186 command_print(CMD_CTX, "Write back data cache...done");
187
188 /* D$ invalidate */
189 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
190 if (result != ERROR_OK) {
191 command_print(CMD_CTX, "Invalidate data cache...failed");
192 return result;
193 }
194
195 command_print(CMD_CTX, "Invalidate data cache...done");
196 } else {
197 if (dcache->line_size == 0)
198 command_print(CMD_CTX, "No data cache");
199 else
200 command_print(CMD_CTX, "Data cache disabled");
201 }
202
203 if ((icache->line_size != 0) && (icache->enable == true)) {
204 /* I$ invalidate */
205 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
206 if (result != ERROR_OK) {
207 command_print(CMD_CTX, "Invalidate instruction cache...failed");
208 return result;
209 }
210
211 command_print(CMD_CTX, "Invalidate instruction cache...done");
212 } else {
213 if (icache->line_size == 0)
214 command_print(CMD_CTX, "No instruction cache");
215 else
216 command_print(CMD_CTX, "Instruction cache disabled");
217 }
218 } else
219 command_print(CMD_CTX, "No valid parameter");
220 }
221
222 return ERROR_OK;
223 }
224
225 COMMAND_HANDLER(handle_nds32_icache_command)
226 {
227 struct target *target = get_current_target(CMD_CTX);
228 struct nds32 *nds32 = target_to_nds32(target);
229 struct aice_port_s *aice = target_to_aice(target);
230 struct nds32_cache *icache = &(nds32->memory.icache);
231 int result;
232
233 if (!is_nds32(nds32)) {
234 command_print(CMD_CTX, "current target isn't an Andes core");
235 return ERROR_FAIL;
236 }
237
238 if (CMD_ARGC > 0) {
239
240 if (icache->line_size == 0) {
241 command_print(CMD_CTX, "No instruction cache");
242 return ERROR_OK;
243 }
244
245 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
246 if (icache->enable == true) {
247 /* I$ invalidate */
248 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
249 if (result != ERROR_OK) {
250 command_print(CMD_CTX, "Invalidate instruction cache...failed");
251 return result;
252 }
253
254 command_print(CMD_CTX, "Invalidate instruction cache...done");
255 } else {
256 command_print(CMD_CTX, "Instruction cache disabled");
257 }
258 } else if (strcmp(CMD_ARGV[0], "enable") == 0) {
259 uint32_t value;
260 nds32_get_mapped_reg(nds32, IR8, &value);
261 nds32_set_mapped_reg(nds32, IR8, value | 0x1);
262 } else if (strcmp(CMD_ARGV[0], "disable") == 0) {
263 uint32_t value;
264 nds32_get_mapped_reg(nds32, IR8, &value);
265 nds32_set_mapped_reg(nds32, IR8, value & ~0x1);
266 } else if (strcmp(CMD_ARGV[0], "dump") == 0) {
267 /* TODO: dump cache content */
268 } else {
269 command_print(CMD_CTX, "No valid parameter");
270 }
271 }
272
273 return ERROR_OK;
274 }
275
276 COMMAND_HANDLER(handle_nds32_dcache_command)
277 {
278 struct target *target = get_current_target(CMD_CTX);
279 struct nds32 *nds32 = target_to_nds32(target);
280 struct aice_port_s *aice = target_to_aice(target);
281 struct nds32_cache *dcache = &(nds32->memory.dcache);
282 int result;
283
284 if (!is_nds32(nds32)) {
285 command_print(CMD_CTX, "current target isn't an Andes core");
286 return ERROR_FAIL;
287 }
288
289 if (CMD_ARGC > 0) {
290
291 if (dcache->line_size == 0) {
292 command_print(CMD_CTX, "No data cache");
293 return ERROR_OK;
294 }
295
296 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
297 if (dcache->enable == true) {
298 /* D$ write back */
299 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
300 if (result != ERROR_OK) {
301 command_print(CMD_CTX, "Write back data cache...failed");
302 return result;
303 }
304
305 command_print(CMD_CTX, "Write back data cache...done");
306
307 /* D$ invalidate */
308 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
309 if (result != ERROR_OK) {
310 command_print(CMD_CTX, "Invalidate data cache...failed");
311 return result;
312 }
313
314 command_print(CMD_CTX, "Invalidate data cache...done");
315 } else {
316 command_print(CMD_CTX, "Data cache disabled");
317 }
318 } else if (strcmp(CMD_ARGV[0], "enable") == 0) {
319 uint32_t value;
320 nds32_get_mapped_reg(nds32, IR8, &value);
321 nds32_set_mapped_reg(nds32, IR8, value | 0x2);
322 } else if (strcmp(CMD_ARGV[0], "disable") == 0) {
323 uint32_t value;
324 nds32_get_mapped_reg(nds32, IR8, &value);
325 nds32_set_mapped_reg(nds32, IR8, value & ~0x2);
326 } else if (strcmp(CMD_ARGV[0], "dump") == 0) {
327 /* TODO: dump cache content */
328 } else {
329 command_print(CMD_CTX, "No valid parameter");
330 }
331 }
332
333 return ERROR_OK;
334 }
335
336 COMMAND_HANDLER(handle_nds32_auto_break_command)
337 {
338 struct target *target = get_current_target(CMD_CTX);
339 struct nds32 *nds32 = target_to_nds32(target);
340
341 if (!is_nds32(nds32)) {
342 command_print(CMD_CTX, "current target isn't an Andes core");
343 return ERROR_FAIL;
344 }
345
346 if (CMD_ARGC > 0) {
347 if (strcmp(CMD_ARGV[0], "on") == 0)
348 nds32->auto_convert_hw_bp = true;
349 if (strcmp(CMD_ARGV[0], "off") == 0)
350 nds32->auto_convert_hw_bp = false;
351 }
352
353 if (nds32->auto_convert_hw_bp)
354 command_print(CMD_CTX, "convert sw break to hw break on ROM: on");
355 else
356 command_print(CMD_CTX, "convert sw break to hw break on ROM: off");
357
358 return ERROR_OK;
359 }
360
361 COMMAND_HANDLER(handle_nds32_virtual_hosting_command)
362 {
363 struct target *target = get_current_target(CMD_CTX);
364 struct nds32 *nds32 = target_to_nds32(target);
365
366 if (!is_nds32(nds32)) {
367 command_print(CMD_CTX, "current target isn't an Andes core");
368 return ERROR_FAIL;
369 }
370
371 if (CMD_ARGC > 0) {
372 if (strcmp(CMD_ARGV[0], "on") == 0)
373 nds32->virtual_hosting = true;
374 if (strcmp(CMD_ARGV[0], "off") == 0)
375 nds32->virtual_hosting = false;
376 }
377
378 if (nds32->virtual_hosting)
379 LOG_INFO("virtual hosting: on");
380 else
381 LOG_INFO("virtual hosting: off");
382
383 return ERROR_OK;
384 }
385
386 COMMAND_HANDLER(handle_nds32_global_stop_command)
387 {
388 struct target *target = get_current_target(CMD_CTX);
389 struct nds32 *nds32 = target_to_nds32(target);
390
391 if (!is_nds32(nds32)) {
392 command_print(CMD_CTX, "current target isn't an Andes core");
393 return ERROR_FAIL;
394 }
395
396 if (CMD_ARGC > 0) {
397 if (strcmp(CMD_ARGV[0], "on") == 0)
398 nds32->global_stop = true;
399 if (strcmp(CMD_ARGV[0], "off") == 0)
400 nds32->global_stop = false;
401 }
402
403 if (nds32->global_stop)
404 LOG_INFO("global stop: on");
405 else
406 LOG_INFO("global stop: off");
407
408 return ERROR_OK;
409 }
410
411 COMMAND_HANDLER(handle_nds32_soft_reset_halt_command)
412 {
413 struct target *target = get_current_target(CMD_CTX);
414 struct nds32 *nds32 = target_to_nds32(target);
415
416 if (!is_nds32(nds32)) {
417 command_print(CMD_CTX, "current target isn't an Andes core");
418 return ERROR_FAIL;
419 }
420
421 if (CMD_ARGC > 0) {
422 if (strcmp(CMD_ARGV[0], "on") == 0)
423 nds32->soft_reset_halt = true;
424 if (strcmp(CMD_ARGV[0], "off") == 0)
425 nds32->soft_reset_halt = false;
426 }
427
428 if (nds32->soft_reset_halt)
429 LOG_INFO("soft-reset-halt: on");
430 else
431 LOG_INFO("soft-reset-halt: off");
432
433 return ERROR_OK;
434 }
435
436 COMMAND_HANDLER(handle_nds32_boot_time_command)
437 {
438 struct target *target = get_current_target(CMD_CTX);
439 struct nds32 *nds32 = target_to_nds32(target);
440
441 if (!is_nds32(nds32)) {
442 command_print(CMD_CTX, "current target isn't an Andes core");
443 return ERROR_FAIL;
444 }
445
446 if (CMD_ARGC > 0)
447 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], nds32->boot_time);
448
449 return ERROR_OK;
450 }
451
452 COMMAND_HANDLER(handle_nds32_login_edm_passcode_command)
453 {
454 struct target *target = get_current_target(CMD_CTX);
455 struct nds32 *nds32 = target_to_nds32(target);
456
457 if (!is_nds32(nds32)) {
458 command_print(CMD_CTX, "current target isn't an Andes core");
459 return ERROR_FAIL;
460 }
461
462 nds32->edm_passcode = strdup(CMD_ARGV[0]);
463
464 LOG_INFO("set EDM passcode: %s", nds32->edm_passcode);
465
466 return ERROR_OK;
467 }
468
469 COMMAND_HANDLER(handle_nds32_login_edm_operation_command)
470 {
471 struct target *target = get_current_target(CMD_CTX);
472 struct nds32 *nds32 = target_to_nds32(target);
473
474 if (!is_nds32(nds32)) {
475 command_print(CMD_CTX, "current target isn't an Andes core");
476 return ERROR_FAIL;
477 }
478
479 if (CMD_ARGC > 1) {
480
481 uint32_t misc_reg_no;
482 uint32_t data;
483
484 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], misc_reg_no);
485 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], data);
486
487 if (nds32_edm_ops_num >= NDS32_EDM_OPERATION_MAX_NUM)
488 return ERROR_FAIL;
489
490 /* Just save the operation. Execute it in nds32_login() */
491 nds32_edm_ops[nds32_edm_ops_num].reg_no = misc_reg_no;
492 nds32_edm_ops[nds32_edm_ops_num].value = data;
493 nds32_edm_ops_num++;
494 } else
495 return ERROR_FAIL;
496
497 return ERROR_OK;
498 }
499
500 COMMAND_HANDLER(handle_nds32_reset_halt_as_init_command)
501 {
502 struct target *target = get_current_target(CMD_CTX);
503 struct nds32 *nds32 = target_to_nds32(target);
504
505 if (!is_nds32(nds32)) {
506 command_print(CMD_CTX, "current target isn't an Andes core");
507 return ERROR_FAIL;
508 }
509
510 if (CMD_ARGC > 0) {
511 if (strcmp(CMD_ARGV[0], "on") == 0)
512 nds32->reset_halt_as_examine = true;
513 if (strcmp(CMD_ARGV[0], "off") == 0)
514 nds32->reset_halt_as_examine = false;
515 }
516
517 return ERROR_OK;
518 }
519
520 COMMAND_HANDLER(handle_nds32_keep_target_edm_ctl_command)
521 {
522 struct target *target = get_current_target(CMD_CTX);
523 struct nds32 *nds32 = target_to_nds32(target);
524
525 if (!is_nds32(nds32)) {
526 command_print(CMD_CTX, "current target isn't an Andes core");
527 return ERROR_FAIL;
528 }
529
530 if (CMD_ARGC > 0) {
531 if (strcmp(CMD_ARGV[0], "on") == 0)
532 nds32->keep_target_edm_ctl = true;
533 if (strcmp(CMD_ARGV[0], "off") == 0)
534 nds32->keep_target_edm_ctl = false;
535 }
536
537 return ERROR_OK;
538 }
539
540 COMMAND_HANDLER(handle_nds32_decode_command)
541 {
542 struct target *target = get_current_target(CMD_CTX);
543 struct nds32 *nds32 = target_to_nds32(target);
544
545 if (!is_nds32(nds32)) {
546 command_print(CMD_CTX, "current target isn't an Andes core");
547 return ERROR_FAIL;
548 }
549
550 if (CMD_ARGC > 1) {
551
552 uint32_t addr;
553 uint32_t insn_count;
554 uint32_t opcode;
555 uint32_t read_addr;
556 uint32_t i;
557 struct nds32_instruction instruction;
558
559 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr);
560 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], insn_count);
561
562 read_addr = addr;
563 i = 0;
564 while (i < insn_count) {
565 if (ERROR_OK != nds32_read_opcode(nds32, read_addr, &opcode))
566 return ERROR_FAIL;
567 if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode,
568 read_addr, &instruction))
569 return ERROR_FAIL;
570
571 command_print(CMD_CTX, "%s", instruction.text);
572
573 read_addr += instruction.instruction_size;
574 i++;
575 }
576 } else if (CMD_ARGC == 1) {
577
578 uint32_t addr;
579 uint32_t opcode;
580 struct nds32_instruction instruction;
581
582 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr);
583
584 if (ERROR_OK != nds32_read_opcode(nds32, addr, &opcode))
585 return ERROR_FAIL;
586 if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode, addr, &instruction))
587 return ERROR_FAIL;
588
589 command_print(CMD_CTX, "%s", instruction.text);
590 } else
591 return ERROR_FAIL;
592
593 return ERROR_OK;
594 }
595
596 COMMAND_HANDLER(handle_nds32_word_access_mem_command)
597 {
598 struct target *target = get_current_target(CMD_CTX);
599 struct nds32 *nds32 = target_to_nds32(target);
600
601 if (!is_nds32(nds32)) {
602 command_print(CMD_CTX, "current target isn't an Andes core");
603 return ERROR_FAIL;
604 }
605
606 if (CMD_ARGC > 0) {
607 if (strcmp(CMD_ARGV[0], "on") == 0)
608 nds32->word_access_mem = true;
609 if (strcmp(CMD_ARGV[0], "off") == 0)
610 nds32->word_access_mem = false;
611 }
612
613 return ERROR_OK;
614 }
615
616 COMMAND_HANDLER(handle_nds32_query_target_command)
617 {
618 struct target *target = get_current_target(CMD_CTX);
619 struct nds32 *nds32 = target_to_nds32(target);
620
621 if (!is_nds32(nds32)) {
622 command_print(CMD_CTX, "current target isn't an Andes core");
623 return ERROR_FAIL;
624 }
625
626 command_print(CMD_CTX, "OCD");
627
628 return ERROR_OK;
629 }
630
631 COMMAND_HANDLER(handle_nds32_query_endian_command)
632 {
633 struct target *target = get_current_target(CMD_CTX);
634 struct nds32 *nds32 = target_to_nds32(target);
635
636 if (!is_nds32(nds32)) {
637 command_print(CMD_CTX, "current target isn't an Andes core");
638 return ERROR_FAIL;
639 }
640
641 uint32_t value_psw;
642 nds32_get_mapped_reg(nds32, IR0, &value_psw);
643
644 if (value_psw & 0x20)
645 command_print(CMD_CTX, "BE");
646 else
647 command_print(CMD_CTX, "LE");
648
649 return ERROR_OK;
650 }
651
652 COMMAND_HANDLER(handle_nds32_query_cpuid_command)
653 {
654 struct target *target = get_current_target(CMD_CTX);
655 struct nds32 *nds32 = target_to_nds32(target);
656
657 if (!is_nds32(nds32)) {
658 command_print(CMD_CTX, "current target isn't an Andes core");
659 return ERROR_FAIL;
660 }
661
662 command_print(CMD_CTX, "CPUID: %s", target_name(target));
663
664 return ERROR_OK;
665 }
666
667 static int jim_nds32_bulk_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
668 {
669 const char *cmd_name = Jim_GetString(argv[0], NULL);
670
671 Jim_GetOptInfo goi;
672 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
673
674 if (goi.argc < 3) {
675 Jim_SetResultFormatted(goi.interp,
676 "usage: %s <address> <count> <data>", cmd_name);
677 return JIM_ERR;
678 }
679
680 int e;
681 jim_wide address;
682 e = Jim_GetOpt_Wide(&goi, &address);
683 if (e != JIM_OK)
684 return e;
685
686 jim_wide count;
687 e = Jim_GetOpt_Wide(&goi, &count);
688 if (e != JIM_OK)
689 return e;
690
691 uint32_t *data = malloc(count * sizeof(uint32_t));
692 jim_wide i;
693 for (i = 0; i < count; i++) {
694 jim_wide tmp;
695 e = Jim_GetOpt_Wide(&goi, &tmp);
696 if (e != JIM_OK)
697 return e;
698 data[i] = (uint32_t)tmp;
699 }
700
701 /* all args must be consumed */
702 if (goi.argc != 0)
703 return JIM_ERR;
704
705 struct target *target = Jim_CmdPrivData(goi.interp);
706 int result;
707
708 result = target_write_buffer(target, address, count * 4, (const uint8_t *)data);
709
710 free(data);
711
712 return result;
713 }
714
715 static int jim_nds32_multi_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
716 {
717 const char *cmd_name = Jim_GetString(argv[0], NULL);
718
719 Jim_GetOptInfo goi;
720 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
721
722 if (goi.argc < 3) {
723 Jim_SetResultFormatted(goi.interp,
724 "usage: %s # of pairs [<address> <data>]+", cmd_name);
725 return JIM_ERR;
726 }
727
728 int e;
729 jim_wide num_of_pairs;
730 e = Jim_GetOpt_Wide(&goi, &num_of_pairs);
731 if (e != JIM_OK)
732 return e;
733
734 struct target *target = Jim_CmdPrivData(goi.interp);
735 struct aice_port_s *aice = target_to_aice(target);
736 int result;
737 uint32_t address;
738 uint32_t data;
739 jim_wide i;
740
741 aice_set_command_mode(aice, AICE_COMMAND_MODE_PACK);
742 for (i = 0; i < num_of_pairs; i++) {
743 jim_wide tmp;
744 e = Jim_GetOpt_Wide(&goi, &tmp);
745 if (e != JIM_OK)
746 break;
747 address = (uint32_t)tmp;
748
749 e = Jim_GetOpt_Wide(&goi, &tmp);
750 if (e != JIM_OK)
751 break;
752 data = (uint32_t)tmp;
753
754 result = target_write_buffer(target, address, 4, (const uint8_t *)&data);
755 if (result != ERROR_OK)
756 break;
757 }
758 aice_set_command_mode(aice, AICE_COMMAND_MODE_NORMAL);
759
760 /* all args must be consumed */
761 if (goi.argc != 0)
762 return JIM_ERR;
763
764 return ERROR_OK;
765 }
766
767 static int jim_nds32_bulk_read(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
768 {
769 const char *cmd_name = Jim_GetString(argv[0], NULL);
770
771 Jim_GetOptInfo goi;
772 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
773
774 if (goi.argc < 2) {
775 Jim_SetResultFormatted(goi.interp,
776 "usage: %s <address> <count>", cmd_name);
777 return JIM_ERR;
778 }
779
780 int e;
781 jim_wide address;
782 e = Jim_GetOpt_Wide(&goi, &address);
783 if (e != JIM_OK)
784 return e;
785
786 jim_wide count;
787 e = Jim_GetOpt_Wide(&goi, &count);
788 if (e != JIM_OK)
789 return e;
790
791 /* all args must be consumed */
792 if (goi.argc != 0)
793 return JIM_ERR;
794
795 struct target *target = Jim_CmdPrivData(goi.interp);
796 uint32_t *data = malloc(count * sizeof(uint32_t));
797 int result;
798 result = target_read_buffer(target, address, count * 4, (uint8_t *)data);
799 char data_str[11];
800
801 jim_wide i;
802 Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
803 for (i = 0; i < count; i++) {
804 sprintf(data_str, "0x%08x ", data[i]);
805 Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL);
806 }
807
808 free(data);
809
810 return result;
811 }
812
813 static int jim_nds32_read_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
814 {
815 const char *cmd_name = Jim_GetString(argv[0], NULL);
816
817 Jim_GetOptInfo goi;
818 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
819
820 if (goi.argc < 1) {
821 Jim_SetResultFormatted(goi.interp,
822 "usage: %s <edm_sr_name>", cmd_name);
823 return JIM_ERR;
824 }
825
826 int e;
827 char *edm_sr_name;
828 int edm_sr_name_len;
829 e = Jim_GetOpt_String(&goi, &edm_sr_name, &edm_sr_name_len);
830 if (e != JIM_OK)
831 return e;
832
833 /* all args must be consumed */
834 if (goi.argc != 0)
835 return JIM_ERR;
836
837 uint32_t edm_sr_number;
838 uint32_t edm_sr_value;
839 if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0)
840 edm_sr_number = NDS_EDM_SR_EDM_DTR;
841 else if (strncmp(edm_sr_name, "edmsw", edm_sr_name_len) == 0)
842 edm_sr_number = NDS_EDM_SR_EDMSW;
843 else
844 return ERROR_FAIL;
845
846 struct target *target = Jim_CmdPrivData(goi.interp);
847 struct aice_port_s *aice = target_to_aice(target);
848 char data_str[11];
849
850 aice_read_debug_reg(aice, edm_sr_number, &edm_sr_value);
851
852 sprintf(data_str, "0x%08x", edm_sr_value);
853 Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
854 Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL);
855
856 return ERROR_OK;
857 }
858
859 static int jim_nds32_write_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
860 {
861 const char *cmd_name = Jim_GetString(argv[0], NULL);
862
863 Jim_GetOptInfo goi;
864 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
865
866 if (goi.argc < 2) {
867 Jim_SetResultFormatted(goi.interp,
868 "usage: %s <edm_sr_name> <value>", cmd_name);
869 return JIM_ERR;
870 }
871
872 int e;
873 char *edm_sr_name;
874 int edm_sr_name_len;
875 e = Jim_GetOpt_String(&goi, &edm_sr_name, &edm_sr_name_len);
876 if (e != JIM_OK)
877 return e;
878
879 jim_wide value;
880 e = Jim_GetOpt_Wide(&goi, &value);
881 if (e != JIM_OK)
882 return e;
883
884 /* all args must be consumed */
885 if (goi.argc != 0)
886 return JIM_ERR;
887
888 uint32_t edm_sr_number;
889 if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0)
890 edm_sr_number = NDS_EDM_SR_EDM_DTR;
891 else
892 return ERROR_FAIL;
893
894 struct target *target = Jim_CmdPrivData(goi.interp);
895 struct aice_port_s *aice = target_to_aice(target);
896
897 aice_write_debug_reg(aice, edm_sr_number, value);
898
899 return ERROR_OK;
900 }
901
902 static const struct command_registration nds32_query_command_handlers[] = {
903 {
904 .name = "target",
905 .handler = handle_nds32_query_target_command,
906 .mode = COMMAND_EXEC,
907 .usage = "",
908 .help = "reply 'OCD' for gdb to identify server-side is OpenOCD",
909 },
910 {
911 .name = "endian",
912 .handler = handle_nds32_query_endian_command,
913 .mode = COMMAND_EXEC,
914 .usage = "",
915 .help = "query target endian",
916 },
917 {
918 .name = "cpuid",
919 .handler = handle_nds32_query_cpuid_command,
920 .mode = COMMAND_EXEC,
921 .usage = "",
922 .help = "query CPU ID",
923 },
924
925 COMMAND_REGISTRATION_DONE
926 };
927
928 static const struct command_registration nds32_exec_command_handlers[] = {
929 {
930 .name = "dssim",
931 .handler = handle_nds32_dssim_command,
932 .mode = COMMAND_EXEC,
933 .usage = "['on'|'off']",
934 .help = "display/change $INT_MASK.DSSIM status",
935 },
936 {
937 .name = "mem_access",
938 .handler = handle_nds32_memory_access_command,
939 .mode = COMMAND_EXEC,
940 .usage = "['bus'|'cpu']",
941 .help = "display/change memory access channel",
942 },
943 {
944 .name = "mem_mode",
945 .handler = handle_nds32_memory_mode_command,
946 .mode = COMMAND_EXEC,
947 .usage = "['auto'|'mem'|'ilm'|'dlm']",
948 .help = "display/change memory mode",
949 },
950 {
951 .name = "cache",
952 .handler = handle_nds32_cache_command,
953 .mode = COMMAND_EXEC,
954 .usage = "['invalidate']",
955 .help = "cache control",
956 },
957 {
958 .name = "icache",
959 .handler = handle_nds32_icache_command,
960 .mode = COMMAND_EXEC,
961 .usage = "['invalidate'|'enable'|'disable'|'dump']",
962 .help = "icache control",
963 },
964 {
965 .name = "dcache",
966 .handler = handle_nds32_dcache_command,
967 .mode = COMMAND_EXEC,
968 .usage = "['invalidate'|'enable'|'disable'|'dump']",
969 .help = "dcache control",
970 },
971 {
972 .name = "auto_break",
973 .handler = handle_nds32_auto_break_command,
974 .mode = COMMAND_EXEC,
975 .usage = "['on'|'off']",
976 .help = "convert software breakpoints to hardware breakpoints if needed",
977 },
978 {
979 .name = "virtual_hosting",
980 .handler = handle_nds32_virtual_hosting_command,
981 .mode = COMMAND_ANY,
982 .usage = "['on'|'off']",
983 .help = "turn on/off virtual hosting",
984 },
985 {
986 .name = "global_stop",
987 .handler = handle_nds32_global_stop_command,
988 .mode = COMMAND_ANY,
989 .usage = "['on'|'off']",
990 .help = "turn on/off global stop. After turning on, every load/store" \
991 "instructions will be stopped to check memory access.",
992 },
993 {
994 .name = "soft_reset_halt",
995 .handler = handle_nds32_soft_reset_halt_command,
996 .mode = COMMAND_ANY,
997 .usage = "['on'|'off']",
998 .help = "as issuing rest-halt, to use soft-reset-halt or not." \
999 "the feature is for backward-compatible.",
1000 },
1001 {
1002 .name = "boot_time",
1003 .handler = handle_nds32_boot_time_command,
1004 .mode = COMMAND_CONFIG,
1005 .usage = "milliseconds",
1006 .help = "set the period to wait after srst.",
1007 },
1008 {
1009 .name = "login_edm_passcode",
1010 .handler = handle_nds32_login_edm_passcode_command,
1011 .mode = COMMAND_CONFIG,
1012 .usage = "passcode",
1013 .help = "set EDM passcode for secure MCU debugging.",
1014 },
1015 {
1016 .name = "login_edm_operation",
1017 .handler = handle_nds32_login_edm_operation_command,
1018 .mode = COMMAND_CONFIG,
1019 .usage = "login_edm_operation misc_reg_no value",
1020 .help = "add EDM operations for secure MCU debugging.",
1021 },
1022 {
1023 .name = "reset_halt_as_init",
1024 .handler = handle_nds32_reset_halt_as_init_command,
1025 .mode = COMMAND_CONFIG,
1026 .usage = "['on'|'off']",
1027 .help = "reset halt as openocd init.",
1028 },
1029 {
1030 .name = "keep_target_edm_ctl",
1031 .handler = handle_nds32_keep_target_edm_ctl_command,
1032 .mode = COMMAND_CONFIG,
1033 .usage = "['on'|'off']",
1034 .help = "Backup/Restore target EDM_CTL register.",
1035 },
1036 {
1037 .name = "decode",
1038 .handler = handle_nds32_decode_command,
1039 .mode = COMMAND_EXEC,
1040 .usage = "address icount",
1041 .help = "decode instruction.",
1042 },
1043 {
1044 .name = "word_access_mem",
1045 .handler = handle_nds32_word_access_mem_command,
1046 .mode = COMMAND_ANY,
1047 .usage = "['on'|'off']",
1048 .help = "Always use word-aligned address to access memory.",
1049 },
1050 {
1051 .name = "bulk_write",
1052 .jim_handler = jim_nds32_bulk_write,
1053 .mode = COMMAND_EXEC,
1054 .help = "Write multiple 32-bit words to target memory",
1055 .usage = "address count data",
1056 },
1057 {
1058 .name = "multi_write",
1059 .jim_handler = jim_nds32_multi_write,
1060 .mode = COMMAND_EXEC,
1061 .help = "Write multiple addresses/words to target memory",
1062 .usage = "num_of_pairs [address data]+",
1063 },
1064 {
1065 .name = "bulk_read",
1066 .jim_handler = jim_nds32_bulk_read,
1067 .mode = COMMAND_EXEC,
1068 .help = "Read multiple 32-bit words from target memory",
1069 .usage = "address count",
1070 },
1071 {
1072 .name = "read_edmsr",
1073 .jim_handler = jim_nds32_read_edm_sr,
1074 .mode = COMMAND_EXEC,
1075 .help = "Read EDM system register",
1076 .usage = "['edmsw'|'edm_dtr']",
1077 },
1078 {
1079 .name = "write_edmsr",
1080 .jim_handler = jim_nds32_write_edm_sr,
1081 .mode = COMMAND_EXEC,
1082 .help = "Write EDM system register",
1083 .usage = "['edm_dtr'] value",
1084 },
1085 {
1086 .name = "query",
1087 .mode = COMMAND_EXEC,
1088 .help = "Andes query command group",
1089 .usage = "",
1090 .chain = nds32_query_command_handlers,
1091 },
1092
1093 COMMAND_REGISTRATION_DONE
1094 };
1095
1096 const struct command_registration nds32_command_handlers[] = {
1097 {
1098 .name = "nds",
1099 .mode = COMMAND_ANY,
1100 .help = "Andes command group",
1101 .usage = "",
1102 .chain = nds32_exec_command_handlers,
1103 },
1104 COMMAND_REGISTRATION_DONE
1105 };
1106
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)