nds32: modify nds commands implementation
[openocd.git] / src / target / nds32_cmd.c
1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include <helper/command.h>
26 #include "nds32.h"
27 #include "nds32_aice.h"
28 #include "nds32_disassembler.h"
29
30 extern struct nds32_edm_operation nds32_edm_ops[NDS32_EDM_OPERATION_MAX_NUM];
31 extern uint32_t nds32_edm_ops_num;
32
33 static const char *const NDS_MEMORY_ACCESS_NAME[] = {
34 "BUS",
35 "CPU",
36 };
37
38 static const char *const NDS_MEMORY_SELECT_NAME[] = {
39 "AUTO",
40 "MEM",
41 "ILM",
42 "DLM",
43 };
44
45 COMMAND_HANDLER(handle_nds32_dssim_command)
46 {
47 struct target *target = get_current_target(CMD_CTX);
48 struct nds32 *nds32 = target_to_nds32(target);
49
50 if (!is_nds32(nds32)) {
51 command_print(CMD_CTX, "current target isn't an Andes core");
52 return ERROR_FAIL;
53 }
54
55 if (CMD_ARGC > 0) {
56 if (strcmp(CMD_ARGV[0], "on") == 0)
57 nds32->step_isr_enable = true;
58 if (strcmp(CMD_ARGV[0], "off") == 0)
59 nds32->step_isr_enable = false;
60 }
61
62 command_print(CMD_CTX, "$INT_MASK.DSSIM: %d", nds32->step_isr_enable);
63
64 return ERROR_OK;
65 }
66
67 COMMAND_HANDLER(handle_nds32_memory_access_command)
68 {
69 struct target *target = get_current_target(CMD_CTX);
70 struct nds32 *nds32 = target_to_nds32(target);
71 struct aice_port_s *aice = target_to_aice(target);
72 struct nds32_memory *memory = &(nds32->memory);
73
74 if (!is_nds32(nds32)) {
75 command_print(CMD_CTX, "current target isn't an Andes core");
76 return ERROR_FAIL;
77 }
78
79 if (CMD_ARGC > 0) {
80 if (strcmp(CMD_ARGV[0], "bus") == 0)
81 memory->access_channel = NDS_MEMORY_ACC_BUS;
82 else if (strcmp(CMD_ARGV[0], "cpu") == 0)
83 memory->access_channel = NDS_MEMORY_ACC_CPU;
84 else /* default access channel is NDS_MEMORY_ACC_CPU */
85 memory->access_channel = NDS_MEMORY_ACC_CPU;
86
87 LOG_DEBUG("memory access channel is changed to %s",
88 NDS_MEMORY_ACCESS_NAME[memory->access_channel]);
89
90 aice_memory_access(aice, memory->access_channel);
91 } else {
92 command_print(CMD_CTX, "memory access channel: %s",
93 NDS_MEMORY_ACCESS_NAME[memory->access_channel]);
94 }
95
96 return ERROR_OK;
97 }
98
99 COMMAND_HANDLER(handle_nds32_memory_mode_command)
100 {
101 struct target *target = get_current_target(CMD_CTX);
102 struct nds32 *nds32 = target_to_nds32(target);
103 struct aice_port_s *aice = target_to_aice(target);
104
105 if (!is_nds32(nds32)) {
106 command_print(CMD_CTX, "current target isn't an Andes core");
107 return ERROR_FAIL;
108 }
109
110 if (CMD_ARGC > 0) {
111
112 if (nds32->edm.access_control == false) {
113 command_print(CMD_CTX, "Target does not support ACC_CTL. "
114 "Set memory mode to MEMORY");
115 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
116 } else if (nds32->edm.direct_access_local_memory == false) {
117 command_print(CMD_CTX, "Target does not support direct access "
118 "local memory. Set memory mode to MEMORY");
119 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
120
121 /* set to ACC_CTL */
122 aice_memory_mode(aice, nds32->memory.mode);
123 } else {
124 if (strcmp(CMD_ARGV[0], "auto") == 0) {
125 nds32->memory.mode = NDS_MEMORY_SELECT_AUTO;
126 } else if (strcmp(CMD_ARGV[0], "mem") == 0) {
127 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
128 } else if (strcmp(CMD_ARGV[0], "ilm") == 0) {
129 if (nds32->memory.ilm_base == 0)
130 command_print(CMD_CTX, "Target does not support ILM");
131 else
132 nds32->memory.mode = NDS_MEMORY_SELECT_ILM;
133 } else if (strcmp(CMD_ARGV[0], "dlm") == 0) {
134 if (nds32->memory.dlm_base == 0)
135 command_print(CMD_CTX, "Target does not support DLM");
136 else
137 nds32->memory.mode = NDS_MEMORY_SELECT_DLM;
138 }
139
140 /* set to ACC_CTL */
141 aice_memory_mode(aice, nds32->memory.mode);
142 }
143 }
144
145 command_print(CMD_CTX, "memory mode: %s",
146 NDS_MEMORY_SELECT_NAME[nds32->memory.mode]);
147
148 return ERROR_OK;
149 }
150
151 COMMAND_HANDLER(handle_nds32_cache_command)
152 {
153 struct target *target = get_current_target(CMD_CTX);
154 struct nds32 *nds32 = target_to_nds32(target);
155 struct aice_port_s *aice = target_to_aice(target);
156 struct nds32_cache *icache = &(nds32->memory.icache);
157 struct nds32_cache *dcache = &(nds32->memory.dcache);
158 int result;
159
160 if (!is_nds32(nds32)) {
161 command_print(CMD_CTX, "current target isn't an Andes core");
162 return ERROR_FAIL;
163 }
164
165 if (CMD_ARGC > 0) {
166
167 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
168 if ((dcache->line_size != 0) && (dcache->enable == true)) {
169 /* D$ write back */
170 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
171 if (result != ERROR_OK) {
172 command_print(CMD_CTX, "Write back data cache...failed");
173 return result;
174 }
175
176 command_print(CMD_CTX, "Write back data cache...done");
177
178 /* D$ invalidate */
179 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
180 if (result != ERROR_OK) {
181 command_print(CMD_CTX, "Invalidate data cache...failed");
182 return result;
183 }
184
185 command_print(CMD_CTX, "Invalidate data cache...done");
186 } else {
187 if (dcache->line_size == 0)
188 command_print(CMD_CTX, "No data cache");
189 else
190 command_print(CMD_CTX, "Data cache disabled");
191 }
192
193 if ((icache->line_size != 0) && (icache->enable == true)) {
194 /* I$ invalidate */
195 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
196 if (result != ERROR_OK) {
197 command_print(CMD_CTX, "Invalidate instruction cache...failed");
198 return result;
199 }
200
201 command_print(CMD_CTX, "Invalidate instruction cache...done");
202 } else {
203 if (icache->line_size == 0)
204 command_print(CMD_CTX, "No instruction cache");
205 else
206 command_print(CMD_CTX, "Instruction cache disabled");
207 }
208 } else
209 command_print(CMD_CTX, "No valid parameter");
210 }
211
212 return ERROR_OK;
213 }
214
215 COMMAND_HANDLER(handle_nds32_icache_command)
216 {
217 struct target *target = get_current_target(CMD_CTX);
218 struct nds32 *nds32 = target_to_nds32(target);
219 struct aice_port_s *aice = target_to_aice(target);
220 struct nds32_cache *icache = &(nds32->memory.icache);
221 int result;
222
223 if (!is_nds32(nds32)) {
224 command_print(CMD_CTX, "current target isn't an Andes core");
225 return ERROR_FAIL;
226 }
227
228 if (CMD_ARGC > 0) {
229
230 if (icache->line_size == 0) {
231 command_print(CMD_CTX, "No instruction cache");
232 return ERROR_OK;
233 }
234
235 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
236 if (icache->enable == true) {
237 /* I$ invalidate */
238 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
239 if (result != ERROR_OK) {
240 command_print(CMD_CTX, "Invalidate instruction cache...failed");
241 return result;
242 }
243
244 command_print(CMD_CTX, "Invalidate instruction cache...done");
245 } else {
246 command_print(CMD_CTX, "Instruction cache disabled");
247 }
248 } else if (strcmp(CMD_ARGV[0], "enable") == 0) {
249 uint32_t value;
250 nds32_get_mapped_reg(nds32, IR8, &value);
251 nds32_set_mapped_reg(nds32, IR8, value | 0x1);
252 } else if (strcmp(CMD_ARGV[0], "disable") == 0) {
253 uint32_t value;
254 nds32_get_mapped_reg(nds32, IR8, &value);
255 nds32_set_mapped_reg(nds32, IR8, value & ~0x1);
256 } else if (strcmp(CMD_ARGV[0], "dump") == 0) {
257 /* TODO: dump cache content */
258 } else {
259 command_print(CMD_CTX, "No valid parameter");
260 }
261 }
262
263 return ERROR_OK;
264 }
265
266 COMMAND_HANDLER(handle_nds32_dcache_command)
267 {
268 struct target *target = get_current_target(CMD_CTX);
269 struct nds32 *nds32 = target_to_nds32(target);
270 struct aice_port_s *aice = target_to_aice(target);
271 struct nds32_cache *dcache = &(nds32->memory.dcache);
272 int result;
273
274 if (!is_nds32(nds32)) {
275 command_print(CMD_CTX, "current target isn't an Andes core");
276 return ERROR_FAIL;
277 }
278
279 if (CMD_ARGC > 0) {
280
281 if (dcache->line_size == 0) {
282 command_print(CMD_CTX, "No data cache");
283 return ERROR_OK;
284 }
285
286 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
287 if (dcache->enable == true) {
288 /* D$ write back */
289 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
290 if (result != ERROR_OK) {
291 command_print(CMD_CTX, "Write back data cache...failed");
292 return result;
293 }
294
295 command_print(CMD_CTX, "Write back data cache...done");
296
297 /* D$ invalidate */
298 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
299 if (result != ERROR_OK) {
300 command_print(CMD_CTX, "Invalidate data cache...failed");
301 return result;
302 }
303
304 command_print(CMD_CTX, "Invalidate data cache...done");
305 } else {
306 command_print(CMD_CTX, "Data cache disabled");
307 }
308 } else if (strcmp(CMD_ARGV[0], "enable") == 0) {
309 uint32_t value;
310 nds32_get_mapped_reg(nds32, IR8, &value);
311 nds32_set_mapped_reg(nds32, IR8, value | 0x2);
312 } else if (strcmp(CMD_ARGV[0], "disable") == 0) {
313 uint32_t value;
314 nds32_get_mapped_reg(nds32, IR8, &value);
315 nds32_set_mapped_reg(nds32, IR8, value & ~0x2);
316 } else if (strcmp(CMD_ARGV[0], "dump") == 0) {
317 /* TODO: dump cache content */
318 } else {
319 command_print(CMD_CTX, "No valid parameter");
320 }
321 }
322
323 return ERROR_OK;
324 }
325
326 COMMAND_HANDLER(handle_nds32_auto_break_command)
327 {
328 struct target *target = get_current_target(CMD_CTX);
329 struct nds32 *nds32 = target_to_nds32(target);
330
331 if (!is_nds32(nds32)) {
332 command_print(CMD_CTX, "current target isn't an Andes core");
333 return ERROR_FAIL;
334 }
335
336 if (CMD_ARGC > 0) {
337 if (strcmp(CMD_ARGV[0], "on") == 0)
338 nds32->auto_convert_hw_bp = true;
339 if (strcmp(CMD_ARGV[0], "off") == 0)
340 nds32->auto_convert_hw_bp = false;
341 }
342
343 if (nds32->auto_convert_hw_bp)
344 command_print(CMD_CTX, "convert sw break to hw break on ROM: on");
345 else
346 command_print(CMD_CTX, "convert sw break to hw break on ROM: off");
347
348 return ERROR_OK;
349 }
350
351 COMMAND_HANDLER(handle_nds32_virtual_hosting_command)
352 {
353 struct target *target = get_current_target(CMD_CTX);
354 struct nds32 *nds32 = target_to_nds32(target);
355
356 if (!is_nds32(nds32)) {
357 command_print(CMD_CTX, "current target isn't an Andes core");
358 return ERROR_FAIL;
359 }
360
361 if (CMD_ARGC > 0) {
362 if (strcmp(CMD_ARGV[0], "on") == 0)
363 nds32->virtual_hosting = true;
364 if (strcmp(CMD_ARGV[0], "off") == 0)
365 nds32->virtual_hosting = false;
366 }
367
368 if (nds32->virtual_hosting)
369 LOG_INFO("virtual hosting: on");
370 else
371 LOG_INFO("virtual hosting: off");
372
373 return ERROR_OK;
374 }
375
376 COMMAND_HANDLER(handle_nds32_global_stop_command)
377 {
378 struct target *target = get_current_target(CMD_CTX);
379 struct nds32 *nds32 = target_to_nds32(target);
380
381 if (!is_nds32(nds32)) {
382 command_print(CMD_CTX, "current target isn't an Andes core");
383 return ERROR_FAIL;
384 }
385
386 if (CMD_ARGC > 0) {
387 if (strcmp(CMD_ARGV[0], "on") == 0)
388 nds32->global_stop = true;
389 if (strcmp(CMD_ARGV[0], "off") == 0)
390 nds32->global_stop = false;
391 }
392
393 if (nds32->global_stop)
394 LOG_INFO("global stop: on");
395 else
396 LOG_INFO("global stop: off");
397
398 return ERROR_OK;
399 }
400
401 COMMAND_HANDLER(handle_nds32_soft_reset_halt_command)
402 {
403 struct target *target = get_current_target(CMD_CTX);
404 struct nds32 *nds32 = target_to_nds32(target);
405
406 if (!is_nds32(nds32)) {
407 command_print(CMD_CTX, "current target isn't an Andes core");
408 return ERROR_FAIL;
409 }
410
411 if (CMD_ARGC > 0) {
412 if (strcmp(CMD_ARGV[0], "on") == 0)
413 nds32->soft_reset_halt = true;
414 if (strcmp(CMD_ARGV[0], "off") == 0)
415 nds32->soft_reset_halt = false;
416 }
417
418 if (nds32->soft_reset_halt)
419 LOG_INFO("soft-reset-halt: on");
420 else
421 LOG_INFO("soft-reset-halt: off");
422
423 return ERROR_OK;
424 }
425
426 COMMAND_HANDLER(handle_nds32_boot_time_command)
427 {
428 struct target *target = get_current_target(CMD_CTX);
429 struct nds32 *nds32 = target_to_nds32(target);
430
431 if (!is_nds32(nds32)) {
432 command_print(CMD_CTX, "current target isn't an Andes core");
433 return ERROR_FAIL;
434 }
435
436 if (CMD_ARGC > 0)
437 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], nds32->boot_time);
438
439 return ERROR_OK;
440 }
441
442 COMMAND_HANDLER(handle_nds32_login_edm_passcode_command)
443 {
444 struct target *target = get_current_target(CMD_CTX);
445 struct nds32 *nds32 = target_to_nds32(target);
446
447 if (!is_nds32(nds32)) {
448 command_print(CMD_CTX, "current target isn't an Andes core");
449 return ERROR_FAIL;
450 }
451
452 nds32->edm_passcode = strdup(CMD_ARGV[0]);
453
454 LOG_INFO("set EDM passcode: %s", nds32->edm_passcode);
455
456 return ERROR_OK;
457 }
458
459 COMMAND_HANDLER(handle_nds32_login_edm_operation_command)
460 {
461 struct target *target = get_current_target(CMD_CTX);
462 struct nds32 *nds32 = target_to_nds32(target);
463
464 if (!is_nds32(nds32)) {
465 command_print(CMD_CTX, "current target isn't an Andes core");
466 return ERROR_FAIL;
467 }
468
469 if (CMD_ARGC > 1) {
470
471 uint32_t misc_reg_no;
472 uint32_t data;
473
474 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], misc_reg_no);
475 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], data);
476
477 if (nds32_edm_ops_num >= NDS32_EDM_OPERATION_MAX_NUM)
478 return ERROR_FAIL;
479
480 /* Just save the operation. Execute it in nds32_login() */
481 nds32_edm_ops[nds32_edm_ops_num].reg_no = misc_reg_no;
482 nds32_edm_ops[nds32_edm_ops_num].value = data;
483 nds32_edm_ops_num++;
484 } else
485 return ERROR_FAIL;
486
487 return ERROR_OK;
488 }
489
490 COMMAND_HANDLER(handle_nds32_reset_halt_as_init_command)
491 {
492 struct target *target = get_current_target(CMD_CTX);
493 struct nds32 *nds32 = target_to_nds32(target);
494
495 if (!is_nds32(nds32)) {
496 command_print(CMD_CTX, "current target isn't an Andes core");
497 return ERROR_FAIL;
498 }
499
500 if (CMD_ARGC > 0) {
501 if (strcmp(CMD_ARGV[0], "on") == 0)
502 nds32->reset_halt_as_examine = true;
503 if (strcmp(CMD_ARGV[0], "off") == 0)
504 nds32->reset_halt_as_examine = false;
505 }
506
507 return ERROR_OK;
508 }
509
510 COMMAND_HANDLER(handle_nds32_keep_target_edm_ctl_command)
511 {
512 struct target *target = get_current_target(CMD_CTX);
513 struct nds32 *nds32 = target_to_nds32(target);
514
515 if (!is_nds32(nds32)) {
516 command_print(CMD_CTX, "current target isn't an Andes core");
517 return ERROR_FAIL;
518 }
519
520 if (CMD_ARGC > 0) {
521 if (strcmp(CMD_ARGV[0], "on") == 0)
522 nds32->keep_target_edm_ctl = true;
523 if (strcmp(CMD_ARGV[0], "off") == 0)
524 nds32->keep_target_edm_ctl = false;
525 }
526
527 return ERROR_OK;
528 }
529
530 COMMAND_HANDLER(handle_nds32_decode_command)
531 {
532 struct target *target = get_current_target(CMD_CTX);
533 struct nds32 *nds32 = target_to_nds32(target);
534
535 if (!is_nds32(nds32)) {
536 command_print(CMD_CTX, "current target isn't an Andes core");
537 return ERROR_FAIL;
538 }
539
540 if (CMD_ARGC > 1) {
541
542 uint32_t addr;
543 uint32_t insn_count;
544 uint32_t opcode;
545 uint32_t read_addr;
546 uint32_t i;
547 struct nds32_instruction instruction;
548
549 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr);
550 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], insn_count);
551
552 read_addr = addr;
553 i = 0;
554 while (i < insn_count) {
555 if (ERROR_OK != nds32_read_opcode(nds32, read_addr, &opcode))
556 return ERROR_FAIL;
557 if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode,
558 read_addr, &instruction))
559 return ERROR_FAIL;
560
561 command_print(CMD_CTX, "%s", instruction.text);
562
563 read_addr += instruction.instruction_size;
564 i++;
565 }
566 } else if (CMD_ARGC == 1) {
567
568 uint32_t addr;
569 uint32_t opcode;
570 struct nds32_instruction instruction;
571
572 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr);
573
574 if (ERROR_OK != nds32_read_opcode(nds32, addr, &opcode))
575 return ERROR_FAIL;
576 if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode, addr, &instruction))
577 return ERROR_FAIL;
578
579 command_print(CMD_CTX, "%s", instruction.text);
580 } else
581 return ERROR_FAIL;
582
583 return ERROR_OK;
584 }
585
586 COMMAND_HANDLER(handle_nds32_word_access_mem_command)
587 {
588 struct target *target = get_current_target(CMD_CTX);
589 struct nds32 *nds32 = target_to_nds32(target);
590
591 if (!is_nds32(nds32)) {
592 command_print(CMD_CTX, "current target isn't an Andes core");
593 return ERROR_FAIL;
594 }
595
596 if (CMD_ARGC > 0) {
597 if (strcmp(CMD_ARGV[0], "on") == 0)
598 nds32->word_access_mem = true;
599 if (strcmp(CMD_ARGV[0], "off") == 0)
600 nds32->word_access_mem = false;
601 }
602
603 return ERROR_OK;
604 }
605
606 COMMAND_HANDLER(handle_nds32_query_target_command)
607 {
608 struct target *target = get_current_target(CMD_CTX);
609 struct nds32 *nds32 = target_to_nds32(target);
610
611 if (!is_nds32(nds32)) {
612 command_print(CMD_CTX, "current target isn't an Andes core");
613 return ERROR_FAIL;
614 }
615
616 command_print(CMD_CTX, "OCD");
617
618 return ERROR_OK;
619 }
620
621 COMMAND_HANDLER(handle_nds32_query_endian_command)
622 {
623 struct target *target = get_current_target(CMD_CTX);
624 struct nds32 *nds32 = target_to_nds32(target);
625
626 if (!is_nds32(nds32)) {
627 command_print(CMD_CTX, "current target isn't an Andes core");
628 return ERROR_FAIL;
629 }
630
631 uint32_t value_psw;
632 nds32_get_mapped_reg(nds32, IR0, &value_psw);
633
634 if (value_psw & 0x20)
635 command_print(CMD_CTX, "BE");
636 else
637 command_print(CMD_CTX, "LE");
638
639 return ERROR_OK;
640 }
641
642 COMMAND_HANDLER(handle_nds32_query_cpuid_command)
643 {
644 struct target *target = get_current_target(CMD_CTX);
645 struct nds32 *nds32 = target_to_nds32(target);
646
647 if (!is_nds32(nds32)) {
648 command_print(CMD_CTX, "current target isn't an Andes core");
649 return ERROR_FAIL;
650 }
651
652 command_print(CMD_CTX, "CPUID: %s", target_name(target));
653
654 return ERROR_OK;
655 }
656
657 static int jim_nds32_bulk_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
658 {
659 const char *cmd_name = Jim_GetString(argv[0], NULL);
660
661 Jim_GetOptInfo goi;
662 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
663
664 if (goi.argc < 3) {
665 Jim_SetResultFormatted(goi.interp,
666 "usage: %s <address> <count> <data>", cmd_name);
667 return JIM_ERR;
668 }
669
670 int e;
671 jim_wide address;
672 e = Jim_GetOpt_Wide(&goi, &address);
673 if (e != JIM_OK)
674 return e;
675
676 jim_wide count;
677 e = Jim_GetOpt_Wide(&goi, &count);
678 if (e != JIM_OK)
679 return e;
680
681 uint32_t *data = malloc(count * sizeof(uint32_t));
682 jim_wide i;
683 for (i = 0; i < count; i++) {
684 jim_wide tmp;
685 e = Jim_GetOpt_Wide(&goi, &tmp);
686 if (e != JIM_OK)
687 return e;
688 data[i] = (uint32_t)tmp;
689 }
690
691 /* all args must be consumed */
692 if (goi.argc != 0)
693 return JIM_ERR;
694
695 struct target *target = Jim_CmdPrivData(goi.interp);
696 int result;
697
698 result = target_write_buffer(target, address, count * 4, (const uint8_t *)data);
699
700 free(data);
701
702 return result;
703 }
704
705 static int jim_nds32_multi_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
706 {
707 const char *cmd_name = Jim_GetString(argv[0], NULL);
708
709 Jim_GetOptInfo goi;
710 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
711
712 if (goi.argc < 3) {
713 Jim_SetResultFormatted(goi.interp,
714 "usage: %s # of pairs [<address> <data>]+", cmd_name);
715 return JIM_ERR;
716 }
717
718 int e;
719 jim_wide num_of_pairs;
720 e = Jim_GetOpt_Wide(&goi, &num_of_pairs);
721 if (e != JIM_OK)
722 return e;
723
724 struct target *target = Jim_CmdPrivData(goi.interp);
725 struct aice_port_s *aice = target_to_aice(target);
726 int result;
727 uint32_t address;
728 uint32_t data;
729 jim_wide i;
730
731 aice_set_command_mode(aice, AICE_COMMAND_MODE_PACK);
732 for (i = 0; i < num_of_pairs; i++) {
733 jim_wide tmp;
734 e = Jim_GetOpt_Wide(&goi, &tmp);
735 if (e != JIM_OK)
736 break;
737 address = (uint32_t)tmp;
738
739 e = Jim_GetOpt_Wide(&goi, &tmp);
740 if (e != JIM_OK)
741 break;
742 data = (uint32_t)tmp;
743
744 result = target_write_buffer(target, address, 4, (const uint8_t *)&data);
745 if (result != ERROR_OK)
746 break;
747 }
748 aice_set_command_mode(aice, AICE_COMMAND_MODE_NORMAL);
749
750 /* all args must be consumed */
751 if (goi.argc != 0)
752 return JIM_ERR;
753
754 return ERROR_OK;
755 }
756
757 static int jim_nds32_bulk_read(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
758 {
759 const char *cmd_name = Jim_GetString(argv[0], NULL);
760
761 Jim_GetOptInfo goi;
762 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
763
764 if (goi.argc < 2) {
765 Jim_SetResultFormatted(goi.interp,
766 "usage: %s <address> <count>", cmd_name);
767 return JIM_ERR;
768 }
769
770 int e;
771 jim_wide address;
772 e = Jim_GetOpt_Wide(&goi, &address);
773 if (e != JIM_OK)
774 return e;
775
776 jim_wide count;
777 e = Jim_GetOpt_Wide(&goi, &count);
778 if (e != JIM_OK)
779 return e;
780
781 /* all args must be consumed */
782 if (goi.argc != 0)
783 return JIM_ERR;
784
785 struct target *target = Jim_CmdPrivData(goi.interp);
786 uint32_t *data = malloc(count * sizeof(uint32_t));
787 int result;
788 result = target_read_buffer(target, address, count * 4, (uint8_t *)data);
789 char data_str[11];
790
791 jim_wide i;
792 Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
793 for (i = 0; i < count; i++) {
794 sprintf(data_str, "0x%08x ", data[i]);
795 Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL);
796 }
797
798 free(data);
799
800 return result;
801 }
802
803 static int jim_nds32_read_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
804 {
805 const char *cmd_name = Jim_GetString(argv[0], NULL);
806
807 Jim_GetOptInfo goi;
808 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
809
810 if (goi.argc < 1) {
811 Jim_SetResultFormatted(goi.interp,
812 "usage: %s <edm_sr_name>", cmd_name);
813 return JIM_ERR;
814 }
815
816 int e;
817 char *edm_sr_name;
818 int edm_sr_name_len;
819 e = Jim_GetOpt_String(&goi, &edm_sr_name, &edm_sr_name_len);
820 if (e != JIM_OK)
821 return e;
822
823 /* all args must be consumed */
824 if (goi.argc != 0)
825 return JIM_ERR;
826
827 uint32_t edm_sr_number;
828 uint32_t edm_sr_value;
829 if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0)
830 edm_sr_number = NDS_EDM_SR_EDM_DTR;
831 else if (strncmp(edm_sr_name, "edmsw", edm_sr_name_len) == 0)
832 edm_sr_number = NDS_EDM_SR_EDMSW;
833 else
834 return ERROR_FAIL;
835
836 struct target *target = Jim_CmdPrivData(goi.interp);
837 struct aice_port_s *aice = target_to_aice(target);
838 char data_str[11];
839
840 aice_read_debug_reg(aice, edm_sr_number, &edm_sr_value);
841
842 sprintf(data_str, "0x%08x", edm_sr_value);
843 Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
844 Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL);
845
846 return ERROR_OK;
847 }
848
849 static int jim_nds32_write_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
850 {
851 const char *cmd_name = Jim_GetString(argv[0], NULL);
852
853 Jim_GetOptInfo goi;
854 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
855
856 if (goi.argc < 2) {
857 Jim_SetResultFormatted(goi.interp,
858 "usage: %s <edm_sr_name> <value>", cmd_name);
859 return JIM_ERR;
860 }
861
862 int e;
863 char *edm_sr_name;
864 int edm_sr_name_len;
865 e = Jim_GetOpt_String(&goi, &edm_sr_name, &edm_sr_name_len);
866 if (e != JIM_OK)
867 return e;
868
869 jim_wide value;
870 e = Jim_GetOpt_Wide(&goi, &value);
871 if (e != JIM_OK)
872 return e;
873
874 /* all args must be consumed */
875 if (goi.argc != 0)
876 return JIM_ERR;
877
878 uint32_t edm_sr_number;
879 if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0)
880 edm_sr_number = NDS_EDM_SR_EDM_DTR;
881 else
882 return ERROR_FAIL;
883
884 struct target *target = Jim_CmdPrivData(goi.interp);
885 struct aice_port_s *aice = target_to_aice(target);
886
887 aice_write_debug_reg(aice, edm_sr_number, value);
888
889 return ERROR_OK;
890 }
891
892 static const struct command_registration nds32_query_command_handlers[] = {
893 {
894 .name = "target",
895 .handler = handle_nds32_query_target_command,
896 .mode = COMMAND_EXEC,
897 .usage = "",
898 .help = "reply 'OCD' for gdb to identify server-side is OpenOCD",
899 },
900 {
901 .name = "endian",
902 .handler = handle_nds32_query_endian_command,
903 .mode = COMMAND_EXEC,
904 .usage = "",
905 .help = "query target endian",
906 },
907 {
908 .name = "cpuid",
909 .handler = handle_nds32_query_cpuid_command,
910 .mode = COMMAND_EXEC,
911 .usage = "",
912 .help = "query CPU ID",
913 },
914
915 COMMAND_REGISTRATION_DONE
916 };
917
918 static const struct command_registration nds32_exec_command_handlers[] = {
919 {
920 .name = "dssim",
921 .handler = handle_nds32_dssim_command,
922 .mode = COMMAND_EXEC,
923 .usage = "['on'|'off']",
924 .help = "display/change $INT_MASK.DSSIM status",
925 },
926 {
927 .name = "mem_access",
928 .handler = handle_nds32_memory_access_command,
929 .mode = COMMAND_EXEC,
930 .usage = "['bus'|'cpu']",
931 .help = "display/change memory access channel",
932 },
933 {
934 .name = "mem_mode",
935 .handler = handle_nds32_memory_mode_command,
936 .mode = COMMAND_EXEC,
937 .usage = "['auto'|'mem'|'ilm'|'dlm']",
938 .help = "display/change memory mode",
939 },
940 {
941 .name = "cache",
942 .handler = handle_nds32_cache_command,
943 .mode = COMMAND_EXEC,
944 .usage = "['invalidate']",
945 .help = "cache control",
946 },
947 {
948 .name = "icache",
949 .handler = handle_nds32_icache_command,
950 .mode = COMMAND_EXEC,
951 .usage = "['invalidate'|'enable'|'disable'|'dump']",
952 .help = "icache control",
953 },
954 {
955 .name = "dcache",
956 .handler = handle_nds32_dcache_command,
957 .mode = COMMAND_EXEC,
958 .usage = "['invalidate'|'enable'|'disable'|'dump']",
959 .help = "dcache control",
960 },
961 {
962 .name = "auto_break",
963 .handler = handle_nds32_auto_break_command,
964 .mode = COMMAND_EXEC,
965 .usage = "['on'|'off']",
966 .help = "convert software breakpoints to hardware breakpoints if needed",
967 },
968 {
969 .name = "virtual_hosting",
970 .handler = handle_nds32_virtual_hosting_command,
971 .mode = COMMAND_ANY,
972 .usage = "['on'|'off']",
973 .help = "turn on/off virtual hosting",
974 },
975 {
976 .name = "global_stop",
977 .handler = handle_nds32_global_stop_command,
978 .mode = COMMAND_ANY,
979 .usage = "['on'|'off']",
980 .help = "turn on/off global stop. After turning on, every load/store" \
981 "instructions will be stopped to check memory access.",
982 },
983 {
984 .name = "soft_reset_halt",
985 .handler = handle_nds32_soft_reset_halt_command,
986 .mode = COMMAND_ANY,
987 .usage = "['on'|'off']",
988 .help = "as issuing rest-halt, to use soft-reset-halt or not." \
989 "the feature is for backward-compatible.",
990 },
991 {
992 .name = "boot_time",
993 .handler = handle_nds32_boot_time_command,
994 .mode = COMMAND_CONFIG,
995 .usage = "milliseconds",
996 .help = "set the period to wait after srst.",
997 },
998 {
999 .name = "login_edm_passcode",
1000 .handler = handle_nds32_login_edm_passcode_command,
1001 .mode = COMMAND_CONFIG,
1002 .usage = "passcode",
1003 .help = "set EDM passcode for secure MCU debugging.",
1004 },
1005 {
1006 .name = "login_edm_operation",
1007 .handler = handle_nds32_login_edm_operation_command,
1008 .mode = COMMAND_CONFIG,
1009 .usage = "login_edm_operation misc_reg_no value",
1010 .help = "add EDM operations for secure MCU debugging.",
1011 },
1012 {
1013 .name = "reset_halt_as_init",
1014 .handler = handle_nds32_reset_halt_as_init_command,
1015 .mode = COMMAND_CONFIG,
1016 .usage = "['on'|'off']",
1017 .help = "reset halt as openocd init.",
1018 },
1019 {
1020 .name = "keep_target_edm_ctl",
1021 .handler = handle_nds32_keep_target_edm_ctl_command,
1022 .mode = COMMAND_CONFIG,
1023 .usage = "['on'|'off']",
1024 .help = "Backup/Restore target EDM_CTL register.",
1025 },
1026 {
1027 .name = "decode",
1028 .handler = handle_nds32_decode_command,
1029 .mode = COMMAND_EXEC,
1030 .usage = "address icount",
1031 .help = "decode instruction.",
1032 },
1033 {
1034 .name = "word_access_mem",
1035 .handler = handle_nds32_word_access_mem_command,
1036 .mode = COMMAND_ANY,
1037 .usage = "['on'|'off']",
1038 .help = "Always use word-aligned address to access memory.",
1039 },
1040 {
1041 .name = "bulk_write",
1042 .jim_handler = jim_nds32_bulk_write,
1043 .mode = COMMAND_EXEC,
1044 .help = "Write multiple 32-bit words to target memory",
1045 .usage = "address count data",
1046 },
1047 {
1048 .name = "multi_write",
1049 .jim_handler = jim_nds32_multi_write,
1050 .mode = COMMAND_EXEC,
1051 .help = "Write multiple addresses/words to target memory",
1052 .usage = "num_of_pairs [address data]+",
1053 },
1054 {
1055 .name = "bulk_read",
1056 .jim_handler = jim_nds32_bulk_read,
1057 .mode = COMMAND_EXEC,
1058 .help = "Read multiple 32-bit words from target memory",
1059 .usage = "address count",
1060 },
1061 {
1062 .name = "read_edmsr",
1063 .jim_handler = jim_nds32_read_edm_sr,
1064 .mode = COMMAND_EXEC,
1065 .help = "Read EDM system register",
1066 .usage = "['edmsw'|'edm_dtr']",
1067 },
1068 {
1069 .name = "write_edmsr",
1070 .jim_handler = jim_nds32_write_edm_sr,
1071 .mode = COMMAND_EXEC,
1072 .help = "Write EDM system register",
1073 .usage = "['edm_dtr'] value",
1074 },
1075 {
1076 .name = "query",
1077 .mode = COMMAND_EXEC,
1078 .help = "Andes query command group",
1079 .usage = "",
1080 .chain = nds32_query_command_handlers,
1081 },
1082
1083 COMMAND_REGISTRATION_DONE
1084 };
1085
1086 const struct command_registration nds32_command_handlers[] = {
1087 {
1088 .name = "nds",
1089 .mode = COMMAND_ANY,
1090 .help = "Andes command group",
1091 .usage = "",
1092 .chain = nds32_exec_command_handlers,
1093 },
1094 COMMAND_REGISTRATION_DONE
1095 };
1096