1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
25 #include <helper/command.h>
27 #include "nds32_aice.h"
28 #include "nds32_disassembler.h"
30 extern struct nds32_edm_operation nds32_edm_ops
[NDS32_EDM_OPERATION_MAX_NUM
];
31 extern uint32_t nds32_edm_ops_num
;
33 static const char *const NDS_MEMORY_ACCESS_NAME
[] = {
38 static const char *const NDS_MEMORY_SELECT_NAME
[] = {
45 COMMAND_HANDLER(handle_nds32_dssim_command
)
47 struct target
*target
= get_current_target(CMD_CTX
);
48 struct nds32
*nds32
= target_to_nds32(target
);
50 if (!is_nds32(nds32
)) {
51 command_print(CMD_CTX
, "current target isn't an Andes core");
56 if (strcmp(CMD_ARGV
[0], "on") == 0)
57 nds32
->step_isr_enable
= true;
58 if (strcmp(CMD_ARGV
[0], "off") == 0)
59 nds32
->step_isr_enable
= false;
62 command_print(CMD_CTX
, "$INT_MASK.DSSIM: %d", nds32
->step_isr_enable
);
67 COMMAND_HANDLER(handle_nds32_memory_access_command
)
69 struct target
*target
= get_current_target(CMD_CTX
);
70 struct nds32
*nds32
= target_to_nds32(target
);
71 struct aice_port_s
*aice
= target_to_aice(target
);
72 struct nds32_memory
*memory
= &(nds32
->memory
);
74 if (!is_nds32(nds32
)) {
75 command_print(CMD_CTX
, "current target isn't an Andes core");
80 if (strcmp(CMD_ARGV
[0], "bus") == 0)
81 memory
->access_channel
= NDS_MEMORY_ACC_BUS
;
82 else if (strcmp(CMD_ARGV
[0], "cpu") == 0)
83 memory
->access_channel
= NDS_MEMORY_ACC_CPU
;
84 else /* default access channel is NDS_MEMORY_ACC_CPU */
85 memory
->access_channel
= NDS_MEMORY_ACC_CPU
;
87 LOG_DEBUG("memory access channel is changed to %s",
88 NDS_MEMORY_ACCESS_NAME
[memory
->access_channel
]);
90 aice_memory_access(aice
, memory
->access_channel
);
92 command_print(CMD_CTX
, "memory access channel: %s",
93 NDS_MEMORY_ACCESS_NAME
[memory
->access_channel
]);
99 COMMAND_HANDLER(handle_nds32_memory_mode_command
)
101 struct target
*target
= get_current_target(CMD_CTX
);
102 struct nds32
*nds32
= target_to_nds32(target
);
103 struct aice_port_s
*aice
= target_to_aice(target
);
105 if (!is_nds32(nds32
)) {
106 command_print(CMD_CTX
, "current target isn't an Andes core");
112 if (nds32
->edm
.access_control
== false) {
113 command_print(CMD_CTX
, "Target does not support ACC_CTL. "
114 "Set memory mode to MEMORY");
115 nds32
->memory
.mode
= NDS_MEMORY_SELECT_MEM
;
116 } else if (nds32
->edm
.direct_access_local_memory
== false) {
117 command_print(CMD_CTX
, "Target does not support direct access "
118 "local memory. Set memory mode to MEMORY");
119 nds32
->memory
.mode
= NDS_MEMORY_SELECT_MEM
;
122 aice_memory_mode(aice
, nds32
->memory
.mode
);
124 if (strcmp(CMD_ARGV
[0], "auto") == 0) {
125 nds32
->memory
.mode
= NDS_MEMORY_SELECT_AUTO
;
126 } else if (strcmp(CMD_ARGV
[0], "mem") == 0) {
127 nds32
->memory
.mode
= NDS_MEMORY_SELECT_MEM
;
128 } else if (strcmp(CMD_ARGV
[0], "ilm") == 0) {
129 if (nds32
->memory
.ilm_base
== 0)
130 command_print(CMD_CTX
, "Target does not support ILM");
132 nds32
->memory
.mode
= NDS_MEMORY_SELECT_ILM
;
133 } else if (strcmp(CMD_ARGV
[0], "dlm") == 0) {
134 if (nds32
->memory
.dlm_base
== 0)
135 command_print(CMD_CTX
, "Target does not support DLM");
137 nds32
->memory
.mode
= NDS_MEMORY_SELECT_DLM
;
141 aice_memory_mode(aice
, nds32
->memory
.mode
);
145 command_print(CMD_CTX
, "memory mode: %s",
146 NDS_MEMORY_SELECT_NAME
[nds32
->memory
.mode
]);
151 COMMAND_HANDLER(handle_nds32_cache_command
)
153 struct target
*target
= get_current_target(CMD_CTX
);
154 struct nds32
*nds32
= target_to_nds32(target
);
155 struct aice_port_s
*aice
= target_to_aice(target
);
156 struct nds32_cache
*icache
= &(nds32
->memory
.icache
);
157 struct nds32_cache
*dcache
= &(nds32
->memory
.dcache
);
160 if (!is_nds32(nds32
)) {
161 command_print(CMD_CTX
, "current target isn't an Andes core");
167 if (strcmp(CMD_ARGV
[0], "invalidate") == 0) {
168 if ((dcache
->line_size
!= 0) && (dcache
->enable
== true)) {
170 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_WBALL
, 0);
171 if (result
!= ERROR_OK
) {
172 command_print(CMD_CTX
, "Write back data cache...failed");
176 command_print(CMD_CTX
, "Write back data cache...done");
179 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_INVALALL
, 0);
180 if (result
!= ERROR_OK
) {
181 command_print(CMD_CTX
, "Invalidate data cache...failed");
185 command_print(CMD_CTX
, "Invalidate data cache...done");
187 if (dcache
->line_size
== 0)
188 command_print(CMD_CTX
, "No data cache");
190 command_print(CMD_CTX
, "Data cache disabled");
193 if ((icache
->line_size
!= 0) && (icache
->enable
== true)) {
195 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1I_INVALALL
, 0);
196 if (result
!= ERROR_OK
) {
197 command_print(CMD_CTX
, "Invalidate instruction cache...failed");
201 command_print(CMD_CTX
, "Invalidate instruction cache...done");
203 if (icache
->line_size
== 0)
204 command_print(CMD_CTX
, "No instruction cache");
206 command_print(CMD_CTX
, "Instruction cache disabled");
209 command_print(CMD_CTX
, "No valid parameter");
215 COMMAND_HANDLER(handle_nds32_icache_command
)
217 struct target
*target
= get_current_target(CMD_CTX
);
218 struct nds32
*nds32
= target_to_nds32(target
);
219 struct aice_port_s
*aice
= target_to_aice(target
);
220 struct nds32_cache
*icache
= &(nds32
->memory
.icache
);
223 if (!is_nds32(nds32
)) {
224 command_print(CMD_CTX
, "current target isn't an Andes core");
230 if (icache
->line_size
== 0) {
231 command_print(CMD_CTX
, "No instruction cache");
235 if (strcmp(CMD_ARGV
[0], "invalidate") == 0) {
236 if (icache
->enable
== true) {
238 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1I_INVALALL
, 0);
239 if (result
!= ERROR_OK
) {
240 command_print(CMD_CTX
, "Invalidate instruction cache...failed");
244 command_print(CMD_CTX
, "Invalidate instruction cache...done");
246 command_print(CMD_CTX
, "Instruction cache disabled");
248 } else if (strcmp(CMD_ARGV
[0], "enable") == 0) {
250 nds32_get_mapped_reg(nds32
, IR8
, &value
);
251 nds32_set_mapped_reg(nds32
, IR8
, value
| 0x1);
252 } else if (strcmp(CMD_ARGV
[0], "disable") == 0) {
254 nds32_get_mapped_reg(nds32
, IR8
, &value
);
255 nds32_set_mapped_reg(nds32
, IR8
, value
& ~0x1);
256 } else if (strcmp(CMD_ARGV
[0], "dump") == 0) {
257 /* TODO: dump cache content */
259 command_print(CMD_CTX
, "No valid parameter");
266 COMMAND_HANDLER(handle_nds32_dcache_command
)
268 struct target
*target
= get_current_target(CMD_CTX
);
269 struct nds32
*nds32
= target_to_nds32(target
);
270 struct aice_port_s
*aice
= target_to_aice(target
);
271 struct nds32_cache
*dcache
= &(nds32
->memory
.dcache
);
274 if (!is_nds32(nds32
)) {
275 command_print(CMD_CTX
, "current target isn't an Andes core");
281 if (dcache
->line_size
== 0) {
282 command_print(CMD_CTX
, "No data cache");
286 if (strcmp(CMD_ARGV
[0], "invalidate") == 0) {
287 if (dcache
->enable
== true) {
289 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_WBALL
, 0);
290 if (result
!= ERROR_OK
) {
291 command_print(CMD_CTX
, "Write back data cache...failed");
295 command_print(CMD_CTX
, "Write back data cache...done");
298 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_INVALALL
, 0);
299 if (result
!= ERROR_OK
) {
300 command_print(CMD_CTX
, "Invalidate data cache...failed");
304 command_print(CMD_CTX
, "Invalidate data cache...done");
306 command_print(CMD_CTX
, "Data cache disabled");
308 } else if (strcmp(CMD_ARGV
[0], "enable") == 0) {
310 nds32_get_mapped_reg(nds32
, IR8
, &value
);
311 nds32_set_mapped_reg(nds32
, IR8
, value
| 0x2);
312 } else if (strcmp(CMD_ARGV
[0], "disable") == 0) {
314 nds32_get_mapped_reg(nds32
, IR8
, &value
);
315 nds32_set_mapped_reg(nds32
, IR8
, value
& ~0x2);
316 } else if (strcmp(CMD_ARGV
[0], "dump") == 0) {
317 /* TODO: dump cache content */
319 command_print(CMD_CTX
, "No valid parameter");
326 COMMAND_HANDLER(handle_nds32_auto_break_command
)
328 struct target
*target
= get_current_target(CMD_CTX
);
329 struct nds32
*nds32
= target_to_nds32(target
);
331 if (!is_nds32(nds32
)) {
332 command_print(CMD_CTX
, "current target isn't an Andes core");
337 if (strcmp(CMD_ARGV
[0], "on") == 0)
338 nds32
->auto_convert_hw_bp
= true;
339 if (strcmp(CMD_ARGV
[0], "off") == 0)
340 nds32
->auto_convert_hw_bp
= false;
343 if (nds32
->auto_convert_hw_bp
)
344 command_print(CMD_CTX
, "convert sw break to hw break on ROM: on");
346 command_print(CMD_CTX
, "convert sw break to hw break on ROM: off");
351 COMMAND_HANDLER(handle_nds32_virtual_hosting_command
)
353 struct target
*target
= get_current_target(CMD_CTX
);
354 struct nds32
*nds32
= target_to_nds32(target
);
356 if (!is_nds32(nds32
)) {
357 command_print(CMD_CTX
, "current target isn't an Andes core");
362 if (strcmp(CMD_ARGV
[0], "on") == 0)
363 nds32
->virtual_hosting
= true;
364 if (strcmp(CMD_ARGV
[0], "off") == 0)
365 nds32
->virtual_hosting
= false;
368 if (nds32
->virtual_hosting
)
369 LOG_INFO("virtual hosting: on");
371 LOG_INFO("virtual hosting: off");
376 COMMAND_HANDLER(handle_nds32_global_stop_command
)
378 struct target
*target
= get_current_target(CMD_CTX
);
379 struct nds32
*nds32
= target_to_nds32(target
);
381 if (!is_nds32(nds32
)) {
382 command_print(CMD_CTX
, "current target isn't an Andes core");
387 if (strcmp(CMD_ARGV
[0], "on") == 0)
388 nds32
->global_stop
= true;
389 if (strcmp(CMD_ARGV
[0], "off") == 0)
390 nds32
->global_stop
= false;
393 if (nds32
->global_stop
)
394 LOG_INFO("global stop: on");
396 LOG_INFO("global stop: off");
401 COMMAND_HANDLER(handle_nds32_soft_reset_halt_command
)
403 struct target
*target
= get_current_target(CMD_CTX
);
404 struct nds32
*nds32
= target_to_nds32(target
);
406 if (!is_nds32(nds32
)) {
407 command_print(CMD_CTX
, "current target isn't an Andes core");
412 if (strcmp(CMD_ARGV
[0], "on") == 0)
413 nds32
->soft_reset_halt
= true;
414 if (strcmp(CMD_ARGV
[0], "off") == 0)
415 nds32
->soft_reset_halt
= false;
418 if (nds32
->soft_reset_halt
)
419 LOG_INFO("soft-reset-halt: on");
421 LOG_INFO("soft-reset-halt: off");
426 COMMAND_HANDLER(handle_nds32_boot_time_command
)
428 struct target
*target
= get_current_target(CMD_CTX
);
429 struct nds32
*nds32
= target_to_nds32(target
);
431 if (!is_nds32(nds32
)) {
432 command_print(CMD_CTX
, "current target isn't an Andes core");
437 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], nds32
->boot_time
);
442 COMMAND_HANDLER(handle_nds32_login_edm_passcode_command
)
444 struct target
*target
= get_current_target(CMD_CTX
);
445 struct nds32
*nds32
= target_to_nds32(target
);
447 if (!is_nds32(nds32
)) {
448 command_print(CMD_CTX
, "current target isn't an Andes core");
452 nds32
->edm_passcode
= strdup(CMD_ARGV
[0]);
454 LOG_INFO("set EDM passcode: %s", nds32
->edm_passcode
);
459 COMMAND_HANDLER(handle_nds32_login_edm_operation_command
)
461 struct target
*target
= get_current_target(CMD_CTX
);
462 struct nds32
*nds32
= target_to_nds32(target
);
464 if (!is_nds32(nds32
)) {
465 command_print(CMD_CTX
, "current target isn't an Andes core");
471 uint32_t misc_reg_no
;
474 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], misc_reg_no
);
475 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], data
);
477 if (nds32_edm_ops_num
>= NDS32_EDM_OPERATION_MAX_NUM
)
480 /* Just save the operation. Execute it in nds32_login() */
481 nds32_edm_ops
[nds32_edm_ops_num
].reg_no
= misc_reg_no
;
482 nds32_edm_ops
[nds32_edm_ops_num
].value
= data
;
490 COMMAND_HANDLER(handle_nds32_reset_halt_as_init_command
)
492 struct target
*target
= get_current_target(CMD_CTX
);
493 struct nds32
*nds32
= target_to_nds32(target
);
495 if (!is_nds32(nds32
)) {
496 command_print(CMD_CTX
, "current target isn't an Andes core");
501 if (strcmp(CMD_ARGV
[0], "on") == 0)
502 nds32
->reset_halt_as_examine
= true;
503 if (strcmp(CMD_ARGV
[0], "off") == 0)
504 nds32
->reset_halt_as_examine
= false;
510 COMMAND_HANDLER(handle_nds32_keep_target_edm_ctl_command
)
512 struct target
*target
= get_current_target(CMD_CTX
);
513 struct nds32
*nds32
= target_to_nds32(target
);
515 if (!is_nds32(nds32
)) {
516 command_print(CMD_CTX
, "current target isn't an Andes core");
521 if (strcmp(CMD_ARGV
[0], "on") == 0)
522 nds32
->keep_target_edm_ctl
= true;
523 if (strcmp(CMD_ARGV
[0], "off") == 0)
524 nds32
->keep_target_edm_ctl
= false;
530 COMMAND_HANDLER(handle_nds32_decode_command
)
532 struct target
*target
= get_current_target(CMD_CTX
);
533 struct nds32
*nds32
= target_to_nds32(target
);
535 if (!is_nds32(nds32
)) {
536 command_print(CMD_CTX
, "current target isn't an Andes core");
547 struct nds32_instruction instruction
;
549 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], addr
);
550 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], insn_count
);
554 while (i
< insn_count
) {
555 if (ERROR_OK
!= nds32_read_opcode(nds32
, read_addr
, &opcode
))
557 if (ERROR_OK
!= nds32_evaluate_opcode(nds32
, opcode
,
558 read_addr
, &instruction
))
561 command_print(CMD_CTX
, "%s", instruction
.text
);
563 read_addr
+= instruction
.instruction_size
;
566 } else if (CMD_ARGC
== 1) {
570 struct nds32_instruction instruction
;
572 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], addr
);
574 if (ERROR_OK
!= nds32_read_opcode(nds32
, addr
, &opcode
))
576 if (ERROR_OK
!= nds32_evaluate_opcode(nds32
, opcode
, addr
, &instruction
))
579 command_print(CMD_CTX
, "%s", instruction
.text
);
586 COMMAND_HANDLER(handle_nds32_word_access_mem_command
)
588 struct target
*target
= get_current_target(CMD_CTX
);
589 struct nds32
*nds32
= target_to_nds32(target
);
591 if (!is_nds32(nds32
)) {
592 command_print(CMD_CTX
, "current target isn't an Andes core");
597 if (strcmp(CMD_ARGV
[0], "on") == 0)
598 nds32
->word_access_mem
= true;
599 if (strcmp(CMD_ARGV
[0], "off") == 0)
600 nds32
->word_access_mem
= false;
606 COMMAND_HANDLER(handle_nds32_query_target_command
)
608 struct target
*target
= get_current_target(CMD_CTX
);
609 struct nds32
*nds32
= target_to_nds32(target
);
611 if (!is_nds32(nds32
)) {
612 command_print(CMD_CTX
, "current target isn't an Andes core");
616 command_print(CMD_CTX
, "OCD");
621 COMMAND_HANDLER(handle_nds32_query_endian_command
)
623 struct target
*target
= get_current_target(CMD_CTX
);
624 struct nds32
*nds32
= target_to_nds32(target
);
626 if (!is_nds32(nds32
)) {
627 command_print(CMD_CTX
, "current target isn't an Andes core");
632 nds32_get_mapped_reg(nds32
, IR0
, &value_psw
);
634 if (value_psw
& 0x20)
635 command_print(CMD_CTX
, "BE");
637 command_print(CMD_CTX
, "LE");
642 COMMAND_HANDLER(handle_nds32_query_cpuid_command
)
644 struct target
*target
= get_current_target(CMD_CTX
);
645 struct nds32
*nds32
= target_to_nds32(target
);
647 if (!is_nds32(nds32
)) {
648 command_print(CMD_CTX
, "current target isn't an Andes core");
652 command_print(CMD_CTX
, "CPUID: %s", target_name(target
));
657 static int jim_nds32_bulk_write(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
659 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
662 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
665 Jim_SetResultFormatted(goi
.interp
,
666 "usage: %s <address> <count> <data>", cmd_name
);
672 e
= Jim_GetOpt_Wide(&goi
, &address
);
677 e
= Jim_GetOpt_Wide(&goi
, &count
);
681 uint32_t *data
= malloc(count
* sizeof(uint32_t));
683 for (i
= 0; i
< count
; i
++) {
685 e
= Jim_GetOpt_Wide(&goi
, &tmp
);
688 data
[i
] = (uint32_t)tmp
;
691 /* all args must be consumed */
695 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
698 result
= target_write_buffer(target
, address
, count
* 4, (const uint8_t *)data
);
705 static int jim_nds32_multi_write(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
707 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
710 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
713 Jim_SetResultFormatted(goi
.interp
,
714 "usage: %s # of pairs [<address> <data>]+", cmd_name
);
719 jim_wide num_of_pairs
;
720 e
= Jim_GetOpt_Wide(&goi
, &num_of_pairs
);
724 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
725 struct aice_port_s
*aice
= target_to_aice(target
);
731 aice_set_command_mode(aice
, AICE_COMMAND_MODE_PACK
);
732 for (i
= 0; i
< num_of_pairs
; i
++) {
734 e
= Jim_GetOpt_Wide(&goi
, &tmp
);
737 address
= (uint32_t)tmp
;
739 e
= Jim_GetOpt_Wide(&goi
, &tmp
);
742 data
= (uint32_t)tmp
;
744 result
= target_write_buffer(target
, address
, 4, (const uint8_t *)&data
);
745 if (result
!= ERROR_OK
)
748 aice_set_command_mode(aice
, AICE_COMMAND_MODE_NORMAL
);
750 /* all args must be consumed */
757 static int jim_nds32_bulk_read(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
759 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
762 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
765 Jim_SetResultFormatted(goi
.interp
,
766 "usage: %s <address> <count>", cmd_name
);
772 e
= Jim_GetOpt_Wide(&goi
, &address
);
777 e
= Jim_GetOpt_Wide(&goi
, &count
);
781 /* all args must be consumed */
785 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
786 uint32_t *data
= malloc(count
* sizeof(uint32_t));
788 result
= target_read_buffer(target
, address
, count
* 4, (uint8_t *)data
);
792 Jim_SetResult(interp
, Jim_NewEmptyStringObj(interp
));
793 for (i
= 0; i
< count
; i
++) {
794 sprintf(data_str
, "0x%08x ", data
[i
]);
795 Jim_AppendStrings(interp
, Jim_GetResult(interp
), data_str
, NULL
);
803 static int jim_nds32_read_edm_sr(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
805 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
808 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
811 Jim_SetResultFormatted(goi
.interp
,
812 "usage: %s <edm_sr_name>", cmd_name
);
819 e
= Jim_GetOpt_String(&goi
, &edm_sr_name
, &edm_sr_name_len
);
823 /* all args must be consumed */
827 uint32_t edm_sr_number
;
828 uint32_t edm_sr_value
;
829 if (strncmp(edm_sr_name
, "edm_dtr", edm_sr_name_len
) == 0)
830 edm_sr_number
= NDS_EDM_SR_EDM_DTR
;
831 else if (strncmp(edm_sr_name
, "edmsw", edm_sr_name_len
) == 0)
832 edm_sr_number
= NDS_EDM_SR_EDMSW
;
836 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
837 struct aice_port_s
*aice
= target_to_aice(target
);
840 aice_read_debug_reg(aice
, edm_sr_number
, &edm_sr_value
);
842 sprintf(data_str
, "0x%08x", edm_sr_value
);
843 Jim_SetResult(interp
, Jim_NewEmptyStringObj(interp
));
844 Jim_AppendStrings(interp
, Jim_GetResult(interp
), data_str
, NULL
);
849 static int jim_nds32_write_edm_sr(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
851 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
854 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
857 Jim_SetResultFormatted(goi
.interp
,
858 "usage: %s <edm_sr_name> <value>", cmd_name
);
865 e
= Jim_GetOpt_String(&goi
, &edm_sr_name
, &edm_sr_name_len
);
870 e
= Jim_GetOpt_Wide(&goi
, &value
);
874 /* all args must be consumed */
878 uint32_t edm_sr_number
;
879 if (strncmp(edm_sr_name
, "edm_dtr", edm_sr_name_len
) == 0)
880 edm_sr_number
= NDS_EDM_SR_EDM_DTR
;
884 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
885 struct aice_port_s
*aice
= target_to_aice(target
);
887 aice_write_debug_reg(aice
, edm_sr_number
, value
);
892 static const struct command_registration nds32_query_command_handlers
[] = {
895 .handler
= handle_nds32_query_target_command
,
896 .mode
= COMMAND_EXEC
,
898 .help
= "reply 'OCD' for gdb to identify server-side is OpenOCD",
902 .handler
= handle_nds32_query_endian_command
,
903 .mode
= COMMAND_EXEC
,
905 .help
= "query target endian",
909 .handler
= handle_nds32_query_cpuid_command
,
910 .mode
= COMMAND_EXEC
,
912 .help
= "query CPU ID",
915 COMMAND_REGISTRATION_DONE
918 static const struct command_registration nds32_exec_command_handlers
[] = {
921 .handler
= handle_nds32_dssim_command
,
922 .mode
= COMMAND_EXEC
,
923 .usage
= "['on'|'off']",
924 .help
= "display/change $INT_MASK.DSSIM status",
927 .name
= "mem_access",
928 .handler
= handle_nds32_memory_access_command
,
929 .mode
= COMMAND_EXEC
,
930 .usage
= "['bus'|'cpu']",
931 .help
= "display/change memory access channel",
935 .handler
= handle_nds32_memory_mode_command
,
936 .mode
= COMMAND_EXEC
,
937 .usage
= "['auto'|'mem'|'ilm'|'dlm']",
938 .help
= "display/change memory mode",
942 .handler
= handle_nds32_cache_command
,
943 .mode
= COMMAND_EXEC
,
944 .usage
= "['invalidate']",
945 .help
= "cache control",
949 .handler
= handle_nds32_icache_command
,
950 .mode
= COMMAND_EXEC
,
951 .usage
= "['invalidate'|'enable'|'disable'|'dump']",
952 .help
= "icache control",
956 .handler
= handle_nds32_dcache_command
,
957 .mode
= COMMAND_EXEC
,
958 .usage
= "['invalidate'|'enable'|'disable'|'dump']",
959 .help
= "dcache control",
962 .name
= "auto_break",
963 .handler
= handle_nds32_auto_break_command
,
964 .mode
= COMMAND_EXEC
,
965 .usage
= "['on'|'off']",
966 .help
= "convert software breakpoints to hardware breakpoints if needed",
969 .name
= "virtual_hosting",
970 .handler
= handle_nds32_virtual_hosting_command
,
972 .usage
= "['on'|'off']",
973 .help
= "turn on/off virtual hosting",
976 .name
= "global_stop",
977 .handler
= handle_nds32_global_stop_command
,
979 .usage
= "['on'|'off']",
980 .help
= "turn on/off global stop. After turning on, every load/store" \
981 "instructions will be stopped to check memory access.",
984 .name
= "soft_reset_halt",
985 .handler
= handle_nds32_soft_reset_halt_command
,
987 .usage
= "['on'|'off']",
988 .help
= "as issuing rest-halt, to use soft-reset-halt or not." \
989 "the feature is for backward-compatible.",
993 .handler
= handle_nds32_boot_time_command
,
994 .mode
= COMMAND_CONFIG
,
995 .usage
= "milliseconds",
996 .help
= "set the period to wait after srst.",
999 .name
= "login_edm_passcode",
1000 .handler
= handle_nds32_login_edm_passcode_command
,
1001 .mode
= COMMAND_CONFIG
,
1002 .usage
= "passcode",
1003 .help
= "set EDM passcode for secure MCU debugging.",
1006 .name
= "login_edm_operation",
1007 .handler
= handle_nds32_login_edm_operation_command
,
1008 .mode
= COMMAND_CONFIG
,
1009 .usage
= "login_edm_operation misc_reg_no value",
1010 .help
= "add EDM operations for secure MCU debugging.",
1013 .name
= "reset_halt_as_init",
1014 .handler
= handle_nds32_reset_halt_as_init_command
,
1015 .mode
= COMMAND_CONFIG
,
1016 .usage
= "['on'|'off']",
1017 .help
= "reset halt as openocd init.",
1020 .name
= "keep_target_edm_ctl",
1021 .handler
= handle_nds32_keep_target_edm_ctl_command
,
1022 .mode
= COMMAND_CONFIG
,
1023 .usage
= "['on'|'off']",
1024 .help
= "Backup/Restore target EDM_CTL register.",
1028 .handler
= handle_nds32_decode_command
,
1029 .mode
= COMMAND_EXEC
,
1030 .usage
= "address icount",
1031 .help
= "decode instruction.",
1034 .name
= "word_access_mem",
1035 .handler
= handle_nds32_word_access_mem_command
,
1036 .mode
= COMMAND_ANY
,
1037 .usage
= "['on'|'off']",
1038 .help
= "Always use word-aligned address to access memory.",
1041 .name
= "bulk_write",
1042 .jim_handler
= jim_nds32_bulk_write
,
1043 .mode
= COMMAND_EXEC
,
1044 .help
= "Write multiple 32-bit words to target memory",
1045 .usage
= "address count data",
1048 .name
= "multi_write",
1049 .jim_handler
= jim_nds32_multi_write
,
1050 .mode
= COMMAND_EXEC
,
1051 .help
= "Write multiple addresses/words to target memory",
1052 .usage
= "num_of_pairs [address data]+",
1055 .name
= "bulk_read",
1056 .jim_handler
= jim_nds32_bulk_read
,
1057 .mode
= COMMAND_EXEC
,
1058 .help
= "Read multiple 32-bit words from target memory",
1059 .usage
= "address count",
1062 .name
= "read_edmsr",
1063 .jim_handler
= jim_nds32_read_edm_sr
,
1064 .mode
= COMMAND_EXEC
,
1065 .help
= "Read EDM system register",
1066 .usage
= "['edmsw'|'edm_dtr']",
1069 .name
= "write_edmsr",
1070 .jim_handler
= jim_nds32_write_edm_sr
,
1071 .mode
= COMMAND_EXEC
,
1072 .help
= "Write EDM system register",
1073 .usage
= "['edm_dtr'] value",
1077 .mode
= COMMAND_EXEC
,
1078 .help
= "Andes query command group",
1080 .chain
= nds32_query_command_handlers
,
1083 COMMAND_REGISTRATION_DONE
1086 const struct command_registration nds32_command_handlers
[] = {
1089 .mode
= COMMAND_ANY
,
1090 .help
= "Andes command group",
1092 .chain
= nds32_exec_command_handlers
,
1094 COMMAND_REGISTRATION_DONE
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)