src/target/nds32.h

   1 /***************************************************************************
   2  *   Copyright (C) 2013 Andes Technology                                   *
   3  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifndef OPENOCD_TARGET_NDS32_H
  20 #define OPENOCD_TARGET_NDS32_H
  21
  22 #include <jtag/jtag.h>
  23 #include "target.h"
  24 #include "target_type.h"
  25 #include "register.h"
  26 #include "breakpoints.h"
  27 #include "nds32_reg.h"
  28 #include "nds32_insn.h"
  29 #include "nds32_edm.h"
  30
  31 #define NDS32_EDM_OPERATION_MAX_NUM 64
  32
  33 #define CHECK_RETVAL(action)                    \
  34         do {                                    \
  35                 int __retval = (action);        \
  36                 if (__retval != ERROR_OK) {     \
  37                         LOG_DEBUG("error while calling \"%s\"", \
  38                                 # action);     \
  39                         return __retval;        \
  40                 }                               \
  41         } while (0)
  42
  43 /**
  44  * @file
  45  * Holds the interface to Andes cores.
  46  */
  47
  48 extern const char *nds32_debug_type_name[11];
  49
  50 enum nds32_debug_reason {
  51         NDS32_DEBUG_BREAK = 0,
  52         NDS32_DEBUG_BREAK_16,
  53         NDS32_DEBUG_INST_BREAK,
  54         NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE,
  55         NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE,
  56         NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE,
  57         NDS32_DEBUG_DEBUG_INTERRUPT,
  58         NDS32_DEBUG_HARDWARE_SINGLE_STEP,
  59         NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE,
  60         NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE,
  61         NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP,
  62 };
  63
  64 #define NDS32_STRUCT_STAT_SIZE 60
  65 #define NDS32_STRUCT_TIMEVAL_SIZE 8
  66
  67 enum nds32_syscall_id {
  68         NDS32_SYSCALL_UNDEFINED = 0,
  69         NDS32_SYSCALL_EXIT = 1,
  70         NDS32_SYSCALL_OPEN = 2,
  71         NDS32_SYSCALL_CLOSE = 3,
  72         NDS32_SYSCALL_READ = 4,
  73         NDS32_SYSCALL_WRITE = 5,
  74         NDS32_SYSCALL_LSEEK = 6,
  75         NDS32_SYSCALL_UNLINK = 7,
  76         NDS32_SYSCALL_RENAME = 3001,
  77         NDS32_SYSCALL_FSTAT = 10,
  78         NDS32_SYSCALL_STAT = 15,
  79         NDS32_SYSCALL_GETTIMEOFDAY = 19,
  80         NDS32_SYSCALL_ISATTY = 3002,
  81         NDS32_SYSCALL_SYSTEM = 3003,
  82         NDS32_SYSCALL_ERRNO = 6001,
  83 };
  84
  85 #define NDS32_COMMON_MAGIC (int)0xADE5ADE5
  86
  87 struct nds32_edm {
  88
  89         /** EDM_CFG.VER, indicate the EDM version */
  90         int version;
  91
  92         /** The number of hardware breakpoints */
  93         int breakpoint_num;
  94
  95         /** EDM_CFG.DALM, indicate if direct local memory access
  96          * feature is supported or not */
  97         bool direct_access_local_memory;
  98
  99         /** Support ACC_CTL register */
 100         bool access_control;
 101
 102         /** */
 103         bool support_max_stop;
 104 };
 105
 106 struct nds32_cache {
 107
 108         /** enable cache or not */
 109         bool enable;
 110
 111         /** cache sets per way */
 112         int set;
 113
 114         /** cache ways */
 115         int way;
 116
 117         /** cache line size */
 118         int line_size;
 119
 120         /** cache locking support */
 121         bool lock_support;
 122 };
 123
 124 struct nds32_memory {
 125
 126         /** ICache */
 127         struct nds32_cache icache;
 128
 129         /** DCache */
 130         struct nds32_cache dcache;
 131
 132         /** On-chip instruction local memory base */
 133         int ilm_base;
 134
 135         /** On-chip instruction local memory size */
 136         int ilm_size;
 137
 138         /** ILM base register alignment version */
 139         int ilm_align_ver;
 140
 141         /** DLM is enabled or not */
 142         bool ilm_enable;
 143
 144         /** DLM start address */
 145         int ilm_start;
 146
 147         /** DLM end address */
 148         int ilm_end;
 149
 150         /** On-chip data local memory base */
 151         int dlm_base;
 152
 153         /** On-chip data local memory size */
 154         int dlm_size;
 155
 156         /** DLM base register alignment version */
 157         int dlm_align_ver;
 158
 159         /** DLM is enabled or not */
 160         bool dlm_enable;
 161
 162         /** DLM start address */
 163         int dlm_start;
 164
 165         /** DLM end address */
 166         int dlm_end;
 167
 168         /** Memory access method */
 169         enum nds_memory_access access_channel;
 170
 171         /** Memory access mode */
 172         enum nds_memory_select mode;
 173
 174         /** Address translation */
 175         bool address_translation;
 176 };
 177
 178 struct nds32_cpu_version {
 179         bool performance_extension;
 180         bool _16bit_extension;
 181         bool performance_extension_2;
 182         bool cop_fpu_extension;
 183         bool string_extension;
 184
 185         int revision;
 186         int cpu_id_family;
 187         int cpu_id_version;
 188 };
 189
 190 struct nds32_mmu_config {
 191         int memory_protection;
 192         int memory_protection_version;
 193         bool fully_associative_tlb;
 194         int tlb_size;
 195         int tlb_ways;
 196         int tlb_sets;
 197         bool _8k_page_support;
 198         int extra_page_size_support;
 199         bool tlb_lock;
 200         bool hardware_page_table_walker;
 201         bool default_endian;
 202         int partition_num;
 203         bool invisible_tlb;
 204         bool vlpt;
 205         bool ntme;
 206         bool drde;
 207         int default_min_page_size;
 208         bool multiple_page_size_in_use;
 209 };
 210
 211 struct nds32_misc_config {
 212         bool edm;
 213         bool local_memory_dma;
 214         bool performance_monitor;
 215         bool high_speed_memory_port;
 216         bool debug_tracer;
 217         bool div_instruction;
 218         bool mac_instruction;
 219         int audio_isa;
 220         bool L2_cache;
 221         bool reduce_register;
 222         bool addr_24;
 223         bool interruption_level;
 224         int baseline_instruction;
 225         bool no_dx_register;
 226         bool implement_dependant_register;
 227         bool implement_dependant_sr_encoding;
 228         bool ifc;
 229         bool mcu;
 230         bool ex9;
 231         int shadow;
 232 };
 233
 234 /**
 235  * Represents a generic Andes core.
 236  */
 237 struct nds32 {
 238         int common_magic;
 239         struct reg_cache *core_cache;
 240
 241         /** Handle for the debug module. */
 242         struct nds32_edm edm;
 243
 244         /** Memory information */
 245         struct nds32_memory memory;
 246
 247         /** cpu version */
 248         struct nds32_cpu_version cpu_version;
 249
 250         /** MMU configuration */
 251         struct nds32_mmu_config mmu_config;
 252
 253         /** Misc configuration */
 254         struct nds32_misc_config misc_config;
 255
 256         /** Retrieve all core registers, for display. */
 257         int (*full_context)(struct nds32 *nds32);
 258
 259         /** Register mappings */
 260         int (*register_map)(struct nds32 *nds32, int reg_no);
 261
 262         /** Get debug exception virtual address */
 263         int (*get_debug_reason)(struct nds32 *nds32, uint32_t *reason);
 264
 265         /** Restore target registers may be modified in debug state */
 266         int (*leave_debug_state)(struct nds32 *nds32, bool enable_watchpoint);
 267
 268         /** Backup target registers may be modified in debug state */
 269         int (*enter_debug_state)(struct nds32 *nds32, bool enable_watchpoint);
 270
 271         /** Get address hit watchpoint */
 272         int (*get_watched_address)(struct nds32 *nds32, uint32_t *address, uint32_t reason);
 273
 274         /** maximum interrupt level */
 275         uint32_t max_interrupt_level;
 276
 277         /** current interrupt level */
 278         uint32_t current_interrupt_level;
 279
 280         uint32_t watched_address;
 281
 282         /** Flag reporting whether virtual hosting is active. */
 283         bool virtual_hosting;
 284
 285         /** Flag reporting whether continue/step hits syscall or not */
 286         bool hit_syscall;
 287
 288         /** Value to be returned by virtual hosting SYS_ERRNO request. */
 289         int virtual_hosting_errno;
 290
 291         /** Flag reporting whether syscall is aborted */
 292         bool virtual_hosting_ctrl_c;
 293
 294         /** Record syscall ID for other operations to do special processing for target */
 295         int active_syscall_id;
 296
 297         struct breakpoint syscall_break;
 298
 299         /** Flag reporting whether global stop is active. */
 300         bool global_stop;
 301
 302         /** Flag reporting whether to use soft-reset-halt or not as issuing reset-halt. */
 303         bool soft_reset_halt;
 304
 305         /** reset-halt as target examine */
 306         bool reset_halt_as_examine;
 307
 308         /** backup/restore target EDM_CTL value. As debugging target debug
 309          * handler, it should be true. */
 310         bool keep_target_edm_ctl;
 311
 312         /* Value of $EDM_CTL before target enters debug mode */
 313         uint32_t backup_edm_ctl;
 314
 315         /** always use word-aligned address to access memory */
 316         bool word_access_mem;
 317
 318         /** EDM passcode for debugging secure MCU */
 319         char *edm_passcode;
 320
 321         /** current privilege_level if using secure MCU. value 0 is the highest level.  */
 322         int privilege_level;
 323
 324         /** Period to wait after SRST. */
 325         uint32_t boot_time;
 326
 327         /** Flag to indicate HSS steps into ISR or not */
 328         bool step_isr_enable;
 329
 330         /** Flag to indicate register table is ready or not */
 331         bool init_arch_info_after_halted;
 332
 333         /** Flag to indicate audio-extension is enabled or not */
 334         bool audio_enable;
 335
 336         /** Flag to indicate fpu-extension is enabled or not */
 337         bool fpu_enable;
 338
 339         /* Andes Core has mixed endian model. Instruction is always big-endian.
 340          * Data may be big or little endian. Device registers may have different
 341          * endian from data and instruction. */
 342         /** Endian of data memory */
 343         enum target_endianness data_endian;
 344
 345         /** Endian of device registers */
 346         enum target_endianness device_reg_endian;
 347
 348         /** Flag to indicate if auto convert software breakpoints to
 349          *  hardware breakpoints or not in ROM */
 350         bool auto_convert_hw_bp;
 351
 352         /* Flag to indicate the target is attached by debugger or not */
 353         bool attached;
 354
 355         /** Backpointer to the target. */
 356         struct target *target;
 357
 358         void *arch_info;
 359 };
 360
 361 struct nds32_reg {
 362         int32_t num;
 363         uint8_t value[8];
 364         struct target *target;
 365         struct nds32 *nds32;
 366         bool enable;
 367 };
 368
 369 struct nds32_edm_operation {
 370         uint32_t reg_no;
 371         uint32_t value;
 372 };
 373
 374 extern int nds32_config(struct nds32 *nds32);
 375 extern int nds32_init_arch_info(struct target *target, struct nds32 *nds32);
 376 extern int nds32_full_context(struct nds32 *nds32);
 377 extern int nds32_arch_state(struct target *target);
 378 extern int nds32_add_software_breakpoint(struct target *target,
 379                 struct breakpoint *breakpoint);
 380 extern int nds32_remove_software_breakpoint(struct target *target,
 381                 struct breakpoint *breakpoint);
 382
 383 extern int nds32_get_gdb_reg_list(struct target *target,
 384                 struct reg **reg_list[], int *reg_list_size,
 385                 enum target_register_class reg_class);
 386
 387 extern int nds32_write_buffer(struct target *target, uint32_t address,
 388                 uint32_t size, const uint8_t *buffer);
 389 extern int nds32_read_buffer(struct target *target, uint32_t address,
 390                 uint32_t size, uint8_t *buffer);
 391 extern int nds32_read_memory(struct target *target, uint32_t address,
 392                 uint32_t size, uint32_t count, uint8_t *buffer);
 393 extern int nds32_write_memory(struct target *target, uint32_t address,
 394                 uint32_t size, uint32_t count, const uint8_t *buffer);
 395
 396 extern int nds32_init_register_table(struct nds32 *nds32);
 397 extern int nds32_init_memory_info(struct nds32 *nds32);
 398 extern int nds32_restore_context(struct target *target);
 399 extern int nds32_get_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t *value);
 400 extern int nds32_set_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t value);
 401
 402 extern int nds32_edm_config(struct nds32 *nds32);
 403 extern int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t length);
 404 extern int nds32_mmu(struct target *target, int *enabled);
 405 extern int nds32_virtual_to_physical(struct target *target, target_addr_t address,
 406                 target_addr_t *physical);
 407 extern int nds32_read_phys_memory(struct target *target, target_addr_t address,
 408                 uint32_t size, uint32_t count, uint8_t *buffer);
 409 extern int nds32_write_phys_memory(struct target *target, target_addr_t address,
 410                 uint32_t size, uint32_t count, const uint8_t *buffer);
 411 extern uint32_t nds32_nextpc(struct nds32 *nds32, int current, uint32_t address);
 412 extern int nds32_examine_debug_reason(struct nds32 *nds32);
 413 extern int nds32_step(struct target *target, int current,
 414                 target_addr_t address, int handle_breakpoints);
 415 extern int nds32_target_state(struct nds32 *nds32, enum target_state *state);
 416 extern int nds32_halt(struct target *target);
 417 extern int nds32_poll(struct target *target);
 418 extern int nds32_resume(struct target *target, int current,
 419                 target_addr_t address, int handle_breakpoints, int debug_execution);
 420 extern int nds32_assert_reset(struct target *target);
 421 extern int nds32_init(struct nds32 *nds32);
 422 extern int nds32_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info);
 423 extern int nds32_gdb_fileio_write_memory(struct nds32 *nds32, uint32_t address,
 424                 uint32_t size, const uint8_t *buffer);
 425 extern int nds32_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c);
 426 extern int nds32_reset_halt(struct nds32 *nds32);
 427 extern int nds32_login(struct nds32 *nds32);
 428 extern int nds32_profiling(struct target *target, uint32_t *samples,
 429                         uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
 430
 431 /** Convert target handle to generic Andes target state handle. */
 432 static inline struct nds32 *target_to_nds32(struct target *target)
 433 {
 434         assert(target != NULL);
 435         return target->arch_info;
 436 }
 437
 438 /** */
 439 static inline struct aice_port_s *target_to_aice(struct target *target)
 440 {
 441         assert(target != NULL);
 442         return target->tap->priv;
 443 }
 444
 445 static inline bool is_nds32(struct nds32 *nds32)
 446 {
 447         assert(nds32 != NULL);
 448         return nds32->common_magic == NDS32_COMMON_MAGIC;
 449 }
 450
 451 static inline bool nds32_reach_max_interrupt_level(struct nds32 *nds32)
 452 {
 453         assert(nds32 != NULL);
 454         return nds32->max_interrupt_level == nds32->current_interrupt_level;
 455 }
 456
 457 #endif /* OPENOCD_TARGET_NDS32_H */