1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
25 #include <helper/log.h>
26 #include <helper/binarybuffer.h>
28 #include "nds32_aice.h"
29 #include "nds32_tlb.h"
30 #include "nds32_disassembler.h"
32 const int NDS32_BREAK_16
= 0x00EA; /* 0xEA00 */
33 const int NDS32_BREAK_32
= 0x0A000064; /* 0x6400000A */
35 struct nds32_edm_operation nds32_edm_ops
[NDS32_EDM_OPERATION_MAX_NUM
];
36 uint32_t nds32_edm_ops_num
;
38 const char *nds32_debug_type_name
[11] = {
41 "HARDWARE BREAKPOINT",
42 "DATA ADDR WATCHPOINT PRECISE",
43 "DATA VALUE WATCHPOINT PRECISE",
44 "DATA VALUE WATCHPOINT IMPRECISE",
46 "HARDWARE SINGLE STEP",
47 "DATA ADDR WATCHPOINT NEXT PRECISE",
48 "DATA VALUE WATCHPOINT NEXT PRECISE",
49 "LOAD STORE GLOBAL STOP",
52 static const int NDS32_LM_SIZE_TABLE
[16] = {
66 static const int NDS32_LINE_SIZE_TABLE
[6] = {
75 static int nds32_get_core_reg(struct reg
*reg
)
78 struct nds32_reg
*reg_arch_info
= reg
->arch_info
;
79 struct target
*target
= reg_arch_info
->target
;
80 struct nds32
*nds32
= target_to_nds32(target
);
81 struct aice_port_s
*aice
= target_to_aice(target
);
83 if (target
->state
!= TARGET_HALTED
) {
84 LOG_ERROR("Target not halted");
85 return ERROR_TARGET_NOT_HALTED
;
89 LOG_DEBUG("reading register(cached) %i(%s), value: 0x%8.8" PRIx32
,
90 reg_arch_info
->num
, reg
->name
, reg_arch_info
->value
);
94 int mapped_regnum
= nds32
->register_map(nds32
, reg_arch_info
->num
);
96 if (reg_arch_info
->enable
== false) {
97 reg_arch_info
->value
= NDS32_REGISTER_DISABLE
;
100 if ((nds32
->fpu_enable
== false) &&
101 (NDS32_REG_TYPE_FPU
== nds32_reg_type(mapped_regnum
))) {
102 reg_arch_info
->value
= 0;
104 } else if ((nds32
->audio_enable
== false) &&
105 (NDS32_REG_TYPE_AUMR
== nds32_reg_type(mapped_regnum
))) {
106 reg_arch_info
->value
= 0;
109 retval
= aice_read_register(aice
,
110 mapped_regnum
, &(reg_arch_info
->value
));
113 LOG_DEBUG("reading register %i(%s), value: 0x%8.8" PRIx32
,
114 reg_arch_info
->num
, reg
->name
, reg_arch_info
->value
);
117 if (retval
== ERROR_OK
) {
125 static int nds32_get_core_reg_64(struct reg
*reg
)
128 struct nds32_reg
*reg_arch_info
= reg
->arch_info
;
129 struct target
*target
= reg_arch_info
->target
;
130 struct nds32
*nds32
= target_to_nds32(target
);
131 struct aice_port_s
*aice
= target_to_aice(target
);
133 if (target
->state
!= TARGET_HALTED
) {
134 LOG_ERROR("Target not halted");
135 return ERROR_TARGET_NOT_HALTED
;
141 if (reg_arch_info
->enable
== false) {
142 reg_arch_info
->value_64
= NDS32_REGISTER_DISABLE
;
145 if ((nds32
->fpu_enable
== false) &&
146 ((FD0
<= reg_arch_info
->num
) && (reg_arch_info
->num
<= FD31
))) {
147 reg_arch_info
->value_64
= 0;
150 retval
= aice_read_reg_64(aice
, reg_arch_info
->num
,
151 &(reg_arch_info
->value_64
));
155 if (retval
== ERROR_OK
) {
163 static int nds32_update_psw(struct nds32
*nds32
)
166 struct aice_port_s
*aice
= target_to_aice(nds32
->target
);
168 nds32_get_mapped_reg(nds32
, IR0
, &value_ir0
);
170 /* Save data memory endian */
171 if ((value_ir0
>> 5) & 0x1) {
172 nds32
->data_endian
= TARGET_BIG_ENDIAN
;
173 aice_set_data_endian(aice
, AICE_BIG_ENDIAN
);
175 nds32
->data_endian
= TARGET_LITTLE_ENDIAN
;
176 aice_set_data_endian(aice
, AICE_LITTLE_ENDIAN
);
179 /* Save translation status */
180 nds32
->memory
.address_translation
= ((value_ir0
>> 7) & 0x1) ? true : false;
185 static int nds32_update_mmu_info(struct nds32
*nds32
)
189 /* Update MMU control status */
190 nds32_get_mapped_reg(nds32
, MR0
, &value
);
191 nds32
->mmu_config
.default_min_page_size
= value
& 0x1;
192 nds32
->mmu_config
.multiple_page_size_in_use
= (value
>> 10) & 0x1;
197 static int nds32_update_cache_info(struct nds32
*nds32
)
201 if (ERROR_OK
== nds32_get_mapped_reg(nds32
, MR8
, &value
)) {
203 nds32
->memory
.icache
.enable
= true;
205 nds32
->memory
.icache
.enable
= false;
208 nds32
->memory
.dcache
.enable
= true;
210 nds32
->memory
.dcache
.enable
= false;
212 nds32
->memory
.icache
.enable
= false;
213 nds32
->memory
.dcache
.enable
= false;
219 static int nds32_update_lm_info(struct nds32
*nds32
)
221 struct nds32_memory
*memory
= &(nds32
->memory
);
225 nds32_get_mapped_reg(nds32
, MR6
, &value_mr6
);
227 memory
->ilm_enable
= true;
229 memory
->ilm_enable
= false;
231 if (memory
->ilm_align_ver
== 0) { /* 1MB aligned */
232 memory
->ilm_start
= value_mr6
& 0xFFF00000;
233 memory
->ilm_end
= memory
->ilm_start
+ memory
->ilm_size
;
234 } else if (memory
->ilm_align_ver
== 1) { /* aligned to local memory size */
235 memory
->ilm_start
= value_mr6
& 0xFFFFFC00;
236 memory
->ilm_end
= memory
->ilm_start
+ memory
->ilm_size
;
238 memory
->ilm_start
= -1;
239 memory
->ilm_end
= -1;
242 nds32_get_mapped_reg(nds32
, MR7
, &value_mr7
);
244 memory
->dlm_enable
= true;
246 memory
->dlm_enable
= false;
248 if (memory
->dlm_align_ver
== 0) { /* 1MB aligned */
249 memory
->dlm_start
= value_mr7
& 0xFFF00000;
250 memory
->dlm_end
= memory
->dlm_start
+ memory
->dlm_size
;
251 } else if (memory
->dlm_align_ver
== 1) { /* aligned to local memory size */
252 memory
->dlm_start
= value_mr7
& 0xFFFFFC00;
253 memory
->dlm_end
= memory
->dlm_start
+ memory
->dlm_size
;
255 memory
->dlm_start
= -1;
256 memory
->dlm_end
= -1;
263 * If fpu/audio is disabled, to access fpu/audio registers will cause
264 * exceptions. So, we need to check if fpu/audio is enabled or not as
265 * target is halted. If fpu/audio is disabled, as users access fpu/audio
266 * registers, OpenOCD will return fake value 0 instead of accessing
267 * registers through DIM.
269 static int nds32_check_extension(struct nds32
*nds32
)
273 nds32_get_mapped_reg(nds32
, FUCPR
, &value
);
274 if (value
== NDS32_REGISTER_DISABLE
) {
275 nds32
->fpu_enable
= false;
276 nds32
->audio_enable
= false;
281 nds32
->fpu_enable
= true;
283 nds32
->fpu_enable
= false;
285 if (value
& 0x80000000)
286 nds32
->audio_enable
= true;
288 nds32
->audio_enable
= false;
293 static int nds32_set_core_reg(struct reg
*reg
, uint8_t *buf
)
295 struct nds32_reg
*reg_arch_info
= reg
->arch_info
;
296 struct target
*target
= reg_arch_info
->target
;
297 struct nds32
*nds32
= target_to_nds32(target
);
298 struct aice_port_s
*aice
= target_to_aice(target
);
299 uint32_t value
= buf_get_u32(buf
, 0, 32);
301 if (target
->state
!= TARGET_HALTED
) {
302 LOG_ERROR("Target not halted");
303 return ERROR_TARGET_NOT_HALTED
;
306 int mapped_regnum
= nds32
->register_map(nds32
, reg_arch_info
->num
);
308 /* ignore values that will generate exception */
309 if (nds32_reg_exception(mapped_regnum
, value
))
312 LOG_DEBUG("writing register %i(%s) with value 0x%8.8" PRIx32
,
313 reg_arch_info
->num
, reg
->name
, value
);
315 if ((nds32
->fpu_enable
== false) &&
316 (NDS32_REG_TYPE_FPU
== nds32_reg_type(mapped_regnum
))) {
318 buf_set_u32(reg
->value
, 0, 32, 0);
319 } else if ((nds32
->audio_enable
== false) &&
320 (NDS32_REG_TYPE_AUMR
== nds32_reg_type(mapped_regnum
))) {
322 buf_set_u32(reg
->value
, 0, 32, 0);
324 buf_set_u32(reg
->value
, 0, 32, value
);
325 aice_write_register(aice
, mapped_regnum
, reg_arch_info
->value
);
327 /* After set value to registers, read the value from target
328 * to avoid W1C inconsistency. */
329 aice_read_register(aice
, mapped_regnum
, &(reg_arch_info
->value
));
335 /* update registers to take effect right now */
336 if (IR0
== mapped_regnum
) {
337 nds32_update_psw(nds32
);
338 } else if (MR0
== mapped_regnum
) {
339 nds32_update_mmu_info(nds32
);
340 } else if ((MR6
== mapped_regnum
) || (MR7
== mapped_regnum
)) {
341 /* update lm information */
342 nds32_update_lm_info(nds32
);
343 } else if (MR8
== mapped_regnum
) {
344 nds32_update_cache_info(nds32
);
345 } else if (FUCPR
== mapped_regnum
) {
346 /* update audio/fpu setting */
347 nds32_check_extension(nds32
);
353 static int nds32_set_core_reg_64(struct reg
*reg
, uint8_t *buf
)
355 struct nds32_reg
*reg_arch_info
= reg
->arch_info
;
356 struct target
*target
= reg_arch_info
->target
;
357 struct nds32
*nds32
= target_to_nds32(target
);
358 uint32_t low_part
= buf_get_u32(buf
, 0, 32);
359 uint32_t high_part
= buf_get_u32(buf
, 32, 32);
361 if (target
->state
!= TARGET_HALTED
) {
362 LOG_ERROR("Target not halted");
363 return ERROR_TARGET_NOT_HALTED
;
366 if ((nds32
->fpu_enable
== false) &&
367 ((FD0
<= reg_arch_info
->num
) && (reg_arch_info
->num
<= FD31
))) {
369 buf_set_u32(reg
->value
, 0, 32, 0);
370 buf_set_u32(reg
->value
, 32, 32, 0);
375 buf_set_u32(reg
->value
, 0, 32, low_part
);
376 buf_set_u32(reg
->value
, 32, 32, high_part
);
385 static const struct reg_arch_type nds32_reg_access_type
= {
386 .get
= nds32_get_core_reg
,
387 .set
= nds32_set_core_reg
,
390 static const struct reg_arch_type nds32_reg_access_type_64
= {
391 .get
= nds32_get_core_reg_64
,
392 .set
= nds32_set_core_reg_64
,
395 static struct reg_cache
*nds32_build_reg_cache(struct target
*target
,
398 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
399 struct reg
*reg_list
= calloc(TOTAL_REG_NUM
, sizeof(struct reg
));
400 struct nds32_reg
*reg_arch_info
= calloc(TOTAL_REG_NUM
, sizeof(struct nds32_reg
));
403 if (!cache
|| !reg_list
|| !reg_arch_info
) {
410 cache
->name
= "Andes registers";
412 cache
->reg_list
= reg_list
;
415 for (i
= 0; i
< TOTAL_REG_NUM
; i
++) {
416 reg_arch_info
[i
].num
= i
;
417 reg_arch_info
[i
].target
= target
;
418 reg_arch_info
[i
].nds32
= nds32
;
419 reg_arch_info
[i
].enable
= false;
421 reg_list
[i
].name
= nds32_reg_simple_name(i
);
422 reg_list
[i
].number
= reg_arch_info
[i
].num
;
423 reg_list
[i
].size
= nds32_reg_size(i
);
424 reg_list
[i
].arch_info
= ®_arch_info
[i
];
426 reg_list
[i
].reg_data_type
= malloc(sizeof(struct reg_data_type
));
428 if (FD0
<= reg_arch_info
[i
].num
&& reg_arch_info
[i
].num
<= FD31
) {
429 reg_list
[i
].value
= &(reg_arch_info
[i
].value_64
);
430 reg_list
[i
].type
= &nds32_reg_access_type_64
;
432 reg_list
[i
].reg_data_type
->type
= REG_TYPE_IEEE_DOUBLE
;
433 reg_list
[i
].reg_data_type
->id
= "ieee_double";
434 reg_list
[i
].group
= "float";
436 reg_list
[i
].value
= &(reg_arch_info
[i
].value
);
437 reg_list
[i
].type
= &nds32_reg_access_type
;
438 reg_list
[i
].group
= "general";
440 if ((FS0
<= reg_arch_info
[i
].num
) && (reg_arch_info
[i
].num
<= FS31
)) {
441 reg_list
[i
].reg_data_type
->type
= REG_TYPE_IEEE_SINGLE
;
442 reg_list
[i
].reg_data_type
->id
= "ieee_single";
443 reg_list
[i
].group
= "float";
444 } else if ((reg_arch_info
[i
].num
== FPCSR
) ||
445 (reg_arch_info
[i
].num
== FPCFG
)) {
446 reg_list
[i
].group
= "float";
447 } else if ((reg_arch_info
[i
].num
== R28
) ||
448 (reg_arch_info
[i
].num
== R29
) ||
449 (reg_arch_info
[i
].num
== R31
)) {
450 reg_list
[i
].reg_data_type
->type
= REG_TYPE_DATA_PTR
;
451 reg_list
[i
].reg_data_type
->id
= "data_ptr";
452 } else if ((reg_arch_info
[i
].num
== R30
) ||
453 (reg_arch_info
[i
].num
== PC
)) {
454 reg_list
[i
].reg_data_type
->type
= REG_TYPE_CODE_PTR
;
455 reg_list
[i
].reg_data_type
->id
= "code_ptr";
457 reg_list
[i
].reg_data_type
->type
= REG_TYPE_UINT32
;
458 reg_list
[i
].reg_data_type
->id
= "uint32";
462 if (R16
<= reg_arch_info
[i
].num
&& reg_arch_info
[i
].num
<= R25
)
463 reg_list
[i
].caller_save
= true;
465 reg_list
[i
].caller_save
= false;
467 reg_list
[i
].feature
= malloc(sizeof(struct reg_feature
));
469 if (R0
<= reg_arch_info
[i
].num
&& reg_arch_info
[i
].num
<= IFC_LP
)
470 reg_list
[i
].feature
->name
= "org.gnu.gdb.nds32.core";
471 else if (CR0
<= reg_arch_info
[i
].num
&& reg_arch_info
[i
].num
<= SECUR0
)
472 reg_list
[i
].feature
->name
= "org.gnu.gdb.nds32.system";
473 else if (D0L24
<= reg_arch_info
[i
].num
&& reg_arch_info
[i
].num
<= CBE3
)
474 reg_list
[i
].feature
->name
= "org.gnu.gdb.nds32.audio";
475 else if (FPCSR
<= reg_arch_info
[i
].num
&& reg_arch_info
[i
].num
<= FD31
)
476 reg_list
[i
].feature
->name
= "org.gnu.gdb.nds32.fpu";
481 nds32
->core_cache
= cache
;
486 static int nds32_reg_cache_init(struct target
*target
, struct nds32
*nds32
)
488 struct reg_cache
*cache
;
490 cache
= nds32_build_reg_cache(target
, nds32
);
494 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
499 static struct reg
*nds32_reg_current(struct nds32
*nds32
, unsigned regnum
)
503 r
= nds32
->core_cache
->reg_list
+ regnum
;
508 int nds32_full_context(struct nds32
*nds32
)
510 uint32_t value
, value_ir0
;
512 /* save $pc & $psw */
513 nds32_get_mapped_reg(nds32
, PC
, &value
);
514 nds32_get_mapped_reg(nds32
, IR0
, &value_ir0
);
516 nds32_update_psw(nds32
);
517 nds32_update_mmu_info(nds32
);
518 nds32_update_cache_info(nds32
);
519 nds32_update_lm_info(nds32
);
521 nds32_check_extension(nds32
);
526 /* get register value internally */
527 int nds32_get_mapped_reg(struct nds32
*nds32
, unsigned regnum
, uint32_t *value
)
529 struct reg_cache
*reg_cache
= nds32
->core_cache
;
532 if (regnum
> reg_cache
->num_regs
)
535 r
= nds32_reg_current(nds32
, regnum
);
537 if (ERROR_OK
!= r
->type
->get(r
))
540 *value
= buf_get_u32(r
->value
, 0, 32);
545 /** set register internally */
546 int nds32_set_mapped_reg(struct nds32
*nds32
, unsigned regnum
, uint32_t value
)
548 struct reg_cache
*reg_cache
= nds32
->core_cache
;
550 uint8_t set_value
[4];
552 if (regnum
> reg_cache
->num_regs
)
555 r
= nds32_reg_current(nds32
, regnum
);
557 buf_set_u32(set_value
, 0, 32, value
);
559 return r
->type
->set(r
, set_value
);
562 /** get general register list */
563 static int nds32_get_general_reg_list(struct nds32
*nds32
,
564 struct reg
**reg_list
[], int *reg_list_size
)
566 struct reg
*reg_current
;
570 /** freed in gdb_server.c */
571 *reg_list
= malloc(sizeof(struct reg
*) * (IFC_LP
- R0
+ 1));
574 for (i
= R0
; i
< IFC_LP
+ 1; i
++) {
575 reg_current
= nds32_reg_current(nds32
, i
);
576 if (((struct nds32_reg
*)reg_current
->arch_info
)->enable
) {
577 (*reg_list
)[current_idx
] = reg_current
;
581 *reg_list_size
= current_idx
;
586 /** get all register list */
587 static int nds32_get_all_reg_list(struct nds32
*nds32
,
588 struct reg
**reg_list
[], int *reg_list_size
)
590 struct reg_cache
*reg_cache
= nds32
->core_cache
;
591 struct reg
*reg_current
;
594 *reg_list_size
= reg_cache
->num_regs
;
596 /** freed in gdb_server.c */
597 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
599 for (i
= 0; i
< reg_cache
->num_regs
; i
++) {
600 reg_current
= nds32_reg_current(nds32
, i
);
601 reg_current
->exist
= ((struct nds32_reg
*)
602 reg_current
->arch_info
)->enable
;
603 (*reg_list
)[i
] = reg_current
;
609 /** get all register list */
610 int nds32_get_gdb_reg_list(struct target
*target
,
611 struct reg
**reg_list
[], int *reg_list_size
,
612 enum target_register_class reg_class
)
614 struct nds32
*nds32
= target_to_nds32(target
);
618 return nds32_get_all_reg_list(nds32
, reg_list
, reg_list_size
);
619 case REG_CLASS_GENERAL
:
620 return nds32_get_general_reg_list(nds32
, reg_list
, reg_list_size
);
628 static int nds32_select_memory_mode(struct target
*target
, uint32_t address
,
629 uint32_t length
, uint32_t *end_address
)
631 struct nds32
*nds32
= target_to_nds32(target
);
632 struct aice_port_s
*aice
= target_to_aice(target
);
633 struct nds32_memory
*memory
= &(nds32
->memory
);
634 struct nds32_edm
*edm
= &(nds32
->edm
);
635 uint32_t dlm_start
, dlm_end
;
636 uint32_t ilm_start
, ilm_end
;
637 uint32_t address_end
= address
+ length
;
639 /* init end_address */
640 *end_address
= address_end
;
642 if (NDS_MEMORY_ACC_CPU
== memory
->access_channel
)
645 if (edm
->access_control
== false) {
646 LOG_DEBUG("EDM does not support ACC_CTL");
650 if (edm
->direct_access_local_memory
== false) {
651 LOG_DEBUG("EDM does not support DALM");
652 aice_memory_mode(aice
, NDS_MEMORY_SELECT_MEM
);
656 if (NDS_MEMORY_SELECT_AUTO
!= memory
->mode
) {
657 LOG_DEBUG("Memory mode is not AUTO");
661 /* set default mode */
662 aice_memory_mode(aice
, NDS_MEMORY_SELECT_MEM
);
664 if ((memory
->ilm_base
!= 0) && (memory
->ilm_enable
== true)) {
665 ilm_start
= memory
->ilm_start
;
666 ilm_end
= memory
->ilm_end
;
668 /* case 1, address < ilm_start */
669 if (address
< ilm_start
) {
670 if (ilm_start
< address_end
) {
671 /* update end_address to split non-ILM from ILM */
672 *end_address
= ilm_start
;
675 aice_memory_mode(aice
, NDS_MEMORY_SELECT_MEM
);
676 } else if ((ilm_start
<= address
) && (address
< ilm_end
)) {
677 /* case 2, ilm_start <= address < ilm_end */
678 if (ilm_end
< address_end
) {
679 /* update end_address to split non-ILM from ILM */
680 *end_address
= ilm_end
;
683 aice_memory_mode(aice
, NDS_MEMORY_SELECT_ILM
);
684 } else { /* case 3, ilm_end <= address */
686 aice_memory_mode(aice
, NDS_MEMORY_SELECT_MEM
);
691 LOG_DEBUG("ILM is not enabled");
694 if ((memory
->dlm_base
!= 0) && (memory
->dlm_enable
== true)) {
695 dlm_start
= memory
->dlm_start
;
696 dlm_end
= memory
->dlm_end
;
698 /* case 1, address < dlm_start */
699 if (address
< dlm_start
) {
700 if (dlm_start
< address_end
) {
701 /* update end_address to split non-DLM from DLM */
702 *end_address
= dlm_start
;
705 aice_memory_mode(aice
, NDS_MEMORY_SELECT_MEM
);
706 } else if ((dlm_start
<= address
) && (address
< dlm_end
)) {
707 /* case 2, dlm_start <= address < dlm_end */
708 if (dlm_end
< address_end
) {
709 /* update end_address to split non-DLM from DLM */
710 *end_address
= dlm_end
;
713 aice_memory_mode(aice
, NDS_MEMORY_SELECT_DLM
);
714 } else { /* case 3, dlm_end <= address */
716 aice_memory_mode(aice
, NDS_MEMORY_SELECT_MEM
);
721 LOG_DEBUG("DLM is not enabled");
727 int nds32_read_buffer(struct target
*target
, uint32_t address
,
728 uint32_t size
, uint8_t *buffer
)
730 struct nds32
*nds32
= target_to_nds32(target
);
731 struct nds32_memory
*memory
= &(nds32
->memory
);
733 if ((NDS_MEMORY_ACC_CPU
== memory
->access_channel
) &&
734 (target
->state
!= TARGET_HALTED
)) {
735 LOG_WARNING("target was not halted");
736 return ERROR_TARGET_NOT_HALTED
;
739 LOG_DEBUG("READ BUFFER: ADDR %08" PRIx32
" SIZE %08" PRIx32
,
743 int retval
= ERROR_OK
;
744 struct aice_port_s
*aice
= target_to_aice(target
);
745 uint32_t end_address
;
747 if (((address
% 2) == 0) && (size
== 2)) {
748 nds32_select_memory_mode(target
, address
, 2, &end_address
);
749 return aice_read_mem_unit(aice
, address
, 2, 1, buffer
);
752 /* handle unaligned head bytes */
754 uint32_t unaligned
= 4 - (address
% 4);
756 if (unaligned
> size
)
759 nds32_select_memory_mode(target
, address
, unaligned
, &end_address
);
760 retval
= aice_read_mem_unit(aice
, address
, 1, unaligned
, buffer
);
761 if (retval
!= ERROR_OK
)
765 address
+= unaligned
;
769 /* handle aligned words */
771 int aligned
= size
- (size
% 4);
775 nds32_select_memory_mode(target
, address
, aligned
, &end_address
);
777 read_len
= end_address
- address
;
780 retval
= aice_read_mem_bulk(aice
, address
, read_len
, buffer
);
782 retval
= aice_read_mem_unit(aice
, address
, 4, read_len
/ 4, buffer
);
784 if (retval
!= ERROR_OK
)
792 } while (aligned
!= 0);
795 /*prevent byte access when possible (avoid AHB access limitations in some cases)*/
797 int aligned
= size
- (size
% 2);
798 nds32_select_memory_mode(target
, address
, aligned
, &end_address
);
799 retval
= aice_read_mem_unit(aice
, address
, 2, aligned
/ 2, buffer
);
800 if (retval
!= ERROR_OK
)
807 /* handle tail writes of less than 4 bytes */
809 nds32_select_memory_mode(target
, address
, size
, &end_address
);
810 retval
= aice_read_mem_unit(aice
, address
, 1, size
, buffer
);
811 if (retval
!= ERROR_OK
)
818 int nds32_read_memory(struct target
*target
, uint32_t address
,
819 uint32_t size
, uint32_t count
, uint8_t *buffer
)
821 struct aice_port_s
*aice
= target_to_aice(target
);
823 return aice_read_mem_unit(aice
, address
, size
, count
, buffer
);
826 int nds32_read_phys_memory(struct target
*target
, uint32_t address
,
827 uint32_t size
, uint32_t count
, uint8_t *buffer
)
829 struct aice_port_s
*aice
= target_to_aice(target
);
830 struct nds32
*nds32
= target_to_nds32(target
);
831 struct nds32_memory
*memory
= &(nds32
->memory
);
832 enum nds_memory_access orig_channel
;
835 /* switch to BUS access mode to skip MMU */
836 orig_channel
= memory
->access_channel
;
837 memory
->access_channel
= NDS_MEMORY_ACC_BUS
;
838 aice_memory_access(aice
, memory
->access_channel
);
840 /* The input address is physical address. No need to do address translation. */
841 result
= aice_read_mem_unit(aice
, address
, size
, count
, buffer
);
843 /* restore to origin access mode */
844 memory
->access_channel
= orig_channel
;
845 aice_memory_access(aice
, memory
->access_channel
);
850 int nds32_write_buffer(struct target
*target
, uint32_t address
,
851 uint32_t size
, const uint8_t *buffer
)
853 struct nds32
*nds32
= target_to_nds32(target
);
854 struct nds32_memory
*memory
= &(nds32
->memory
);
856 if ((NDS_MEMORY_ACC_CPU
== memory
->access_channel
) &&
857 (target
->state
!= TARGET_HALTED
)) {
858 LOG_WARNING("target was not halted");
859 return ERROR_TARGET_NOT_HALTED
;
862 LOG_DEBUG("WRITE BUFFER: ADDR %08" PRIx32
" SIZE %08" PRIx32
,
866 struct aice_port_s
*aice
= target_to_aice(target
);
867 int retval
= ERROR_OK
;
868 uint32_t end_address
;
870 if (((address
% 2) == 0) && (size
== 2)) {
871 nds32_select_memory_mode(target
, address
, 2, &end_address
);
872 return aice_write_mem_unit(aice
, address
, 2, 1, buffer
);
875 /* handle unaligned head bytes */
877 uint32_t unaligned
= 4 - (address
% 4);
879 if (unaligned
> size
)
882 nds32_select_memory_mode(target
, address
, unaligned
, &end_address
);
883 retval
= aice_write_mem_unit(aice
, address
, 1, unaligned
, buffer
);
884 if (retval
!= ERROR_OK
)
888 address
+= unaligned
;
892 /* handle aligned words */
894 int aligned
= size
- (size
% 4);
898 nds32_select_memory_mode(target
, address
, aligned
, &end_address
);
900 write_len
= end_address
- address
;
902 retval
= aice_write_mem_bulk(aice
, address
, write_len
, buffer
);
904 retval
= aice_write_mem_unit(aice
, address
, 4, write_len
/ 4, buffer
);
905 if (retval
!= ERROR_OK
)
909 address
+= write_len
;
911 aligned
-= write_len
;
913 } while (aligned
!= 0);
916 /* handle tail writes of less than 4 bytes */
918 nds32_select_memory_mode(target
, address
, size
, &end_address
);
919 retval
= aice_write_mem_unit(aice
, address
, 1, size
, buffer
);
920 if (retval
!= ERROR_OK
)
927 int nds32_write_memory(struct target
*target
, uint32_t address
,
928 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
930 struct aice_port_s
*aice
= target_to_aice(target
);
932 return aice_write_mem_unit(aice
, address
, size
, count
, buffer
);
935 int nds32_write_phys_memory(struct target
*target
, uint32_t address
,
936 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
938 struct aice_port_s
*aice
= target_to_aice(target
);
939 struct nds32
*nds32
= target_to_nds32(target
);
940 struct nds32_memory
*memory
= &(nds32
->memory
);
941 enum nds_memory_access orig_channel
;
944 /* switch to BUS access mode to skip MMU */
945 orig_channel
= memory
->access_channel
;
946 memory
->access_channel
= NDS_MEMORY_ACC_BUS
;
947 aice_memory_access(aice
, memory
->access_channel
);
949 /* The input address is physical address. No need to do address translation. */
950 result
= aice_write_mem_unit(aice
, address
, size
, count
, buffer
);
952 /* restore to origin access mode */
953 memory
->access_channel
= orig_channel
;
954 aice_memory_access(aice
, memory
->access_channel
);
959 int nds32_mmu(struct target
*target
, int *enabled
)
961 if (target
->state
!= TARGET_HALTED
) {
962 LOG_ERROR("%s: target not halted", __func__
);
963 return ERROR_TARGET_INVALID
;
966 struct nds32
*nds32
= target_to_nds32(target
);
967 struct nds32_memory
*memory
= &(nds32
->memory
);
968 struct nds32_mmu_config
*mmu_config
= &(nds32
->mmu_config
);
970 if ((mmu_config
->memory_protection
== 2) && (memory
->address_translation
== true))
978 int nds32_arch_state(struct target
*target
)
980 struct nds32
*nds32
= target_to_nds32(target
);
982 if (nds32
->common_magic
!= NDS32_COMMON_MAGIC
) {
983 LOG_ERROR("BUG: called for a non-Andes target");
987 uint32_t value_pc
, value_psw
;
989 nds32_get_mapped_reg(nds32
, PC
, &value_pc
);
990 nds32_get_mapped_reg(nds32
, IR0
, &value_psw
);
992 LOG_USER("target halted due to %s\n"
993 "psw: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"%s",
994 debug_reason_name(target
),
997 nds32
->virtual_hosting
? ", virtual hosting" : "");
999 /* save pc value to pseudo register pc */
1000 struct reg
*reg
= register_get_by_name(target
->reg_cache
, "pc", 1);
1001 buf_set_u32(reg
->value
, 0, 32, value_pc
);
1006 static void nds32_init_must_have_registers(struct nds32
*nds32
)
1008 struct reg_cache
*reg_cache
= nds32
->core_cache
;
1010 /** MUST have general registers */
1011 ((struct nds32_reg
*)reg_cache
->reg_list
[R0
].arch_info
)->enable
= true;
1012 ((struct nds32_reg
*)reg_cache
->reg_list
[R1
].arch_info
)->enable
= true;
1013 ((struct nds32_reg
*)reg_cache
->reg_list
[R2
].arch_info
)->enable
= true;
1014 ((struct nds32_reg
*)reg_cache
->reg_list
[R3
].arch_info
)->enable
= true;
1015 ((struct nds32_reg
*)reg_cache
->reg_list
[R4
].arch_info
)->enable
= true;
1016 ((struct nds32_reg
*)reg_cache
->reg_list
[R5
].arch_info
)->enable
= true;
1017 ((struct nds32_reg
*)reg_cache
->reg_list
[R6
].arch_info
)->enable
= true;
1018 ((struct nds32_reg
*)reg_cache
->reg_list
[R7
].arch_info
)->enable
= true;
1019 ((struct nds32_reg
*)reg_cache
->reg_list
[R8
].arch_info
)->enable
= true;
1020 ((struct nds32_reg
*)reg_cache
->reg_list
[R9
].arch_info
)->enable
= true;
1021 ((struct nds32_reg
*)reg_cache
->reg_list
[R10
].arch_info
)->enable
= true;
1022 ((struct nds32_reg
*)reg_cache
->reg_list
[R15
].arch_info
)->enable
= true;
1023 ((struct nds32_reg
*)reg_cache
->reg_list
[R28
].arch_info
)->enable
= true;
1024 ((struct nds32_reg
*)reg_cache
->reg_list
[R29
].arch_info
)->enable
= true;
1025 ((struct nds32_reg
*)reg_cache
->reg_list
[R30
].arch_info
)->enable
= true;
1026 ((struct nds32_reg
*)reg_cache
->reg_list
[R31
].arch_info
)->enable
= true;
1027 ((struct nds32_reg
*)reg_cache
->reg_list
[PC
].arch_info
)->enable
= true;
1029 /** MUST have configuration system registers */
1030 ((struct nds32_reg
*)reg_cache
->reg_list
[CR0
].arch_info
)->enable
= true;
1031 ((struct nds32_reg
*)reg_cache
->reg_list
[CR1
].arch_info
)->enable
= true;
1032 ((struct nds32_reg
*)reg_cache
->reg_list
[CR2
].arch_info
)->enable
= true;
1033 ((struct nds32_reg
*)reg_cache
->reg_list
[CR3
].arch_info
)->enable
= true;
1034 ((struct nds32_reg
*)reg_cache
->reg_list
[CR4
].arch_info
)->enable
= true;
1036 /** MUST have interrupt system registers */
1037 ((struct nds32_reg
*)reg_cache
->reg_list
[IR0
].arch_info
)->enable
= true;
1038 ((struct nds32_reg
*)reg_cache
->reg_list
[IR1
].arch_info
)->enable
= true;
1039 ((struct nds32_reg
*)reg_cache
->reg_list
[IR3
].arch_info
)->enable
= true;
1040 ((struct nds32_reg
*)reg_cache
->reg_list
[IR4
].arch_info
)->enable
= true;
1041 ((struct nds32_reg
*)reg_cache
->reg_list
[IR6
].arch_info
)->enable
= true;
1042 ((struct nds32_reg
*)reg_cache
->reg_list
[IR9
].arch_info
)->enable
= true;
1043 ((struct nds32_reg
*)reg_cache
->reg_list
[IR11
].arch_info
)->enable
= true;
1044 ((struct nds32_reg
*)reg_cache
->reg_list
[IR14
].arch_info
)->enable
= true;
1045 ((struct nds32_reg
*)reg_cache
->reg_list
[IR15
].arch_info
)->enable
= true;
1047 /** MUST have MMU system registers */
1048 ((struct nds32_reg
*)reg_cache
->reg_list
[MR0
].arch_info
)->enable
= true;
1050 /** MUST have EDM system registers */
1051 ((struct nds32_reg
*)reg_cache
->reg_list
[DR40
].arch_info
)->enable
= true;
1052 ((struct nds32_reg
*)reg_cache
->reg_list
[DR42
].arch_info
)->enable
= true;
1055 static int nds32_init_memory_config(struct nds32
*nds32
)
1057 uint32_t value_cr1
; /* ICM_CFG */
1058 uint32_t value_cr2
; /* DCM_CFG */
1059 struct nds32_memory
*memory
= &(nds32
->memory
);
1061 /* read $cr1 to init instruction memory information */
1062 nds32_get_mapped_reg(nds32
, CR1
, &value_cr1
);
1063 memory
->icache
.set
= value_cr1
& 0x7;
1064 memory
->icache
.way
= (value_cr1
>> 3) & 0x7;
1065 memory
->icache
.line_size
= (value_cr1
>> 6) & 0x7;
1066 memory
->icache
.lock_support
= (value_cr1
>> 9) & 0x1;
1068 memory
->ilm_base
= (value_cr1
>> 10) & 0x7;
1069 memory
->ilm_align_ver
= (value_cr1
>> 13) & 0x3;
1071 /* read $cr2 to init data memory information */
1072 nds32_get_mapped_reg(nds32
, CR2
, &value_cr2
);
1073 memory
->dcache
.set
= value_cr2
& 0x7;
1074 memory
->dcache
.way
= (value_cr2
>> 3) & 0x7;
1075 memory
->dcache
.line_size
= (value_cr2
>> 6) & 0x7;
1076 memory
->dcache
.lock_support
= (value_cr2
>> 9) & 0x1;
1078 memory
->dlm_base
= (value_cr2
>> 10) & 0x7;
1079 memory
->dlm_align_ver
= (value_cr2
>> 13) & 0x3;
1084 static void nds32_init_config(struct nds32
*nds32
)
1089 struct nds32_cpu_version
*cpu_version
= &(nds32
->cpu_version
);
1090 struct nds32_mmu_config
*mmu_config
= &(nds32
->mmu_config
);
1091 struct nds32_misc_config
*misc_config
= &(nds32
->misc_config
);
1093 nds32_get_mapped_reg(nds32
, CR0
, &value_cr0
);
1094 nds32_get_mapped_reg(nds32
, CR3
, &value_cr3
);
1095 nds32_get_mapped_reg(nds32
, CR4
, &value_cr4
);
1097 /* config cpu version */
1098 cpu_version
->performance_extension
= value_cr0
& 0x1;
1099 cpu_version
->_16bit_extension
= (value_cr0
>> 1) & 0x1;
1100 cpu_version
->performance_extension_2
= (value_cr0
>> 2) & 0x1;
1101 cpu_version
->cop_fpu_extension
= (value_cr0
>> 3) & 0x1;
1102 cpu_version
->string_extension
= (value_cr0
>> 4) & 0x1;
1103 cpu_version
->revision
= (value_cr0
>> 16) & 0xFF;
1104 cpu_version
->cpu_id_family
= (value_cr0
>> 24) & 0xF;
1105 cpu_version
->cpu_id_version
= (value_cr0
>> 28) & 0xF;
1108 mmu_config
->memory_protection
= value_cr3
& 0x3;
1109 mmu_config
->memory_protection_version
= (value_cr3
>> 2) & 0x1F;
1110 mmu_config
->fully_associative_tlb
= (value_cr3
>> 7) & 0x1;
1111 if (mmu_config
->fully_associative_tlb
) {
1112 mmu_config
->tlb_size
= (value_cr3
>> 8) & 0x7F;
1114 mmu_config
->tlb_ways
= (value_cr3
>> 8) & 0x7;
1115 mmu_config
->tlb_sets
= (value_cr3
>> 11) & 0x7;
1117 mmu_config
->_8k_page_support
= (value_cr3
>> 15) & 0x1;
1118 mmu_config
->extra_page_size_support
= (value_cr3
>> 16) & 0xFF;
1119 mmu_config
->tlb_lock
= (value_cr3
>> 24) & 0x1;
1120 mmu_config
->hardware_page_table_walker
= (value_cr3
>> 25) & 0x1;
1121 mmu_config
->default_endian
= (value_cr3
>> 26) & 0x1;
1122 mmu_config
->partition_num
= (value_cr3
>> 27) & 0x1;
1123 mmu_config
->invisible_tlb
= (value_cr3
>> 28) & 0x1;
1124 mmu_config
->vlpt
= (value_cr3
>> 29) & 0x1;
1125 mmu_config
->ntme
= (value_cr3
>> 30) & 0x1;
1126 mmu_config
->drde
= (value_cr3
>> 31) & 0x1;
1129 misc_config
->edm
= value_cr4
& 0x1;
1130 misc_config
->local_memory_dma
= (value_cr4
>> 1) & 0x1;
1131 misc_config
->performance_monitor
= (value_cr4
>> 2) & 0x1;
1132 misc_config
->high_speed_memory_port
= (value_cr4
>> 3) & 0x1;
1133 misc_config
->debug_tracer
= (value_cr4
>> 4) & 0x1;
1134 misc_config
->div_instruction
= (value_cr4
>> 5) & 0x1;
1135 misc_config
->mac_instruction
= (value_cr4
>> 6) & 0x1;
1136 misc_config
->audio_isa
= (value_cr4
>> 7) & 0x3;
1137 misc_config
->L2_cache
= (value_cr4
>> 9) & 0x1;
1138 misc_config
->reduce_register
= (value_cr4
>> 10) & 0x1;
1139 misc_config
->addr_24
= (value_cr4
>> 11) & 0x1;
1140 misc_config
->interruption_level
= (value_cr4
>> 12) & 0x1;
1141 misc_config
->baseline_instruction
= (value_cr4
>> 13) & 0x7;
1142 misc_config
->no_dx_register
= (value_cr4
>> 16) & 0x1;
1143 misc_config
->implement_dependant_register
= (value_cr4
>> 17) & 0x1;
1144 misc_config
->implement_dependant_sr_encoding
= (value_cr4
>> 18) & 0x1;
1145 misc_config
->ifc
= (value_cr4
>> 19) & 0x1;
1146 misc_config
->mcu
= (value_cr4
>> 20) & 0x1;
1147 misc_config
->shadow
= (value_cr4
>> 21) & 0x7;
1148 misc_config
->ex9
= (value_cr4
>> 24) & 0x1;
1150 nds32_init_memory_config(nds32
);
1153 static int nds32_init_option_registers(struct nds32
*nds32
)
1155 struct reg_cache
*reg_cache
= nds32
->core_cache
;
1156 struct nds32_cpu_version
*cpu_version
= &(nds32
->cpu_version
);
1157 struct nds32_mmu_config
*mmu_config
= &(nds32
->mmu_config
);
1158 struct nds32_misc_config
*misc_config
= &(nds32
->misc_config
);
1159 struct nds32_memory
*memory_config
= &(nds32
->memory
);
1165 if (((cpu_version
->cpu_id_family
== 0xC) || (cpu_version
->cpu_id_family
== 0xD)) &&
1166 ((cpu_version
->revision
& 0xFC) == 0)) {
1176 if (misc_config
->reduce_register
== false) {
1177 ((struct nds32_reg
*)reg_cache
->reg_list
[R11
].arch_info
)->enable
= true;
1178 ((struct nds32_reg
*)reg_cache
->reg_list
[R12
].arch_info
)->enable
= true;
1179 ((struct nds32_reg
*)reg_cache
->reg_list
[R13
].arch_info
)->enable
= true;
1180 ((struct nds32_reg
*)reg_cache
->reg_list
[R14
].arch_info
)->enable
= true;
1181 ((struct nds32_reg
*)reg_cache
->reg_list
[R16
].arch_info
)->enable
= true;
1182 ((struct nds32_reg
*)reg_cache
->reg_list
[R17
].arch_info
)->enable
= true;
1183 ((struct nds32_reg
*)reg_cache
->reg_list
[R18
].arch_info
)->enable
= true;
1184 ((struct nds32_reg
*)reg_cache
->reg_list
[R19
].arch_info
)->enable
= true;
1185 ((struct nds32_reg
*)reg_cache
->reg_list
[R20
].arch_info
)->enable
= true;
1186 ((struct nds32_reg
*)reg_cache
->reg_list
[R21
].arch_info
)->enable
= true;
1187 ((struct nds32_reg
*)reg_cache
->reg_list
[R22
].arch_info
)->enable
= true;
1188 ((struct nds32_reg
*)reg_cache
->reg_list
[R23
].arch_info
)->enable
= true;
1189 ((struct nds32_reg
*)reg_cache
->reg_list
[R24
].arch_info
)->enable
= true;
1190 ((struct nds32_reg
*)reg_cache
->reg_list
[R25
].arch_info
)->enable
= true;
1191 ((struct nds32_reg
*)reg_cache
->reg_list
[R26
].arch_info
)->enable
= true;
1192 ((struct nds32_reg
*)reg_cache
->reg_list
[R27
].arch_info
)->enable
= true;
1195 if (misc_config
->no_dx_register
== false) {
1196 ((struct nds32_reg
*)reg_cache
->reg_list
[D0LO
].arch_info
)->enable
= true;
1197 ((struct nds32_reg
*)reg_cache
->reg_list
[D0HI
].arch_info
)->enable
= true;
1198 ((struct nds32_reg
*)reg_cache
->reg_list
[D1LO
].arch_info
)->enable
= true;
1199 ((struct nds32_reg
*)reg_cache
->reg_list
[D1HI
].arch_info
)->enable
= true;
1202 if (misc_config
->ex9
)
1203 ((struct nds32_reg
*)reg_cache
->reg_list
[ITB
].arch_info
)->enable
= true;
1205 if (no_cr5
== false)
1206 ((struct nds32_reg
*)reg_cache
->reg_list
[CR5
].arch_info
)->enable
= true;
1208 if (cpu_version
->cop_fpu_extension
) {
1209 ((struct nds32_reg
*)reg_cache
->reg_list
[CR6
].arch_info
)->enable
= true;
1210 ((struct nds32_reg
*)reg_cache
->reg_list
[FPCSR
].arch_info
)->enable
= true;
1211 ((struct nds32_reg
*)reg_cache
->reg_list
[FPCFG
].arch_info
)->enable
= true;
1214 if (mmu_config
->memory_protection
== 1) {
1215 /* Secure MPU has no IPC, IPSW, P_ITYPE */
1216 ((struct nds32_reg
*)reg_cache
->reg_list
[IR1
].arch_info
)->enable
= false;
1217 ((struct nds32_reg
*)reg_cache
->reg_list
[IR9
].arch_info
)->enable
= false;
1220 if (nds32
->privilege_level
!= 0)
1221 ((struct nds32_reg
*)reg_cache
->reg_list
[IR3
].arch_info
)->enable
= false;
1223 if (misc_config
->mcu
== true)
1224 ((struct nds32_reg
*)reg_cache
->reg_list
[IR4
].arch_info
)->enable
= false;
1226 if (misc_config
->interruption_level
== false) {
1227 ((struct nds32_reg
*)reg_cache
->reg_list
[IR2
].arch_info
)->enable
= true;
1228 ((struct nds32_reg
*)reg_cache
->reg_list
[IR5
].arch_info
)->enable
= true;
1229 ((struct nds32_reg
*)reg_cache
->reg_list
[IR10
].arch_info
)->enable
= true;
1230 ((struct nds32_reg
*)reg_cache
->reg_list
[IR12
].arch_info
)->enable
= true;
1231 ((struct nds32_reg
*)reg_cache
->reg_list
[IR13
].arch_info
)->enable
= true;
1233 /* Secure MPU has no IPC, IPSW, P_ITYPE */
1234 if (mmu_config
->memory_protection
!= 1)
1235 ((struct nds32_reg
*)reg_cache
->reg_list
[IR7
].arch_info
)->enable
= true;
1238 if ((cpu_version
->cpu_id_family
== 0x9) ||
1239 (cpu_version
->cpu_id_family
== 0xA) ||
1240 (cpu_version
->cpu_id_family
== 0xC) ||
1241 (cpu_version
->cpu_id_family
== 0xD))
1242 ((struct nds32_reg
*)reg_cache
->reg_list
[IR8
].arch_info
)->enable
= true;
1244 if (misc_config
->shadow
== 1) {
1245 ((struct nds32_reg
*)reg_cache
->reg_list
[IR16
].arch_info
)->enable
= true;
1246 ((struct nds32_reg
*)reg_cache
->reg_list
[IR17
].arch_info
)->enable
= true;
1249 if (misc_config
->ifc
)
1250 ((struct nds32_reg
*)reg_cache
->reg_list
[IFC_LP
].arch_info
)->enable
= true;
1252 if (nds32
->privilege_level
!= 0)
1253 ((struct nds32_reg
*)reg_cache
->reg_list
[MR0
].arch_info
)->enable
= false;
1255 if (mmu_config
->memory_protection
== 1) {
1256 if (mmu_config
->memory_protection_version
== 24)
1257 ((struct nds32_reg
*)reg_cache
->reg_list
[MR4
].arch_info
)->enable
= true;
1259 if (nds32
->privilege_level
== 0) {
1260 if ((mmu_config
->memory_protection_version
== 16) ||
1261 (mmu_config
->memory_protection_version
== 24)) {
1262 ((struct nds32_reg
*)reg_cache
->reg_list
[MR11
].arch_info
)->enable
= true;
1263 ((struct nds32_reg
*)reg_cache
->reg_list
[SECUR0
].arch_info
)->enable
= true;
1264 ((struct nds32_reg
*)reg_cache
->reg_list
[IR20
].arch_info
)->enable
= true;
1265 ((struct nds32_reg
*)reg_cache
->reg_list
[IR22
].arch_info
)->enable
= true;
1266 ((struct nds32_reg
*)reg_cache
->reg_list
[IR24
].arch_info
)->enable
= true;
1267 ((struct nds32_reg
*)reg_cache
->reg_list
[IR30
].arch_info
)->enable
= true;
1269 if (misc_config
->shadow
== 1) {
1270 ((struct nds32_reg
*)reg_cache
->reg_list
[IR21
].arch_info
)->enable
= true;
1271 ((struct nds32_reg
*)reg_cache
->reg_list
[IR23
].arch_info
)->enable
= true;
1272 ((struct nds32_reg
*)reg_cache
->reg_list
[IR25
].arch_info
)->enable
= true;
1276 } else if (mmu_config
->memory_protection
== 2) {
1277 ((struct nds32_reg
*)reg_cache
->reg_list
[MR1
].arch_info
)->enable
= true;
1278 ((struct nds32_reg
*)reg_cache
->reg_list
[MR4
].arch_info
)->enable
= true;
1280 if ((cpu_version
->cpu_id_family
!= 0xA) && (cpu_version
->cpu_id_family
!= 0xC) &&
1281 (cpu_version
->cpu_id_family
!= 0xD))
1282 ((struct nds32_reg
*)reg_cache
->reg_list
[MR5
].arch_info
)->enable
= true;
1285 if (mmu_config
->memory_protection
> 0) {
1286 ((struct nds32_reg
*)reg_cache
->reg_list
[MR2
].arch_info
)->enable
= true;
1287 ((struct nds32_reg
*)reg_cache
->reg_list
[MR3
].arch_info
)->enable
= true;
1290 if (memory_config
->ilm_base
!= 0)
1291 if (nds32
->privilege_level
== 0)
1292 ((struct nds32_reg
*)reg_cache
->reg_list
[MR6
].arch_info
)->enable
= true;
1294 if (memory_config
->dlm_base
!= 0)
1295 if (nds32
->privilege_level
== 0)
1296 ((struct nds32_reg
*)reg_cache
->reg_list
[MR7
].arch_info
)->enable
= true;
1298 if ((memory_config
->icache
.line_size
!= 0) && (memory_config
->dcache
.line_size
!= 0))
1299 ((struct nds32_reg
*)reg_cache
->reg_list
[MR8
].arch_info
)->enable
= true;
1301 if (misc_config
->high_speed_memory_port
)
1302 ((struct nds32_reg
*)reg_cache
->reg_list
[MR9
].arch_info
)->enable
= true;
1305 ((struct nds32_reg
*)reg_cache
->reg_list
[MR10
].arch_info
)->enable
= true;
1307 if (misc_config
->edm
) {
1308 int dr_reg_n
= nds32
->edm
.breakpoint_num
* 5;
1310 for (int i
= 0 ; i
< dr_reg_n
; i
++)
1311 ((struct nds32_reg
*)reg_cache
->reg_list
[DR0
+ i
].arch_info
)->enable
= true;
1313 ((struct nds32_reg
*)reg_cache
->reg_list
[DR41
].arch_info
)->enable
= true;
1314 ((struct nds32_reg
*)reg_cache
->reg_list
[DR43
].arch_info
)->enable
= true;
1315 ((struct nds32_reg
*)reg_cache
->reg_list
[DR44
].arch_info
)->enable
= true;
1316 ((struct nds32_reg
*)reg_cache
->reg_list
[DR45
].arch_info
)->enable
= true;
1319 if (misc_config
->debug_tracer
) {
1320 ((struct nds32_reg
*)reg_cache
->reg_list
[DR46
].arch_info
)->enable
= true;
1321 ((struct nds32_reg
*)reg_cache
->reg_list
[DR47
].arch_info
)->enable
= true;
1324 if (misc_config
->performance_monitor
) {
1325 ((struct nds32_reg
*)reg_cache
->reg_list
[PFR0
].arch_info
)->enable
= true;
1326 ((struct nds32_reg
*)reg_cache
->reg_list
[PFR1
].arch_info
)->enable
= true;
1327 ((struct nds32_reg
*)reg_cache
->reg_list
[PFR2
].arch_info
)->enable
= true;
1328 ((struct nds32_reg
*)reg_cache
->reg_list
[PFR3
].arch_info
)->enable
= true;
1331 if (misc_config
->local_memory_dma
) {
1332 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR0
].arch_info
)->enable
= true;
1333 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR1
].arch_info
)->enable
= true;
1334 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR2
].arch_info
)->enable
= true;
1335 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR3
].arch_info
)->enable
= true;
1336 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR4
].arch_info
)->enable
= true;
1337 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR5
].arch_info
)->enable
= true;
1338 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR6
].arch_info
)->enable
= true;
1339 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR7
].arch_info
)->enable
= true;
1340 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR8
].arch_info
)->enable
= true;
1341 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR9
].arch_info
)->enable
= true;
1342 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR10
].arch_info
)->enable
= true;
1345 if ((misc_config
->local_memory_dma
|| misc_config
->performance_monitor
) &&
1346 (no_racr0
== false))
1347 ((struct nds32_reg
*)reg_cache
->reg_list
[RACR
].arch_info
)->enable
= true;
1349 if (cpu_version
->cop_fpu_extension
|| (misc_config
->audio_isa
!= 0))
1350 ((struct nds32_reg
*)reg_cache
->reg_list
[FUCPR
].arch_info
)->enable
= true;
1352 if (misc_config
->audio_isa
!= 0) {
1353 if (misc_config
->audio_isa
> 1) {
1354 ((struct nds32_reg
*)reg_cache
->reg_list
[D0L24
].arch_info
)->enable
= true;
1355 ((struct nds32_reg
*)reg_cache
->reg_list
[D1L24
].arch_info
)->enable
= true;
1358 ((struct nds32_reg
*)reg_cache
->reg_list
[I0
].arch_info
)->enable
= true;
1359 ((struct nds32_reg
*)reg_cache
->reg_list
[I1
].arch_info
)->enable
= true;
1360 ((struct nds32_reg
*)reg_cache
->reg_list
[I2
].arch_info
)->enable
= true;
1361 ((struct nds32_reg
*)reg_cache
->reg_list
[I3
].arch_info
)->enable
= true;
1362 ((struct nds32_reg
*)reg_cache
->reg_list
[I4
].arch_info
)->enable
= true;
1363 ((struct nds32_reg
*)reg_cache
->reg_list
[I5
].arch_info
)->enable
= true;
1364 ((struct nds32_reg
*)reg_cache
->reg_list
[I6
].arch_info
)->enable
= true;
1365 ((struct nds32_reg
*)reg_cache
->reg_list
[I7
].arch_info
)->enable
= true;
1366 ((struct nds32_reg
*)reg_cache
->reg_list
[M1
].arch_info
)->enable
= true;
1367 ((struct nds32_reg
*)reg_cache
->reg_list
[M2
].arch_info
)->enable
= true;
1368 ((struct nds32_reg
*)reg_cache
->reg_list
[M3
].arch_info
)->enable
= true;
1369 ((struct nds32_reg
*)reg_cache
->reg_list
[M5
].arch_info
)->enable
= true;
1370 ((struct nds32_reg
*)reg_cache
->reg_list
[M6
].arch_info
)->enable
= true;
1371 ((struct nds32_reg
*)reg_cache
->reg_list
[M7
].arch_info
)->enable
= true;
1372 ((struct nds32_reg
*)reg_cache
->reg_list
[MOD
].arch_info
)->enable
= true;
1373 ((struct nds32_reg
*)reg_cache
->reg_list
[LBE
].arch_info
)->enable
= true;
1374 ((struct nds32_reg
*)reg_cache
->reg_list
[LE
].arch_info
)->enable
= true;
1375 ((struct nds32_reg
*)reg_cache
->reg_list
[LC
].arch_info
)->enable
= true;
1376 ((struct nds32_reg
*)reg_cache
->reg_list
[ADM_VBASE
].arch_info
)->enable
= true;
1377 ((struct nds32_reg
*)reg_cache
->reg_list
[SHFT_CTL0
].arch_info
)->enable
= true;
1378 ((struct nds32_reg
*)reg_cache
->reg_list
[SHFT_CTL1
].arch_info
)->enable
= true;
1381 uint32_t fucpr_backup
;
1382 /* enable fpu and get configuration */
1383 nds32_get_mapped_reg(nds32
, FUCPR
, &fucpr_backup
);
1384 if ((fucpr_backup
& 0x80000000) == 0)
1385 nds32_set_mapped_reg(nds32
, FUCPR
, fucpr_backup
| 0x80000000);
1386 nds32_get_mapped_reg(nds32
, MOD
, &value_mod
);
1387 /* restore origin fucpr value */
1388 if ((fucpr_backup
& 0x80000000) == 0)
1389 nds32_set_mapped_reg(nds32
, FUCPR
, fucpr_backup
);
1391 if ((value_mod
>> 6) & 0x1) {
1392 ((struct nds32_reg
*)reg_cache
->reg_list
[CB_CTL
].arch_info
)->enable
= true;
1393 ((struct nds32_reg
*)reg_cache
->reg_list
[CBB0
].arch_info
)->enable
= true;
1394 ((struct nds32_reg
*)reg_cache
->reg_list
[CBB1
].arch_info
)->enable
= true;
1395 ((struct nds32_reg
*)reg_cache
->reg_list
[CBB2
].arch_info
)->enable
= true;
1396 ((struct nds32_reg
*)reg_cache
->reg_list
[CBB3
].arch_info
)->enable
= true;
1397 ((struct nds32_reg
*)reg_cache
->reg_list
[CBE0
].arch_info
)->enable
= true;
1398 ((struct nds32_reg
*)reg_cache
->reg_list
[CBE1
].arch_info
)->enable
= true;
1399 ((struct nds32_reg
*)reg_cache
->reg_list
[CBE2
].arch_info
)->enable
= true;
1400 ((struct nds32_reg
*)reg_cache
->reg_list
[CBE3
].arch_info
)->enable
= true;
1404 if ((cpu_version
->cpu_id_family
== 0x9) ||
1405 (cpu_version
->cpu_id_family
== 0xA) ||
1406 (cpu_version
->cpu_id_family
== 0xC)) {
1408 ((struct nds32_reg
*)reg_cache
->reg_list
[IDR0
].arch_info
)->enable
= true;
1409 ((struct nds32_reg
*)reg_cache
->reg_list
[IDR1
].arch_info
)->enable
= true;
1411 if ((cpu_version
->cpu_id_family
== 0xC) && (cpu_version
->revision
== 0x0C))
1412 ((struct nds32_reg
*)reg_cache
->reg_list
[IDR0
].arch_info
)->enable
= false;
1416 uint32_t ivb_prog_pri_lvl
;
1417 uint32_t ivb_ivic_ver
;
1419 nds32_get_mapped_reg(nds32
, IR3
, &ir3_value
);
1420 ivb_prog_pri_lvl
= ir3_value
& 0x1;
1421 ivb_ivic_ver
= (ir3_value
>> 11) & 0x3;
1423 if ((ivb_prog_pri_lvl
== 1) || (ivb_ivic_ver
>= 1)) {
1424 ((struct nds32_reg
*)reg_cache
->reg_list
[IR18
].arch_info
)->enable
= true;
1425 ((struct nds32_reg
*)reg_cache
->reg_list
[IR19
].arch_info
)->enable
= true;
1428 if (ivb_ivic_ver
>= 1) {
1429 ((struct nds32_reg
*)reg_cache
->reg_list
[IR26
].arch_info
)->enable
= true;
1430 ((struct nds32_reg
*)reg_cache
->reg_list
[IR27
].arch_info
)->enable
= true;
1431 ((struct nds32_reg
*)reg_cache
->reg_list
[IR28
].arch_info
)->enable
= true;
1432 ((struct nds32_reg
*)reg_cache
->reg_list
[IR29
].arch_info
)->enable
= true;
1438 int nds32_init_register_table(struct nds32
*nds32
)
1440 nds32_init_must_have_registers(nds32
);
1445 int nds32_add_software_breakpoint(struct target
*target
,
1446 struct breakpoint
*breakpoint
)
1449 uint32_t check_data
;
1450 uint32_t break_insn
;
1452 /* check the breakpoint size */
1453 target
->type
->read_buffer(target
, breakpoint
->address
, 4, (uint8_t *)&data
);
1455 /* backup origin instruction
1456 * instruction is big-endian */
1457 if (*(char *)&data
& 0x80) { /* 16-bits instruction */
1458 breakpoint
->length
= 2;
1459 break_insn
= NDS32_BREAK_16
;
1460 } else { /* 32-bits instruction */
1461 breakpoint
->length
= 4;
1462 break_insn
= NDS32_BREAK_32
;
1465 if (breakpoint
->orig_instr
!= NULL
)
1466 free(breakpoint
->orig_instr
);
1468 breakpoint
->orig_instr
= malloc(breakpoint
->length
);
1469 memcpy(breakpoint
->orig_instr
, &data
, breakpoint
->length
);
1471 /* self-modified code */
1472 target
->type
->write_buffer(target
, breakpoint
->address
, breakpoint
->length
, (const uint8_t *)&break_insn
);
1473 /* write_back & invalidate dcache & invalidate icache */
1474 nds32_cache_sync(target
, breakpoint
->address
, breakpoint
->length
);
1476 /* read back to check */
1477 target
->type
->read_buffer(target
, breakpoint
->address
, breakpoint
->length
, (uint8_t *)&check_data
);
1478 if (memcmp(&check_data
, &break_insn
, breakpoint
->length
) == 0)
1484 int nds32_remove_software_breakpoint(struct target
*target
,
1485 struct breakpoint
*breakpoint
)
1487 uint32_t check_data
;
1488 uint32_t break_insn
;
1490 if (breakpoint
->length
== 2)
1491 break_insn
= NDS32_BREAK_16
;
1492 else if (breakpoint
->length
== 4)
1493 break_insn
= NDS32_BREAK_32
;
1497 target
->type
->read_buffer(target
, breakpoint
->address
, breakpoint
->length
,
1498 (uint8_t *)&check_data
);
1500 /* break instruction is modified */
1501 if (memcmp(&check_data
, &break_insn
, breakpoint
->length
) != 0)
1504 /* self-modified code */
1505 target
->type
->write_buffer(target
, breakpoint
->address
, breakpoint
->length
,
1506 breakpoint
->orig_instr
);
1508 /* write_back & invalidate dcache & invalidate icache */
1509 nds32_cache_sync(target
, breakpoint
->address
, breakpoint
->length
);
1515 * Restore the processor context on an Andes target. The full processor
1516 * context is analyzed to see if any of the registers are dirty on this end, but
1517 * have a valid new value. If this is the case, the processor is changed to the
1518 * appropriate mode and the new register values are written out to the
1519 * processor. If there happens to be a dirty register with an invalid value, an
1520 * error will be logged.
1522 * @param target Pointer to the Andes target to have its context restored
1523 * @return Error status if the target is not halted.
1525 int nds32_restore_context(struct target
*target
)
1527 struct nds32
*nds32
= target_to_nds32(target
);
1528 struct aice_port_s
*aice
= target_to_aice(target
);
1529 struct reg_cache
*reg_cache
= nds32
->core_cache
;
1531 struct nds32_reg
*reg_arch_info
;
1536 if (target
->state
!= TARGET_HALTED
) {
1537 LOG_WARNING("target not halted");
1538 return ERROR_TARGET_NOT_HALTED
;
1541 /* check if there are dirty registers */
1542 for (i
= 0; i
< reg_cache
->num_regs
; i
++) {
1543 reg
= &(reg_cache
->reg_list
[i
]);
1544 if (reg
->dirty
== true) {
1545 if (reg
->valid
== true) {
1547 LOG_DEBUG("examining dirty reg: %s", reg
->name
);
1548 LOG_DEBUG("writing register %i "
1549 "with value 0x%8.8" PRIx32
, i
, buf_get_u32(reg
->value
, 0, 32));
1551 reg_arch_info
= reg
->arch_info
;
1552 if (FD0
<= reg_arch_info
->num
&& reg_arch_info
->num
<= FD31
)
1553 aice_write_reg_64(aice
, reg_arch_info
->num
, reg_arch_info
->value_64
);
1555 aice_write_register(aice
, reg_arch_info
->num
, reg_arch_info
->value
);
1565 int nds32_edm_config(struct nds32
*nds32
)
1567 struct target
*target
= nds32
->target
;
1568 struct aice_port_s
*aice
= target_to_aice(target
);
1572 aice_read_debug_reg(aice
, NDS_EDM_SR_EDM_CFG
, &edm_cfg
);
1574 nds32
->edm
.version
= (edm_cfg
>> 16) & 0xFFFF;
1575 LOG_INFO("EDM version 0x%04" PRIx32
, nds32
->edm
.version
);
1577 nds32
->edm
.breakpoint_num
= (edm_cfg
& 0x7) + 1;
1579 if ((nds32
->edm
.version
& 0x1000) || (0x60 <= nds32
->edm
.version
))
1580 nds32
->edm
.access_control
= true;
1582 nds32
->edm
.access_control
= false;
1584 if ((edm_cfg
>> 4) & 0x1)
1585 nds32
->edm
.direct_access_local_memory
= true;
1587 nds32
->edm
.direct_access_local_memory
= false;
1589 if (nds32
->edm
.version
<= 0x20)
1590 nds32
->edm
.direct_access_local_memory
= false;
1592 aice_read_debug_reg(aice
, NDS_EDM_SR_EDM_CTL
, &edm_ctl
);
1593 if (edm_ctl
& (0x1 << 29))
1594 nds32
->edm
.support_max_stop
= true;
1596 nds32
->edm
.support_max_stop
= false;
1598 /* set passcode for secure MCU */
1604 int nds32_config(struct nds32
*nds32
)
1606 nds32_init_config(nds32
);
1608 /* init optional system registers according to config registers */
1609 nds32_init_option_registers(nds32
);
1611 /* get max interrupt level */
1612 if (nds32
->misc_config
.interruption_level
)
1613 nds32
->max_interrupt_level
= 2;
1615 nds32
->max_interrupt_level
= 3;
1617 /* get ILM/DLM size from MR6/MR7 */
1618 uint32_t value_mr6
, value_mr7
;
1619 uint32_t size_index
;
1620 nds32_get_mapped_reg(nds32
, MR6
, &value_mr6
);
1621 size_index
= (value_mr6
>> 1) & 0xF;
1622 nds32
->memory
.ilm_size
= NDS32_LM_SIZE_TABLE
[size_index
];
1624 nds32_get_mapped_reg(nds32
, MR7
, &value_mr7
);
1625 size_index
= (value_mr7
>> 1) & 0xF;
1626 nds32
->memory
.dlm_size
= NDS32_LM_SIZE_TABLE
[size_index
];
1631 int nds32_init_arch_info(struct target
*target
, struct nds32
*nds32
)
1633 target
->arch_info
= nds32
;
1634 nds32
->target
= target
;
1636 nds32
->common_magic
= NDS32_COMMON_MAGIC
;
1637 nds32
->init_arch_info_after_halted
= false;
1638 nds32
->auto_convert_hw_bp
= true;
1639 nds32
->global_stop
= false;
1640 nds32
->soft_reset_halt
= false;
1641 nds32
->edm_passcode
= NULL
;
1642 nds32
->privilege_level
= 0;
1643 nds32
->boot_time
= 1500;
1644 nds32
->reset_halt_as_examine
= false;
1645 nds32
->keep_target_edm_ctl
= false;
1646 nds32
->word_access_mem
= false;
1647 nds32
->virtual_hosting
= false;
1651 if (ERROR_FAIL
== nds32_reg_cache_init(target
, nds32
))
1654 if (ERROR_OK
!= nds32_init_register_table(nds32
))
1660 int nds32_virtual_to_physical(struct target
*target
, uint32_t address
, uint32_t *physical
)
1662 struct nds32
*nds32
= target_to_nds32(target
);
1664 if (nds32
->memory
.address_translation
== false) {
1665 *physical
= address
;
1669 if (ERROR_OK
== nds32_probe_tlb(nds32
, address
, physical
))
1672 if (ERROR_OK
== nds32_walk_page_table(nds32
, address
, physical
))
1678 int nds32_cache_sync(struct target
*target
, uint32_t address
, uint32_t length
)
1680 struct aice_port_s
*aice
= target_to_aice(target
);
1681 struct nds32
*nds32
= target_to_nds32(target
);
1682 struct nds32_cache
*dcache
= &(nds32
->memory
.dcache
);
1683 struct nds32_cache
*icache
= &(nds32
->memory
.icache
);
1684 uint32_t dcache_line_size
= NDS32_LINE_SIZE_TABLE
[dcache
->line_size
];
1685 uint32_t icache_line_size
= NDS32_LINE_SIZE_TABLE
[icache
->line_size
];
1686 uint32_t cur_address
;
1688 uint32_t start_line
, end_line
;
1691 if ((dcache
->line_size
!= 0) && (dcache
->enable
== true)) {
1692 /* address / dcache_line_size */
1693 start_line
= address
>> (dcache
->line_size
+ 2);
1694 /* (address + length - 1) / dcache_line_size */
1695 end_line
= (address
+ length
- 1) >> (dcache
->line_size
+ 2);
1697 for (cur_address
= address
, cur_line
= start_line
;
1698 cur_line
<= end_line
;
1699 cur_address
+= dcache_line_size
, cur_line
++) {
1701 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_VA_WB
, cur_address
);
1702 if (result
!= ERROR_OK
)
1706 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_VA_INVAL
, cur_address
);
1707 if (result
!= ERROR_OK
)
1712 if ((icache
->line_size
!= 0) && (icache
->enable
== true)) {
1713 /* address / icache_line_size */
1714 start_line
= address
>> (icache
->line_size
+ 2);
1715 /* (address + length - 1) / icache_line_size */
1716 end_line
= (address
+ length
- 1) >> (icache
->line_size
+ 2);
1718 for (cur_address
= address
, cur_line
= start_line
;
1719 cur_line
<= end_line
;
1720 cur_address
+= icache_line_size
, cur_line
++) {
1721 /* Because PSW.IT is turned off under debug exception, address MUST
1722 * be physical address. L1I_VA_INVALIDATE uses PSW.IT to decide
1723 * address translation or not. */
1724 uint32_t physical_addr
;
1725 if (ERROR_FAIL
== target
->type
->virt2phys(target
, cur_address
,
1730 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1I_VA_INVAL
, physical_addr
);
1731 if (result
!= ERROR_OK
)
1739 uint32_t nds32_nextpc(struct nds32
*nds32
, int current
, uint32_t address
)
1742 nds32_set_mapped_reg(nds32
, PC
, address
);
1744 nds32_get_mapped_reg(nds32
, PC
, &address
);
1749 int nds32_step(struct target
*target
, int current
,
1750 uint32_t address
, int handle_breakpoints
)
1752 LOG_DEBUG("target->state: %s",
1753 target_state_name(target
));
1755 if (target
->state
!= TARGET_HALTED
) {
1756 LOG_WARNING("target was not halted");
1757 return ERROR_TARGET_NOT_HALTED
;
1760 struct nds32
*nds32
= target_to_nds32(target
);
1762 address
= nds32_nextpc(nds32
, current
, address
);
1764 LOG_DEBUG("STEP PC %08" PRIx32
"%s", address
, !current
? "!" : "");
1767 uint32_t ir14_value
;
1768 nds32_get_mapped_reg(nds32
, IR14
, &ir14_value
);
1769 if (nds32
->step_isr_enable
)
1770 ir14_value
|= (0x1 << 31);
1772 ir14_value
&= ~(0x1 << 31);
1773 nds32_set_mapped_reg(nds32
, IR14
, ir14_value
);
1775 /********* TODO: maybe create another function to handle this part */
1776 CHECK_RETVAL(nds32
->leave_debug_state(nds32
, true));
1777 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
1779 struct aice_port_s
*aice
= target_to_aice(target
);
1780 if (ERROR_OK
!= aice_step(aice
))
1784 CHECK_RETVAL(nds32
->enter_debug_state(nds32
, true));
1785 /********* TODO: maybe create another function to handle this part */
1788 if (nds32
->step_isr_enable
) {
1789 nds32_get_mapped_reg(nds32
, IR14
, &ir14_value
);
1790 ir14_value
&= ~(0x1 << 31);
1791 nds32_set_mapped_reg(nds32
, IR14
, ir14_value
);
1794 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1799 static int nds32_step_without_watchpoint(struct nds32
*nds32
)
1801 struct target
*target
= nds32
->target
;
1803 if (target
->state
!= TARGET_HALTED
) {
1804 LOG_WARNING("target was not halted");
1805 return ERROR_TARGET_NOT_HALTED
;
1809 uint32_t ir14_value
;
1810 nds32_get_mapped_reg(nds32
, IR14
, &ir14_value
);
1811 if (nds32
->step_isr_enable
)
1812 ir14_value
|= (0x1 << 31);
1814 ir14_value
&= ~(0x1 << 31);
1815 nds32_set_mapped_reg(nds32
, IR14
, ir14_value
);
1817 /********* TODO: maybe create another function to handle this part */
1818 CHECK_RETVAL(nds32
->leave_debug_state(nds32
, false));
1820 struct aice_port_s
*aice
= target_to_aice(target
);
1822 if (ERROR_OK
!= aice_step(aice
))
1826 CHECK_RETVAL(nds32
->enter_debug_state(nds32
, false));
1827 /********* TODO: maybe create another function to handle this part */
1830 if (nds32
->step_isr_enable
) {
1831 nds32_get_mapped_reg(nds32
, IR14
, &ir14_value
);
1832 ir14_value
&= ~(0x1 << 31);
1833 nds32_set_mapped_reg(nds32
, IR14
, ir14_value
);
1839 int nds32_target_state(struct nds32
*nds32
, enum target_state
*state
)
1841 struct aice_port_s
*aice
= target_to_aice(nds32
->target
);
1842 enum aice_target_state_s nds32_state
;
1844 if (aice_state(aice
, &nds32_state
) != ERROR_OK
)
1847 switch (nds32_state
) {
1848 case AICE_DISCONNECT
:
1849 LOG_INFO("USB is disconnected");
1851 case AICE_TARGET_DETACH
:
1852 LOG_INFO("Target is disconnected");
1854 case AICE_TARGET_UNKNOWN
:
1855 *state
= TARGET_UNKNOWN
;
1857 case AICE_TARGET_RUNNING
:
1858 *state
= TARGET_RUNNING
;
1860 case AICE_TARGET_HALTED
:
1861 *state
= TARGET_HALTED
;
1863 case AICE_TARGET_RESET
:
1864 *state
= TARGET_RESET
;
1866 case AICE_TARGET_DEBUG_RUNNING
:
1867 *state
= TARGET_DEBUG_RUNNING
;
1876 int nds32_examine_debug_reason(struct nds32
*nds32
)
1879 struct target
*target
= nds32
->target
;
1881 nds32
->get_debug_reason(nds32
, &reason
);
1883 LOG_DEBUG("nds32 examines debug reason: %s", nds32_debug_type_name
[reason
]);
1885 /* Examine debug reason */
1887 case NDS32_DEBUG_BREAK
:
1888 case NDS32_DEBUG_BREAK_16
:
1889 case NDS32_DEBUG_INST_BREAK
:
1893 struct nds32_instruction instruction
;
1895 nds32_get_mapped_reg(nds32
, PC
, &value_pc
);
1897 if (ERROR_OK
!= nds32_read_opcode(nds32
, value_pc
, &opcode
))
1899 if (ERROR_OK
!= nds32_evaluate_opcode(nds32
, opcode
, value_pc
,
1903 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1906 case NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE
:
1907 case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE
:
1908 case NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP
: /* GLOBAL_STOP is precise exception */
1912 result
= nds32
->get_watched_address(nds32
,
1913 &(nds32
->watched_address
), reason
);
1914 /* do single step(without watchpoints) to skip the "watched" instruction */
1915 nds32_step_without_watchpoint(nds32
);
1917 /* before single_step, save exception address */
1918 if (ERROR_OK
!= result
)
1921 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1924 case NDS32_DEBUG_DEBUG_INTERRUPT
:
1925 target
->debug_reason
= DBG_REASON_DBGRQ
;
1927 case NDS32_DEBUG_HARDWARE_SINGLE_STEP
:
1928 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1930 case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE
:
1931 case NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE
:
1932 case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE
:
1933 if (ERROR_OK
!= nds32
->get_watched_address(nds32
,
1934 &(nds32
->watched_address
), reason
))
1937 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1940 target
->debug_reason
= DBG_REASON_UNDEFINED
;
1947 int nds32_login(struct nds32
*nds32
)
1949 struct target
*target
= nds32
->target
;
1950 struct aice_port_s
*aice
= target_to_aice(target
);
1951 uint32_t passcode_length
;
1952 char command_sequence
[129];
1953 char command_str
[33];
1955 uint32_t copy_length
;
1959 LOG_DEBUG("nds32_login");
1961 if (nds32
->edm_passcode
!= NULL
) {
1962 /* convert EDM passcode to command sequences */
1963 passcode_length
= strlen(nds32
->edm_passcode
);
1964 command_sequence
[0] = '\0';
1965 for (i
= 0; i
< passcode_length
; i
+= 8) {
1966 if (passcode_length
- i
< 8)
1967 copy_length
= passcode_length
- i
;
1971 strncpy(code_str
, nds32
->edm_passcode
+ i
, copy_length
);
1972 code_str
[copy_length
] = '\0';
1973 code
= strtoul(code_str
, NULL
, 16);
1975 sprintf(command_str
, "write_misc gen_port0 0x%x;", code
);
1976 strcat(command_sequence
, command_str
);
1979 if (ERROR_OK
!= aice_program_edm(aice
, command_sequence
))
1982 /* get current privilege level */
1983 uint32_t value_edmsw
;
1984 aice_read_debug_reg(aice
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
1985 nds32
->privilege_level
= (value_edmsw
>> 16) & 0x3;
1986 LOG_INFO("Current privilege level: %d", nds32
->privilege_level
);
1989 if (nds32_edm_ops_num
> 0) {
1990 const char *reg_name
;
1991 for (i
= 0 ; i
< nds32_edm_ops_num
; i
++) {
1992 code
= nds32_edm_ops
[i
].value
;
1993 if (nds32_edm_ops
[i
].reg_no
== 6)
1994 reg_name
= "gen_port0";
1995 else if (nds32_edm_ops
[i
].reg_no
== 7)
1996 reg_name
= "gen_port1";
2000 sprintf(command_str
, "write_misc %s 0x%x;", reg_name
, code
);
2001 if (ERROR_OK
!= aice_program_edm(aice
, command_str
))
2009 int nds32_halt(struct target
*target
)
2011 struct nds32
*nds32
= target_to_nds32(target
);
2012 struct aice_port_s
*aice
= target_to_aice(target
);
2013 enum target_state state
;
2015 LOG_DEBUG("target->state: %s",
2016 target_state_name(target
));
2018 if (target
->state
== TARGET_HALTED
) {
2019 LOG_DEBUG("target was already halted");
2023 if (nds32_target_state(nds32
, &state
) != ERROR_OK
)
2026 if (TARGET_HALTED
!= state
)
2027 /* TODO: if state == TARGET_HALTED, check ETYPE is DBGI or not */
2028 if (ERROR_OK
!= aice_halt(aice
))
2031 CHECK_RETVAL(nds32
->enter_debug_state(nds32
, true));
2033 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
2038 /* poll current target status */
2039 int nds32_poll(struct target
*target
)
2041 struct nds32
*nds32
= target_to_nds32(target
);
2042 enum target_state state
;
2044 if (nds32_target_state(nds32
, &state
) != ERROR_OK
)
2047 if (state
== TARGET_HALTED
) {
2048 if (target
->state
!= TARGET_HALTED
) {
2049 /* if false_hit, continue free_run */
2050 if (ERROR_OK
!= nds32
->enter_debug_state(nds32
, true)) {
2051 struct aice_port_s
*aice
= target_to_aice(target
);
2056 LOG_DEBUG("Change target state to TARGET_HALTED.");
2058 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
2060 } else if (state
== TARGET_RESET
) {
2061 if (target
->state
== TARGET_HALTED
) {
2062 /* similar to assert srst */
2063 register_cache_invalidate(nds32
->core_cache
);
2064 target
->state
= TARGET_RESET
;
2066 /* TODO: deassert srst */
2067 } else if (target
->state
== TARGET_RUNNING
) {
2068 /* reset as running */
2069 LOG_WARNING("<-- TARGET WARNING! The debug target has been reset. -->");
2072 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
) {
2073 LOG_DEBUG("Change target state to TARGET_RUNNING.");
2074 target
->state
= TARGET_RUNNING
;
2075 target
->debug_reason
= DBG_REASON_NOTHALTED
;
2082 int nds32_resume(struct target
*target
, int current
,
2083 uint32_t address
, int handle_breakpoints
, int debug_execution
)
2085 LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
2086 current
, address
, handle_breakpoints
, debug_execution
);
2088 struct nds32
*nds32
= target_to_nds32(target
);
2090 if (target
->state
!= TARGET_HALTED
) {
2091 LOG_ERROR("Target not halted");
2092 return ERROR_TARGET_NOT_HALTED
;
2095 address
= nds32_nextpc(nds32
, current
, address
);
2097 LOG_DEBUG("RESUME PC %08" PRIx32
"%s", address
, !current
? "!" : "");
2099 if (!debug_execution
)
2100 target_free_all_working_areas(target
);
2102 /* Disable HSS to avoid users misuse HSS */
2103 if (nds32_reach_max_interrupt_level(nds32
) == false) {
2105 nds32_get_mapped_reg(nds32
, IR0
, &value_ir0
);
2106 value_ir0
&= ~(0x1 << 11);
2107 nds32_set_mapped_reg(nds32
, IR0
, value_ir0
);
2110 CHECK_RETVAL(nds32
->leave_debug_state(nds32
, true));
2111 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
2113 struct aice_port_s
*aice
= target_to_aice(target
);
2116 target
->debug_reason
= DBG_REASON_NOTHALTED
;
2117 if (!debug_execution
)
2118 target
->state
= TARGET_RUNNING
;
2120 target
->state
= TARGET_DEBUG_RUNNING
;
2122 LOG_DEBUG("target->state: %s",
2123 target_state_name(target
));
2128 int nds32_assert_reset(struct target
*target
)
2130 struct nds32
*nds32
= target_to_nds32(target
);
2131 struct aice_port_s
*aice
= target_to_aice(target
);
2133 jtag_poll_set_enabled(true);
2135 if (target
->reset_halt
) {
2136 if (nds32
->soft_reset_halt
)
2137 target
->type
->soft_reset_halt(target
);
2139 aice_assert_srst(aice
, AICE_RESET_HOLD
);
2141 aice_assert_srst(aice
, AICE_SRST
);
2142 alive_sleep(nds32
->boot_time
);
2145 /* set passcode for secure MCU after core reset */
2148 /* registers are now invalid */
2149 register_cache_invalidate(nds32
->core_cache
);
2151 target
->state
= TARGET_RESET
;
2156 static uint32_t nds32_backup_edm_ctl
;
2157 static bool gdb_attached
;
2159 static int nds32_gdb_attach(struct nds32
*nds32
)
2161 LOG_DEBUG("nds32_gdb_attach");
2163 if (gdb_attached
== false) {
2165 if (nds32
->keep_target_edm_ctl
) {
2166 /* backup target EDM_CTL */
2167 struct aice_port_s
*aice
= target_to_aice(nds32
->target
);
2168 aice_read_debug_reg(aice
, NDS_EDM_SR_EDM_CTL
, &nds32_backup_edm_ctl
);
2171 target_halt(nds32
->target
);
2172 target_poll(nds32
->target
);
2174 gdb_attached
= true;
2180 static int nds32_gdb_detach(struct nds32
*nds32
)
2182 LOG_DEBUG("nds32_gdb_detach");
2183 bool backup_virtual_hosting_setting
;
2187 backup_virtual_hosting_setting
= nds32
->virtual_hosting
;
2188 /* turn off virtual hosting before resume as gdb-detach */
2189 nds32
->virtual_hosting
= false;
2190 target_resume(nds32
->target
, 1, 0, 0, 0);
2191 nds32
->virtual_hosting
= backup_virtual_hosting_setting
;
2193 if (nds32
->keep_target_edm_ctl
) {
2194 /* restore target EDM_CTL */
2195 struct aice_port_s
*aice
= target_to_aice(nds32
->target
);
2196 aice_write_debug_reg(aice
, NDS_EDM_SR_EDM_CTL
, nds32_backup_edm_ctl
);
2199 /* turn off polling */
2200 jtag_poll_set_enabled(false);
2202 gdb_attached
= false;
2208 static int nds32_callback_event_handler(struct target
*target
,
2209 enum target_event event
, void *priv
)
2211 int retval
= ERROR_OK
;
2212 struct nds32
*nds32
= priv
;
2215 case TARGET_EVENT_GDB_ATTACH
:
2216 retval
= nds32_gdb_attach(nds32
);
2218 case TARGET_EVENT_GDB_DETACH
:
2219 retval
= nds32_gdb_detach(nds32
);
2228 int nds32_init(struct nds32
*nds32
)
2230 /* Initialize anything we can set up without talking to the target */
2231 nds32
->memory
.access_channel
= NDS_MEMORY_ACC_CPU
;
2233 /* turn off polling by default */
2234 jtag_poll_set_enabled(false);
2236 /* register event callback */
2237 target_register_event_callback(nds32_callback_event_handler
, nds32
);
2242 int nds32_reset_halt(struct nds32
*nds32
)
2244 LOG_INFO("reset halt as init");
2246 struct aice_port_s
*aice
= target_to_aice(nds32
->target
);
2247 aice_assert_srst(aice
, AICE_RESET_HOLD
);
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