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target/arm946e: change prototype of arm946e_verify_pointer()
[openocd.git] / src / target / nds32.c
1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include <helper/log.h>
24 #include <helper/binarybuffer.h>
25 #include "nds32.h"
26 #include "nds32_aice.h"
27 #include "nds32_tlb.h"
28 #include "nds32_disassembler.h"
29
30 const int NDS32_BREAK_16 = 0x00EA; /* 0xEA00 */
31 const int NDS32_BREAK_32 = 0x0A000064; /* 0x6400000A */
32
33 struct nds32_edm_operation nds32_edm_ops[NDS32_EDM_OPERATION_MAX_NUM];
34 uint32_t nds32_edm_ops_num;
35
36 const char *nds32_debug_type_name[11] = {
37 "SOFTWARE BREAK",
38 "SOFTWARE BREAK_16",
39 "HARDWARE BREAKPOINT",
40 "DATA ADDR WATCHPOINT PRECISE",
41 "DATA VALUE WATCHPOINT PRECISE",
42 "DATA VALUE WATCHPOINT IMPRECISE",
43 "DEBUG INTERRUPT",
44 "HARDWARE SINGLE STEP",
45 "DATA ADDR WATCHPOINT NEXT PRECISE",
46 "DATA VALUE WATCHPOINT NEXT PRECISE",
47 "LOAD STORE GLOBAL STOP",
48 };
49
50 static const int NDS32_LM_SIZE_TABLE[16] = {
51 4 * 1024,
52 8 * 1024,
53 16 * 1024,
54 32 * 1024,
55 64 * 1024,
56 128 * 1024,
57 256 * 1024,
58 512 * 1024,
59 1024 * 1024,
60 1 * 1024,
61 2 * 1024,
62 };
63
64 static const int NDS32_LINE_SIZE_TABLE[6] = {
65 0,
66 8,
67 16,
68 32,
69 64,
70 128,
71 };
72
73 static int nds32_get_core_reg(struct reg *reg)
74 {
75 int retval;
76 struct nds32_reg *reg_arch_info = reg->arch_info;
77 struct target *target = reg_arch_info->target;
78 struct nds32 *nds32 = target_to_nds32(target);
79 struct aice_port_s *aice = target_to_aice(target);
80
81 if (target->state != TARGET_HALTED) {
82 LOG_ERROR("Target not halted");
83 return ERROR_TARGET_NOT_HALTED;
84 }
85
86 if (reg->valid) {
87 uint32_t val = buf_get_u32(reg_arch_info->value, 0, 32);
88 LOG_DEBUG("reading register(cached) %" PRIi32 "(%s), value: 0x%8.8" PRIx32,
89 reg_arch_info->num, reg->name, val);
90 return ERROR_OK;
91 }
92
93 int mapped_regnum = nds32->register_map(nds32, reg_arch_info->num);
94
95 if (reg_arch_info->enable == false) {
96 buf_set_u32(reg_arch_info->value, 0, 32, NDS32_REGISTER_DISABLE);
97 retval = ERROR_FAIL;
98 } else {
99 uint32_t val = 0;
100 if ((nds32->fpu_enable == false)
101 && (NDS32_REG_TYPE_FPU == nds32_reg_type(mapped_regnum))) {
102 retval = ERROR_OK;
103 } else if ((nds32->audio_enable == false)
104 && (NDS32_REG_TYPE_AUMR == nds32_reg_type(mapped_regnum))) {
105 retval = ERROR_OK;
106 } else {
107 retval = aice_read_register(aice, mapped_regnum, &val);
108 }
109 buf_set_u32(reg_arch_info->value, 0, 32, val);
110
111 LOG_DEBUG("reading register %" PRIi32 "(%s), value: 0x%8.8" PRIx32,
112 reg_arch_info->num, reg->name, val);
113 }
114
115 if (retval == ERROR_OK) {
116 reg->valid = true;
117 reg->dirty = false;
118 }
119
120 return retval;
121 }
122
123 static int nds32_get_core_reg_64(struct reg *reg)
124 {
125 int retval;
126 struct nds32_reg *reg_arch_info = reg->arch_info;
127 struct target *target = reg_arch_info->target;
128 struct nds32 *nds32 = target_to_nds32(target);
129 struct aice_port_s *aice = target_to_aice(target);
130
131 if (target->state != TARGET_HALTED) {
132 LOG_ERROR("Target not halted");
133 return ERROR_TARGET_NOT_HALTED;
134 }
135
136 if (reg->valid)
137 return ERROR_OK;
138
139 if (reg_arch_info->enable == false) {
140 buf_set_u64(reg_arch_info->value, 0, 64, NDS32_REGISTER_DISABLE);
141 retval = ERROR_FAIL;
142 } else {
143 uint64_t val = 0;
144 if ((nds32->fpu_enable == false)
145 && ((FD0 <= reg_arch_info->num) && (reg_arch_info->num <= FD31))) {
146 retval = ERROR_OK;
147 } else {
148 retval = aice_read_reg_64(aice, reg_arch_info->num, &val);
149 }
150 buf_set_u64(reg_arch_info->value, 0, 64, val);
151 }
152
153 if (retval == ERROR_OK) {
154 reg->valid = true;
155 reg->dirty = false;
156 }
157
158 return retval;
159 }
160
161 static int nds32_update_psw(struct nds32 *nds32)
162 {
163 uint32_t value_ir0;
164 struct aice_port_s *aice = target_to_aice(nds32->target);
165
166 nds32_get_mapped_reg(nds32, IR0, &value_ir0);
167
168 /* Save data memory endian */
169 if ((value_ir0 >> 5) & 0x1) {
170 nds32->data_endian = TARGET_BIG_ENDIAN;
171 aice_set_data_endian(aice, AICE_BIG_ENDIAN);
172 } else {
173 nds32->data_endian = TARGET_LITTLE_ENDIAN;
174 aice_set_data_endian(aice, AICE_LITTLE_ENDIAN);
175 }
176
177 /* Save translation status */
178 nds32->memory.address_translation = ((value_ir0 >> 7) & 0x1) ? true : false;
179
180 return ERROR_OK;
181 }
182
183 static int nds32_update_mmu_info(struct nds32 *nds32)
184 {
185 uint32_t value;
186
187 /* Update MMU control status */
188 nds32_get_mapped_reg(nds32, MR0, &value);
189 nds32->mmu_config.default_min_page_size = value & 0x1;
190 nds32->mmu_config.multiple_page_size_in_use = (value >> 10) & 0x1;
191
192 return ERROR_OK;
193 }
194
195 static int nds32_update_cache_info(struct nds32 *nds32)
196 {
197 uint32_t value;
198
199 if (ERROR_OK == nds32_get_mapped_reg(nds32, MR8, &value)) {
200 if (value & 0x1)
201 nds32->memory.icache.enable = true;
202 else
203 nds32->memory.icache.enable = false;
204
205 if (value & 0x2)
206 nds32->memory.dcache.enable = true;
207 else
208 nds32->memory.dcache.enable = false;
209 } else {
210 nds32->memory.icache.enable = false;
211 nds32->memory.dcache.enable = false;
212 }
213
214 return ERROR_OK;
215 }
216
217 static int nds32_update_lm_info(struct nds32 *nds32)
218 {
219 struct nds32_memory *memory = &(nds32->memory);
220 uint32_t value_mr6;
221 uint32_t value_mr7;
222
223 nds32_get_mapped_reg(nds32, MR6, &value_mr6);
224 if (value_mr6 & 0x1)
225 memory->ilm_enable = true;
226 else
227 memory->ilm_enable = false;
228
229 if (memory->ilm_align_ver == 0) { /* 1MB aligned */
230 memory->ilm_start = value_mr6 & 0xFFF00000;
231 memory->ilm_end = memory->ilm_start + memory->ilm_size;
232 } else if (memory->ilm_align_ver == 1) { /* aligned to local memory size */
233 memory->ilm_start = value_mr6 & 0xFFFFFC00;
234 memory->ilm_end = memory->ilm_start + memory->ilm_size;
235 } else {
236 memory->ilm_start = -1;
237 memory->ilm_end = -1;
238 }
239
240 nds32_get_mapped_reg(nds32, MR7, &value_mr7);
241 if (value_mr7 & 0x1)
242 memory->dlm_enable = true;
243 else
244 memory->dlm_enable = false;
245
246 if (memory->dlm_align_ver == 0) { /* 1MB aligned */
247 memory->dlm_start = value_mr7 & 0xFFF00000;
248 memory->dlm_end = memory->dlm_start + memory->dlm_size;
249 } else if (memory->dlm_align_ver == 1) { /* aligned to local memory size */
250 memory->dlm_start = value_mr7 & 0xFFFFFC00;
251 memory->dlm_end = memory->dlm_start + memory->dlm_size;
252 } else {
253 memory->dlm_start = -1;
254 memory->dlm_end = -1;
255 }
256
257 return ERROR_OK;
258 }
259
260 /**
261 * If fpu/audio is disabled, to access fpu/audio registers will cause
262 * exceptions. So, we need to check if fpu/audio is enabled or not as
263 * target is halted. If fpu/audio is disabled, as users access fpu/audio
264 * registers, OpenOCD will return fake value 0 instead of accessing
265 * registers through DIM.
266 */
267 static int nds32_check_extension(struct nds32 *nds32)
268 {
269 uint32_t value;
270
271 nds32_get_mapped_reg(nds32, FUCPR, &value);
272 if (value == NDS32_REGISTER_DISABLE) {
273 nds32->fpu_enable = false;
274 nds32->audio_enable = false;
275 return ERROR_OK;
276 }
277
278 if (value & 0x1)
279 nds32->fpu_enable = true;
280 else
281 nds32->fpu_enable = false;
282
283 if (value & 0x80000000)
284 nds32->audio_enable = true;
285 else
286 nds32->audio_enable = false;
287
288 return ERROR_OK;
289 }
290
291 static int nds32_set_core_reg(struct reg *reg, uint8_t *buf)
292 {
293 struct nds32_reg *reg_arch_info = reg->arch_info;
294 struct target *target = reg_arch_info->target;
295 struct nds32 *nds32 = target_to_nds32(target);
296 struct aice_port_s *aice = target_to_aice(target);
297 uint32_t value = buf_get_u32(buf, 0, 32);
298
299 if (target->state != TARGET_HALTED) {
300 LOG_ERROR("Target not halted");
301 return ERROR_TARGET_NOT_HALTED;
302 }
303
304 int mapped_regnum = nds32->register_map(nds32, reg_arch_info->num);
305
306 /* ignore values that will generate exception */
307 if (nds32_reg_exception(mapped_regnum, value))
308 return ERROR_OK;
309
310 LOG_DEBUG("writing register %" PRIi32 "(%s) with value 0x%8.8" PRIx32,
311 reg_arch_info->num, reg->name, value);
312
313 if ((nds32->fpu_enable == false) &&
314 (NDS32_REG_TYPE_FPU == nds32_reg_type(mapped_regnum))) {
315
316 buf_set_u32(reg->value, 0, 32, 0);
317 } else if ((nds32->audio_enable == false) &&
318 (NDS32_REG_TYPE_AUMR == nds32_reg_type(mapped_regnum))) {
319
320 buf_set_u32(reg->value, 0, 32, 0);
321 } else {
322 buf_set_u32(reg->value, 0, 32, value);
323 uint32_t val = buf_get_u32(reg_arch_info->value, 0, 32);
324 aice_write_register(aice, mapped_regnum, val);
325
326 /* After set value to registers, read the value from target
327 * to avoid W1C inconsistency. */
328 aice_read_register(aice, mapped_regnum, &val);
329 buf_set_u32(reg_arch_info->value, 0, 32, val);
330 }
331
332 reg->valid = true;
333 reg->dirty = false;
334
335 /* update registers to take effect right now */
336 if (IR0 == mapped_regnum) {
337 nds32_update_psw(nds32);
338 } else if (MR0 == mapped_regnum) {
339 nds32_update_mmu_info(nds32);
340 } else if ((MR6 == mapped_regnum) || (MR7 == mapped_regnum)) {
341 /* update lm information */
342 nds32_update_lm_info(nds32);
343 } else if (MR8 == mapped_regnum) {
344 nds32_update_cache_info(nds32);
345 } else if (FUCPR == mapped_regnum) {
346 /* update audio/fpu setting */
347 nds32_check_extension(nds32);
348 }
349
350 return ERROR_OK;
351 }
352
353 static int nds32_set_core_reg_64(struct reg *reg, uint8_t *buf)
354 {
355 struct nds32_reg *reg_arch_info = reg->arch_info;
356 struct target *target = reg_arch_info->target;
357 struct nds32 *nds32 = target_to_nds32(target);
358 uint32_t low_part = buf_get_u32(buf, 0, 32);
359 uint32_t high_part = buf_get_u32(buf, 32, 32);
360
361 if (target->state != TARGET_HALTED) {
362 LOG_ERROR("Target not halted");
363 return ERROR_TARGET_NOT_HALTED;
364 }
365
366 if ((nds32->fpu_enable == false) &&
367 ((FD0 <= reg_arch_info->num) && (reg_arch_info->num <= FD31))) {
368
369 buf_set_u32(reg->value, 0, 32, 0);
370 buf_set_u32(reg->value, 32, 32, 0);
371
372 reg->valid = true;
373 reg->dirty = false;
374 } else {
375 buf_set_u32(reg->value, 0, 32, low_part);
376 buf_set_u32(reg->value, 32, 32, high_part);
377
378 reg->valid = true;
379 reg->dirty = true;
380 }
381
382 return ERROR_OK;
383 }
384
385 static const struct reg_arch_type nds32_reg_access_type = {
386 .get = nds32_get_core_reg,
387 .set = nds32_set_core_reg,
388 };
389
390 static const struct reg_arch_type nds32_reg_access_type_64 = {
391 .get = nds32_get_core_reg_64,
392 .set = nds32_set_core_reg_64,
393 };
394
395 static struct reg_cache *nds32_build_reg_cache(struct target *target,
396 struct nds32 *nds32)
397 {
398 struct reg_cache *cache = calloc(sizeof(struct reg_cache), 1);
399 struct reg *reg_list = calloc(TOTAL_REG_NUM, sizeof(struct reg));
400 struct nds32_reg *reg_arch_info = calloc(TOTAL_REG_NUM, sizeof(struct nds32_reg));
401 int i;
402
403 if (!cache || !reg_list || !reg_arch_info) {
404 free(cache);
405 free(reg_list);
406 free(reg_arch_info);
407 return NULL;
408 }
409
410 cache->name = "Andes registers";
411 cache->next = NULL;
412 cache->reg_list = reg_list;
413 cache->num_regs = 0;
414
415 for (i = 0; i < TOTAL_REG_NUM; i++) {
416 reg_arch_info[i].num = i;
417 reg_arch_info[i].target = target;
418 reg_arch_info[i].nds32 = nds32;
419 reg_arch_info[i].enable = false;
420
421 reg_list[i].name = nds32_reg_simple_name(i);
422 reg_list[i].number = reg_arch_info[i].num;
423 reg_list[i].size = nds32_reg_size(i);
424 reg_list[i].arch_info = &reg_arch_info[i];
425
426 reg_list[i].reg_data_type = calloc(sizeof(struct reg_data_type), 1);
427
428 if (FD0 <= reg_arch_info[i].num && reg_arch_info[i].num <= FD31) {
429 reg_list[i].value = reg_arch_info[i].value;
430 reg_list[i].type = &nds32_reg_access_type_64;
431
432 reg_list[i].reg_data_type->type = REG_TYPE_IEEE_DOUBLE;
433 reg_list[i].reg_data_type->id = "ieee_double";
434 reg_list[i].group = "float";
435 } else {
436 reg_list[i].value = reg_arch_info[i].value;
437 reg_list[i].type = &nds32_reg_access_type;
438 reg_list[i].group = "general";
439
440 if ((FS0 <= reg_arch_info[i].num) && (reg_arch_info[i].num <= FS31)) {
441 reg_list[i].reg_data_type->type = REG_TYPE_IEEE_SINGLE;
442 reg_list[i].reg_data_type->id = "ieee_single";
443 reg_list[i].group = "float";
444 } else if ((reg_arch_info[i].num == FPCSR) ||
445 (reg_arch_info[i].num == FPCFG)) {
446 reg_list[i].group = "float";
447 } else if ((reg_arch_info[i].num == R28) ||
448 (reg_arch_info[i].num == R29) ||
449 (reg_arch_info[i].num == R31)) {
450 reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
451 reg_list[i].reg_data_type->id = "data_ptr";
452 } else if ((reg_arch_info[i].num == R30) ||
453 (reg_arch_info[i].num == PC)) {
454 reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
455 reg_list[i].reg_data_type->id = "code_ptr";
456 } else {
457 reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
458 reg_list[i].reg_data_type->id = "uint32";
459 }
460 }
461
462 if (R16 <= reg_arch_info[i].num && reg_arch_info[i].num <= R25)
463 reg_list[i].caller_save = true;
464 else
465 reg_list[i].caller_save = false;
466
467 reg_list[i].feature = malloc(sizeof(struct reg_feature));
468
469 if (R0 <= reg_arch_info[i].num && reg_arch_info[i].num <= IFC_LP)
470 reg_list[i].feature->name = "org.gnu.gdb.nds32.core";
471 else if (CR0 <= reg_arch_info[i].num && reg_arch_info[i].num <= SECUR0)
472 reg_list[i].feature->name = "org.gnu.gdb.nds32.system";
473 else if (D0L24 <= reg_arch_info[i].num && reg_arch_info[i].num <= CBE3)
474 reg_list[i].feature->name = "org.gnu.gdb.nds32.audio";
475 else if (FPCSR <= reg_arch_info[i].num && reg_arch_info[i].num <= FD31)
476 reg_list[i].feature->name = "org.gnu.gdb.nds32.fpu";
477
478 cache->num_regs++;
479 }
480
481 nds32->core_cache = cache;
482
483 return cache;
484 }
485
486 static int nds32_reg_cache_init(struct target *target, struct nds32 *nds32)
487 {
488 struct reg_cache *cache;
489
490 cache = nds32_build_reg_cache(target, nds32);
491 if (!cache)
492 return ERROR_FAIL;
493
494 *register_get_last_cache_p(&target->reg_cache) = cache;
495
496 return ERROR_OK;
497 }
498
499 static struct reg *nds32_reg_current(struct nds32 *nds32, unsigned regnum)
500 {
501 struct reg *r;
502
503 r = nds32->core_cache->reg_list + regnum;
504
505 return r;
506 }
507
508 int nds32_full_context(struct nds32 *nds32)
509 {
510 uint32_t value, value_ir0;
511
512 /* save $pc & $psw */
513 nds32_get_mapped_reg(nds32, PC, &value);
514 nds32_get_mapped_reg(nds32, IR0, &value_ir0);
515
516 nds32_update_psw(nds32);
517 nds32_update_mmu_info(nds32);
518 nds32_update_cache_info(nds32);
519 nds32_update_lm_info(nds32);
520
521 nds32_check_extension(nds32);
522
523 return ERROR_OK;
524 }
525
526 /* get register value internally */
527 int nds32_get_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t *value)
528 {
529 struct reg_cache *reg_cache = nds32->core_cache;
530 struct reg *r;
531
532 if (regnum > reg_cache->num_regs)
533 return ERROR_FAIL;
534
535 r = nds32_reg_current(nds32, regnum);
536
537 if (ERROR_OK != r->type->get(r))
538 return ERROR_FAIL;
539
540 *value = buf_get_u32(r->value, 0, 32);
541
542 return ERROR_OK;
543 }
544
545 /** set register internally */
546 int nds32_set_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t value)
547 {
548 struct reg_cache *reg_cache = nds32->core_cache;
549 struct reg *r;
550 uint8_t set_value[4];
551
552 if (regnum > reg_cache->num_regs)
553 return ERROR_FAIL;
554
555 r = nds32_reg_current(nds32, regnum);
556
557 buf_set_u32(set_value, 0, 32, value);
558
559 return r->type->set(r, set_value);
560 }
561
562 /** get general register list */
563 static int nds32_get_general_reg_list(struct nds32 *nds32,
564 struct reg **reg_list[], int *reg_list_size)
565 {
566 struct reg *reg_current;
567 int i;
568 int current_idx;
569
570 /** freed in gdb_server.c */
571 *reg_list = malloc(sizeof(struct reg *) * (IFC_LP - R0 + 1));
572 current_idx = 0;
573
574 for (i = R0; i < IFC_LP + 1; i++) {
575 reg_current = nds32_reg_current(nds32, i);
576 if (((struct nds32_reg *)reg_current->arch_info)->enable) {
577 (*reg_list)[current_idx] = reg_current;
578 current_idx++;
579 }
580 }
581 *reg_list_size = current_idx;
582
583 return ERROR_OK;
584 }
585
586 /** get all register list */
587 static int nds32_get_all_reg_list(struct nds32 *nds32,
588 struct reg **reg_list[], int *reg_list_size)
589 {
590 struct reg_cache *reg_cache = nds32->core_cache;
591 struct reg *reg_current;
592 unsigned int i;
593
594 *reg_list_size = reg_cache->num_regs;
595
596 /** freed in gdb_server.c */
597 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
598
599 for (i = 0; i < reg_cache->num_regs; i++) {
600 reg_current = nds32_reg_current(nds32, i);
601 reg_current->exist = ((struct nds32_reg *)
602 reg_current->arch_info)->enable;
603 (*reg_list)[i] = reg_current;
604 }
605
606 return ERROR_OK;
607 }
608
609 /** get all register list */
610 int nds32_get_gdb_reg_list(struct target *target,
611 struct reg **reg_list[], int *reg_list_size,
612 enum target_register_class reg_class)
613 {
614 struct nds32 *nds32 = target_to_nds32(target);
615
616 switch (reg_class) {
617 case REG_CLASS_ALL:
618 return nds32_get_all_reg_list(nds32, reg_list, reg_list_size);
619 case REG_CLASS_GENERAL:
620 return nds32_get_general_reg_list(nds32, reg_list, reg_list_size);
621 default:
622 return ERROR_FAIL;
623 }
624
625 return ERROR_FAIL;
626 }
627
628 static int nds32_select_memory_mode(struct target *target, uint32_t address,
629 uint32_t length, uint32_t *end_address)
630 {
631 struct nds32 *nds32 = target_to_nds32(target);
632 struct aice_port_s *aice = target_to_aice(target);
633 struct nds32_memory *memory = &(nds32->memory);
634 struct nds32_edm *edm = &(nds32->edm);
635 uint32_t dlm_start, dlm_end;
636 uint32_t ilm_start, ilm_end;
637 uint32_t address_end = address + length;
638
639 /* init end_address */
640 *end_address = address_end;
641
642 if (NDS_MEMORY_ACC_CPU == memory->access_channel)
643 return ERROR_OK;
644
645 if (edm->access_control == false) {
646 LOG_DEBUG("EDM does not support ACC_CTL");
647 return ERROR_OK;
648 }
649
650 if (edm->direct_access_local_memory == false) {
651 LOG_DEBUG("EDM does not support DALM");
652 aice_memory_mode(aice, NDS_MEMORY_SELECT_MEM);
653 return ERROR_OK;
654 }
655
656 if (NDS_MEMORY_SELECT_AUTO != memory->mode) {
657 LOG_DEBUG("Memory mode is not AUTO");
658 return ERROR_OK;
659 }
660
661 /* set default mode */
662 aice_memory_mode(aice, NDS_MEMORY_SELECT_MEM);
663
664 if ((memory->ilm_base != 0) && (memory->ilm_enable == true)) {
665 ilm_start = memory->ilm_start;
666 ilm_end = memory->ilm_end;
667
668 /* case 1, address < ilm_start */
669 if (address < ilm_start) {
670 if (ilm_start < address_end) {
671 /* update end_address to split non-ILM from ILM */
672 *end_address = ilm_start;
673 }
674 /* MEM mode */
675 aice_memory_mode(aice, NDS_MEMORY_SELECT_MEM);
676 } else if ((ilm_start <= address) && (address < ilm_end)) {
677 /* case 2, ilm_start <= address < ilm_end */
678 if (ilm_end < address_end) {
679 /* update end_address to split non-ILM from ILM */
680 *end_address = ilm_end;
681 }
682 /* ILM mode */
683 aice_memory_mode(aice, NDS_MEMORY_SELECT_ILM);
684 } else { /* case 3, ilm_end <= address */
685 /* MEM mode */
686 aice_memory_mode(aice, NDS_MEMORY_SELECT_MEM);
687 }
688
689 return ERROR_OK;
690 } else {
691 LOG_DEBUG("ILM is not enabled");
692 }
693
694 if ((memory->dlm_base != 0) && (memory->dlm_enable == true)) {
695 dlm_start = memory->dlm_start;
696 dlm_end = memory->dlm_end;
697
698 /* case 1, address < dlm_start */
699 if (address < dlm_start) {
700 if (dlm_start < address_end) {
701 /* update end_address to split non-DLM from DLM */
702 *end_address = dlm_start;
703 }
704 /* MEM mode */
705 aice_memory_mode(aice, NDS_MEMORY_SELECT_MEM);
706 } else if ((dlm_start <= address) && (address < dlm_end)) {
707 /* case 2, dlm_start <= address < dlm_end */
708 if (dlm_end < address_end) {
709 /* update end_address to split non-DLM from DLM */
710 *end_address = dlm_end;
711 }
712 /* DLM mode */
713 aice_memory_mode(aice, NDS_MEMORY_SELECT_DLM);
714 } else { /* case 3, dlm_end <= address */
715 /* MEM mode */
716 aice_memory_mode(aice, NDS_MEMORY_SELECT_MEM);
717 }
718
719 return ERROR_OK;
720 } else {
721 LOG_DEBUG("DLM is not enabled");
722 }
723
724 return ERROR_OK;
725 }
726
727 int nds32_read_buffer(struct target *target, uint32_t address,
728 uint32_t size, uint8_t *buffer)
729 {
730 struct nds32 *nds32 = target_to_nds32(target);
731 struct nds32_memory *memory = &(nds32->memory);
732
733 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
734 (target->state != TARGET_HALTED)) {
735 LOG_WARNING("target was not halted");
736 return ERROR_TARGET_NOT_HALTED;
737 }
738
739 LOG_DEBUG("READ BUFFER: ADDR %08" PRIx32 " SIZE %08" PRIx32,
740 address,
741 size);
742
743 int retval = ERROR_OK;
744 struct aice_port_s *aice = target_to_aice(target);
745 uint32_t end_address;
746
747 if (((address % 2) == 0) && (size == 2)) {
748 nds32_select_memory_mode(target, address, 2, &end_address);
749 return aice_read_mem_unit(aice, address, 2, 1, buffer);
750 }
751
752 /* handle unaligned head bytes */
753 if (address % 4) {
754 uint32_t unaligned = 4 - (address % 4);
755
756 if (unaligned > size)
757 unaligned = size;
758
759 nds32_select_memory_mode(target, address, unaligned, &end_address);
760 retval = aice_read_mem_unit(aice, address, 1, unaligned, buffer);
761 if (retval != ERROR_OK)
762 return retval;
763
764 buffer += unaligned;
765 address += unaligned;
766 size -= unaligned;
767 }
768
769 /* handle aligned words */
770 if (size >= 4) {
771 int aligned = size - (size % 4);
772 int read_len;
773
774 do {
775 nds32_select_memory_mode(target, address, aligned, &end_address);
776
777 read_len = end_address - address;
778
779 if (read_len > 8)
780 retval = aice_read_mem_bulk(aice, address, read_len, buffer);
781 else
782 retval = aice_read_mem_unit(aice, address, 4, read_len / 4, buffer);
783
784 if (retval != ERROR_OK)
785 return retval;
786
787 buffer += read_len;
788 address += read_len;
789 size -= read_len;
790 aligned -= read_len;
791
792 } while (aligned != 0);
793 }
794
795 /*prevent byte access when possible (avoid AHB access limitations in some cases)*/
796 if (size >= 2) {
797 int aligned = size - (size % 2);
798 nds32_select_memory_mode(target, address, aligned, &end_address);
799 retval = aice_read_mem_unit(aice, address, 2, aligned / 2, buffer);
800 if (retval != ERROR_OK)
801 return retval;
802
803 buffer += aligned;
804 address += aligned;
805 size -= aligned;
806 }
807 /* handle tail writes of less than 4 bytes */
808 if (size > 0) {
809 nds32_select_memory_mode(target, address, size, &end_address);
810 retval = aice_read_mem_unit(aice, address, 1, size, buffer);
811 if (retval != ERROR_OK)
812 return retval;
813 }
814
815 return ERROR_OK;
816 }
817
818 int nds32_read_memory(struct target *target, uint32_t address,
819 uint32_t size, uint32_t count, uint8_t *buffer)
820 {
821 struct aice_port_s *aice = target_to_aice(target);
822
823 return aice_read_mem_unit(aice, address, size, count, buffer);
824 }
825
826 int nds32_read_phys_memory(struct target *target, target_addr_t address,
827 uint32_t size, uint32_t count, uint8_t *buffer)
828 {
829 struct aice_port_s *aice = target_to_aice(target);
830 struct nds32 *nds32 = target_to_nds32(target);
831 struct nds32_memory *memory = &(nds32->memory);
832 enum nds_memory_access orig_channel;
833 int result;
834
835 /* switch to BUS access mode to skip MMU */
836 orig_channel = memory->access_channel;
837 memory->access_channel = NDS_MEMORY_ACC_BUS;
838 aice_memory_access(aice, memory->access_channel);
839
840 /* The input address is physical address. No need to do address translation. */
841 result = aice_read_mem_unit(aice, address, size, count, buffer);
842
843 /* restore to origin access mode */
844 memory->access_channel = orig_channel;
845 aice_memory_access(aice, memory->access_channel);
846
847 return result;
848 }
849
850 int nds32_write_buffer(struct target *target, uint32_t address,
851 uint32_t size, const uint8_t *buffer)
852 {
853 struct nds32 *nds32 = target_to_nds32(target);
854 struct nds32_memory *memory = &(nds32->memory);
855
856 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
857 (target->state != TARGET_HALTED)) {
858 LOG_WARNING("target was not halted");
859 return ERROR_TARGET_NOT_HALTED;
860 }
861
862 LOG_DEBUG("WRITE BUFFER: ADDR %08" PRIx32 " SIZE %08" PRIx32,
863 address,
864 size);
865
866 struct aice_port_s *aice = target_to_aice(target);
867 int retval = ERROR_OK;
868 uint32_t end_address;
869
870 if (((address % 2) == 0) && (size == 2)) {
871 nds32_select_memory_mode(target, address, 2, &end_address);
872 return aice_write_mem_unit(aice, address, 2, 1, buffer);
873 }
874
875 /* handle unaligned head bytes */
876 if (address % 4) {
877 uint32_t unaligned = 4 - (address % 4);
878
879 if (unaligned > size)
880 unaligned = size;
881
882 nds32_select_memory_mode(target, address, unaligned, &end_address);
883 retval = aice_write_mem_unit(aice, address, 1, unaligned, buffer);
884 if (retval != ERROR_OK)
885 return retval;
886
887 buffer += unaligned;
888 address += unaligned;
889 size -= unaligned;
890 }
891
892 /* handle aligned words */
893 if (size >= 4) {
894 int aligned = size - (size % 4);
895 int write_len;
896
897 do {
898 nds32_select_memory_mode(target, address, aligned, &end_address);
899
900 write_len = end_address - address;
901 if (write_len > 8)
902 retval = aice_write_mem_bulk(aice, address, write_len, buffer);
903 else
904 retval = aice_write_mem_unit(aice, address, 4, write_len / 4, buffer);
905 if (retval != ERROR_OK)
906 return retval;
907
908 buffer += write_len;
909 address += write_len;
910 size -= write_len;
911 aligned -= write_len;
912
913 } while (aligned != 0);
914 }
915
916 /* handle tail writes of less than 4 bytes */
917 if (size > 0) {
918 nds32_select_memory_mode(target, address, size, &end_address);
919 retval = aice_write_mem_unit(aice, address, 1, size, buffer);
920 if (retval != ERROR_OK)
921 return retval;
922 }
923
924 return retval;
925 }
926
927 int nds32_write_memory(struct target *target, uint32_t address,
928 uint32_t size, uint32_t count, const uint8_t *buffer)
929 {
930 struct aice_port_s *aice = target_to_aice(target);
931
932 return aice_write_mem_unit(aice, address, size, count, buffer);
933 }
934
935 int nds32_write_phys_memory(struct target *target, target_addr_t address,
936 uint32_t size, uint32_t count, const uint8_t *buffer)
937 {
938 struct aice_port_s *aice = target_to_aice(target);
939 struct nds32 *nds32 = target_to_nds32(target);
940 struct nds32_memory *memory = &(nds32->memory);
941 enum nds_memory_access orig_channel;
942 int result;
943
944 /* switch to BUS access mode to skip MMU */
945 orig_channel = memory->access_channel;
946 memory->access_channel = NDS_MEMORY_ACC_BUS;
947 aice_memory_access(aice, memory->access_channel);
948
949 /* The input address is physical address. No need to do address translation. */
950 result = aice_write_mem_unit(aice, address, size, count, buffer);
951
952 /* restore to origin access mode */
953 memory->access_channel = orig_channel;
954 aice_memory_access(aice, memory->access_channel);
955
956 return result;
957 }
958
959 int nds32_mmu(struct target *target, int *enabled)
960 {
961 if (target->state != TARGET_HALTED) {
962 LOG_ERROR("%s: target not halted", __func__);
963 return ERROR_TARGET_INVALID;
964 }
965
966 struct nds32 *nds32 = target_to_nds32(target);
967 struct nds32_memory *memory = &(nds32->memory);
968 struct nds32_mmu_config *mmu_config = &(nds32->mmu_config);
969
970 if ((mmu_config->memory_protection == 2) && (memory->address_translation == true))
971 *enabled = 1;
972 else
973 *enabled = 0;
974
975 return ERROR_OK;
976 }
977
978 int nds32_arch_state(struct target *target)
979 {
980 struct nds32 *nds32 = target_to_nds32(target);
981
982 if (nds32->common_magic != NDS32_COMMON_MAGIC) {
983 LOG_ERROR("BUG: called for a non-Andes target");
984 return ERROR_FAIL;
985 }
986
987 uint32_t value_pc, value_psw;
988
989 nds32_get_mapped_reg(nds32, PC, &value_pc);
990 nds32_get_mapped_reg(nds32, IR0, &value_psw);
991
992 LOG_USER("target halted due to %s\n"
993 "psw: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
994 debug_reason_name(target),
995 value_psw,
996 value_pc,
997 nds32->virtual_hosting ? ", virtual hosting" : "");
998
999 /* save pc value to pseudo register pc */
1000 struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
1001 buf_set_u32(reg->value, 0, 32, value_pc);
1002
1003 return ERROR_OK;
1004 }
1005
1006 static void nds32_init_must_have_registers(struct nds32 *nds32)
1007 {
1008 struct reg_cache *reg_cache = nds32->core_cache;
1009
1010 /** MUST have general registers */
1011 ((struct nds32_reg *)reg_cache->reg_list[R0].arch_info)->enable = true;
1012 ((struct nds32_reg *)reg_cache->reg_list[R1].arch_info)->enable = true;
1013 ((struct nds32_reg *)reg_cache->reg_list[R2].arch_info)->enable = true;
1014 ((struct nds32_reg *)reg_cache->reg_list[R3].arch_info)->enable = true;
1015 ((struct nds32_reg *)reg_cache->reg_list[R4].arch_info)->enable = true;
1016 ((struct nds32_reg *)reg_cache->reg_list[R5].arch_info)->enable = true;
1017 ((struct nds32_reg *)reg_cache->reg_list[R6].arch_info)->enable = true;
1018 ((struct nds32_reg *)reg_cache->reg_list[R7].arch_info)->enable = true;
1019 ((struct nds32_reg *)reg_cache->reg_list[R8].arch_info)->enable = true;
1020 ((struct nds32_reg *)reg_cache->reg_list[R9].arch_info)->enable = true;
1021 ((struct nds32_reg *)reg_cache->reg_list[R10].arch_info)->enable = true;
1022 ((struct nds32_reg *)reg_cache->reg_list[R15].arch_info)->enable = true;
1023 ((struct nds32_reg *)reg_cache->reg_list[R28].arch_info)->enable = true;
1024 ((struct nds32_reg *)reg_cache->reg_list[R29].arch_info)->enable = true;
1025 ((struct nds32_reg *)reg_cache->reg_list[R30].arch_info)->enable = true;
1026 ((struct nds32_reg *)reg_cache->reg_list[R31].arch_info)->enable = true;
1027 ((struct nds32_reg *)reg_cache->reg_list[PC].arch_info)->enable = true;
1028
1029 /** MUST have configuration system registers */
1030 ((struct nds32_reg *)reg_cache->reg_list[CR0].arch_info)->enable = true;
1031 ((struct nds32_reg *)reg_cache->reg_list[CR1].arch_info)->enable = true;
1032 ((struct nds32_reg *)reg_cache->reg_list[CR2].arch_info)->enable = true;
1033 ((struct nds32_reg *)reg_cache->reg_list[CR3].arch_info)->enable = true;
1034 ((struct nds32_reg *)reg_cache->reg_list[CR4].arch_info)->enable = true;
1035
1036 /** MUST have interrupt system registers */
1037 ((struct nds32_reg *)reg_cache->reg_list[IR0].arch_info)->enable = true;
1038 ((struct nds32_reg *)reg_cache->reg_list[IR1].arch_info)->enable = true;
1039 ((struct nds32_reg *)reg_cache->reg_list[IR3].arch_info)->enable = true;
1040 ((struct nds32_reg *)reg_cache->reg_list[IR4].arch_info)->enable = true;
1041 ((struct nds32_reg *)reg_cache->reg_list[IR6].arch_info)->enable = true;
1042 ((struct nds32_reg *)reg_cache->reg_list[IR9].arch_info)->enable = true;
1043 ((struct nds32_reg *)reg_cache->reg_list[IR11].arch_info)->enable = true;
1044 ((struct nds32_reg *)reg_cache->reg_list[IR14].arch_info)->enable = true;
1045 ((struct nds32_reg *)reg_cache->reg_list[IR15].arch_info)->enable = true;
1046
1047 /** MUST have MMU system registers */
1048 ((struct nds32_reg *)reg_cache->reg_list[MR0].arch_info)->enable = true;
1049
1050 /** MUST have EDM system registers */
1051 ((struct nds32_reg *)reg_cache->reg_list[DR40].arch_info)->enable = true;
1052 ((struct nds32_reg *)reg_cache->reg_list[DR42].arch_info)->enable = true;
1053 }
1054
1055 static int nds32_init_memory_config(struct nds32 *nds32)
1056 {
1057 uint32_t value_cr1; /* ICM_CFG */
1058 uint32_t value_cr2; /* DCM_CFG */
1059 struct nds32_memory *memory = &(nds32->memory);
1060
1061 /* read $cr1 to init instruction memory information */
1062 nds32_get_mapped_reg(nds32, CR1, &value_cr1);
1063 memory->icache.set = value_cr1 & 0x7;
1064 memory->icache.way = (value_cr1 >> 3) & 0x7;
1065 memory->icache.line_size = (value_cr1 >> 6) & 0x7;
1066 memory->icache.lock_support = (value_cr1 >> 9) & 0x1;
1067
1068 memory->ilm_base = (value_cr1 >> 10) & 0x7;
1069 memory->ilm_align_ver = (value_cr1 >> 13) & 0x3;
1070
1071 /* read $cr2 to init data memory information */
1072 nds32_get_mapped_reg(nds32, CR2, &value_cr2);
1073 memory->dcache.set = value_cr2 & 0x7;
1074 memory->dcache.way = (value_cr2 >> 3) & 0x7;
1075 memory->dcache.line_size = (value_cr2 >> 6) & 0x7;
1076 memory->dcache.lock_support = (value_cr2 >> 9) & 0x1;
1077
1078 memory->dlm_base = (value_cr2 >> 10) & 0x7;
1079 memory->dlm_align_ver = (value_cr2 >> 13) & 0x3;
1080
1081 return ERROR_OK;
1082 }
1083
1084 static void nds32_init_config(struct nds32 *nds32)
1085 {
1086 uint32_t value_cr0;
1087 uint32_t value_cr3;
1088 uint32_t value_cr4;
1089 struct nds32_cpu_version *cpu_version = &(nds32->cpu_version);
1090 struct nds32_mmu_config *mmu_config = &(nds32->mmu_config);
1091 struct nds32_misc_config *misc_config = &(nds32->misc_config);
1092
1093 nds32_get_mapped_reg(nds32, CR0, &value_cr0);
1094 nds32_get_mapped_reg(nds32, CR3, &value_cr3);
1095 nds32_get_mapped_reg(nds32, CR4, &value_cr4);
1096
1097 /* config cpu version */
1098 cpu_version->performance_extension = value_cr0 & 0x1;
1099 cpu_version->_16bit_extension = (value_cr0 >> 1) & 0x1;
1100 cpu_version->performance_extension_2 = (value_cr0 >> 2) & 0x1;
1101 cpu_version->cop_fpu_extension = (value_cr0 >> 3) & 0x1;
1102 cpu_version->string_extension = (value_cr0 >> 4) & 0x1;
1103 cpu_version->revision = (value_cr0 >> 16) & 0xFF;
1104 cpu_version->cpu_id_family = (value_cr0 >> 24) & 0xF;
1105 cpu_version->cpu_id_version = (value_cr0 >> 28) & 0xF;
1106
1107 /* config MMU */
1108 mmu_config->memory_protection = value_cr3 & 0x3;
1109 mmu_config->memory_protection_version = (value_cr3 >> 2) & 0x1F;
1110 mmu_config->fully_associative_tlb = (value_cr3 >> 7) & 0x1;
1111 if (mmu_config->fully_associative_tlb) {
1112 mmu_config->tlb_size = (value_cr3 >> 8) & 0x7F;
1113 } else {
1114 mmu_config->tlb_ways = (value_cr3 >> 8) & 0x7;
1115 mmu_config->tlb_sets = (value_cr3 >> 11) & 0x7;
1116 }
1117 mmu_config->_8k_page_support = (value_cr3 >> 15) & 0x1;
1118 mmu_config->extra_page_size_support = (value_cr3 >> 16) & 0xFF;
1119 mmu_config->tlb_lock = (value_cr3 >> 24) & 0x1;
1120 mmu_config->hardware_page_table_walker = (value_cr3 >> 25) & 0x1;
1121 mmu_config->default_endian = (value_cr3 >> 26) & 0x1;
1122 mmu_config->partition_num = (value_cr3 >> 27) & 0x1;
1123 mmu_config->invisible_tlb = (value_cr3 >> 28) & 0x1;
1124 mmu_config->vlpt = (value_cr3 >> 29) & 0x1;
1125 mmu_config->ntme = (value_cr3 >> 30) & 0x1;
1126 mmu_config->drde = (value_cr3 >> 31) & 0x1;
1127
1128 /* config misc */
1129 misc_config->edm = value_cr4 & 0x1;
1130 misc_config->local_memory_dma = (value_cr4 >> 1) & 0x1;
1131 misc_config->performance_monitor = (value_cr4 >> 2) & 0x1;
1132 misc_config->high_speed_memory_port = (value_cr4 >> 3) & 0x1;
1133 misc_config->debug_tracer = (value_cr4 >> 4) & 0x1;
1134 misc_config->div_instruction = (value_cr4 >> 5) & 0x1;
1135 misc_config->mac_instruction = (value_cr4 >> 6) & 0x1;
1136 misc_config->audio_isa = (value_cr4 >> 7) & 0x3;
1137 misc_config->L2_cache = (value_cr4 >> 9) & 0x1;
1138 misc_config->reduce_register = (value_cr4 >> 10) & 0x1;
1139 misc_config->addr_24 = (value_cr4 >> 11) & 0x1;
1140 misc_config->interruption_level = (value_cr4 >> 12) & 0x1;
1141 misc_config->baseline_instruction = (value_cr4 >> 13) & 0x7;
1142 misc_config->no_dx_register = (value_cr4 >> 16) & 0x1;
1143 misc_config->implement_dependant_register = (value_cr4 >> 17) & 0x1;
1144 misc_config->implement_dependant_sr_encoding = (value_cr4 >> 18) & 0x1;
1145 misc_config->ifc = (value_cr4 >> 19) & 0x1;
1146 misc_config->mcu = (value_cr4 >> 20) & 0x1;
1147 misc_config->shadow = (value_cr4 >> 21) & 0x7;
1148 misc_config->ex9 = (value_cr4 >> 24) & 0x1;
1149
1150 nds32_init_memory_config(nds32);
1151 }
1152
1153 static int nds32_init_option_registers(struct nds32 *nds32)
1154 {
1155 struct reg_cache *reg_cache = nds32->core_cache;
1156 struct nds32_cpu_version *cpu_version = &(nds32->cpu_version);
1157 struct nds32_mmu_config *mmu_config = &(nds32->mmu_config);
1158 struct nds32_misc_config *misc_config = &(nds32->misc_config);
1159 struct nds32_memory *memory_config = &(nds32->memory);
1160
1161 bool no_cr5;
1162 bool mr10_exist;
1163 bool no_racr0;
1164
1165 if (((cpu_version->cpu_id_family == 0xC) || (cpu_version->cpu_id_family == 0xD)) &&
1166 ((cpu_version->revision & 0xFC) == 0)) {
1167 no_cr5 = true;
1168 mr10_exist = true;
1169 no_racr0 = true;
1170 } else {
1171 no_cr5 = false;
1172 mr10_exist = false;
1173 no_racr0 = false;
1174 }
1175
1176 if (misc_config->reduce_register == false) {
1177 ((struct nds32_reg *)reg_cache->reg_list[R11].arch_info)->enable = true;
1178 ((struct nds32_reg *)reg_cache->reg_list[R12].arch_info)->enable = true;
1179 ((struct nds32_reg *)reg_cache->reg_list[R13].arch_info)->enable = true;
1180 ((struct nds32_reg *)reg_cache->reg_list[R14].arch_info)->enable = true;
1181 ((struct nds32_reg *)reg_cache->reg_list[R16].arch_info)->enable = true;
1182 ((struct nds32_reg *)reg_cache->reg_list[R17].arch_info)->enable = true;
1183 ((struct nds32_reg *)reg_cache->reg_list[R18].arch_info)->enable = true;
1184 ((struct nds32_reg *)reg_cache->reg_list[R19].arch_info)->enable = true;
1185 ((struct nds32_reg *)reg_cache->reg_list[R20].arch_info)->enable = true;
1186 ((struct nds32_reg *)reg_cache->reg_list[R21].arch_info)->enable = true;
1187 ((struct nds32_reg *)reg_cache->reg_list[R22].arch_info)->enable = true;
1188 ((struct nds32_reg *)reg_cache->reg_list[R23].arch_info)->enable = true;
1189 ((struct nds32_reg *)reg_cache->reg_list[R24].arch_info)->enable = true;
1190 ((struct nds32_reg *)reg_cache->reg_list[R25].arch_info)->enable = true;
1191 ((struct nds32_reg *)reg_cache->reg_list[R26].arch_info)->enable = true;
1192 ((struct nds32_reg *)reg_cache->reg_list[R27].arch_info)->enable = true;
1193 }
1194
1195 if (misc_config->no_dx_register == false) {
1196 ((struct nds32_reg *)reg_cache->reg_list[D0LO].arch_info)->enable = true;
1197 ((struct nds32_reg *)reg_cache->reg_list[D0HI].arch_info)->enable = true;
1198 ((struct nds32_reg *)reg_cache->reg_list[D1LO].arch_info)->enable = true;
1199 ((struct nds32_reg *)reg_cache->reg_list[D1HI].arch_info)->enable = true;
1200 }
1201
1202 if (misc_config->ex9)
1203 ((struct nds32_reg *)reg_cache->reg_list[ITB].arch_info)->enable = true;
1204
1205 if (no_cr5 == false)
1206 ((struct nds32_reg *)reg_cache->reg_list[CR5].arch_info)->enable = true;
1207
1208 if (cpu_version->cop_fpu_extension) {
1209 ((struct nds32_reg *)reg_cache->reg_list[CR6].arch_info)->enable = true;
1210 ((struct nds32_reg *)reg_cache->reg_list[FPCSR].arch_info)->enable = true;
1211 ((struct nds32_reg *)reg_cache->reg_list[FPCFG].arch_info)->enable = true;
1212 }
1213
1214 if (mmu_config->memory_protection == 1) {
1215 /* Secure MPU has no IPC, IPSW, P_ITYPE */
1216 ((struct nds32_reg *)reg_cache->reg_list[IR1].arch_info)->enable = false;
1217 ((struct nds32_reg *)reg_cache->reg_list[IR9].arch_info)->enable = false;
1218 }
1219
1220 if (nds32->privilege_level != 0)
1221 ((struct nds32_reg *)reg_cache->reg_list[IR3].arch_info)->enable = false;
1222
1223 if (misc_config->mcu == true)
1224 ((struct nds32_reg *)reg_cache->reg_list[IR4].arch_info)->enable = false;
1225
1226 if (misc_config->interruption_level == false) {
1227 ((struct nds32_reg *)reg_cache->reg_list[IR2].arch_info)->enable = true;
1228 ((struct nds32_reg *)reg_cache->reg_list[IR5].arch_info)->enable = true;
1229 ((struct nds32_reg *)reg_cache->reg_list[IR10].arch_info)->enable = true;
1230 ((struct nds32_reg *)reg_cache->reg_list[IR12].arch_info)->enable = true;
1231 ((struct nds32_reg *)reg_cache->reg_list[IR13].arch_info)->enable = true;
1232
1233 /* Secure MPU has no IPC, IPSW, P_ITYPE */
1234 if (mmu_config->memory_protection != 1)
1235 ((struct nds32_reg *)reg_cache->reg_list[IR7].arch_info)->enable = true;
1236 }
1237
1238 if ((cpu_version->cpu_id_family == 0x9) ||
1239 (cpu_version->cpu_id_family == 0xA) ||
1240 (cpu_version->cpu_id_family == 0xC) ||
1241 (cpu_version->cpu_id_family == 0xD))
1242 ((struct nds32_reg *)reg_cache->reg_list[IR8].arch_info)->enable = true;
1243
1244 if (misc_config->shadow == 1) {
1245 ((struct nds32_reg *)reg_cache->reg_list[IR16].arch_info)->enable = true;
1246 ((struct nds32_reg *)reg_cache->reg_list[IR17].arch_info)->enable = true;
1247 }
1248
1249 if (misc_config->ifc)
1250 ((struct nds32_reg *)reg_cache->reg_list[IFC_LP].arch_info)->enable = true;
1251
1252 if (nds32->privilege_level != 0)
1253 ((struct nds32_reg *)reg_cache->reg_list[MR0].arch_info)->enable = false;
1254
1255 if (mmu_config->memory_protection == 1) {
1256 if (mmu_config->memory_protection_version == 24)
1257 ((struct nds32_reg *)reg_cache->reg_list[MR4].arch_info)->enable = true;
1258
1259 if (nds32->privilege_level == 0) {
1260 if ((mmu_config->memory_protection_version == 16) ||
1261 (mmu_config->memory_protection_version == 24)) {
1262 ((struct nds32_reg *)reg_cache->reg_list[MR11].arch_info)->enable = true;
1263 ((struct nds32_reg *)reg_cache->reg_list[SECUR0].arch_info)->enable = true;
1264 ((struct nds32_reg *)reg_cache->reg_list[IR20].arch_info)->enable = true;
1265 ((struct nds32_reg *)reg_cache->reg_list[IR22].arch_info)->enable = true;
1266 ((struct nds32_reg *)reg_cache->reg_list[IR24].arch_info)->enable = true;
1267 ((struct nds32_reg *)reg_cache->reg_list[IR30].arch_info)->enable = true;
1268
1269 if (misc_config->shadow == 1) {
1270 ((struct nds32_reg *)reg_cache->reg_list[IR21].arch_info)->enable = true;
1271 ((struct nds32_reg *)reg_cache->reg_list[IR23].arch_info)->enable = true;
1272 ((struct nds32_reg *)reg_cache->reg_list[IR25].arch_info)->enable = true;
1273 }
1274 }
1275 }
1276 } else if (mmu_config->memory_protection == 2) {
1277 ((struct nds32_reg *)reg_cache->reg_list[MR1].arch_info)->enable = true;
1278 ((struct nds32_reg *)reg_cache->reg_list[MR4].arch_info)->enable = true;
1279
1280 if ((cpu_version->cpu_id_family != 0xA) && (cpu_version->cpu_id_family != 0xC) &&
1281 (cpu_version->cpu_id_family != 0xD))
1282 ((struct nds32_reg *)reg_cache->reg_list[MR5].arch_info)->enable = true;
1283 }
1284
1285 if (mmu_config->memory_protection > 0) {
1286 ((struct nds32_reg *)reg_cache->reg_list[MR2].arch_info)->enable = true;
1287 ((struct nds32_reg *)reg_cache->reg_list[MR3].arch_info)->enable = true;
1288 }
1289
1290 if (memory_config->ilm_base != 0)
1291 if (nds32->privilege_level == 0)
1292 ((struct nds32_reg *)reg_cache->reg_list[MR6].arch_info)->enable = true;
1293
1294 if (memory_config->dlm_base != 0)
1295 if (nds32->privilege_level == 0)
1296 ((struct nds32_reg *)reg_cache->reg_list[MR7].arch_info)->enable = true;
1297
1298 if ((memory_config->icache.line_size != 0) && (memory_config->dcache.line_size != 0))
1299 ((struct nds32_reg *)reg_cache->reg_list[MR8].arch_info)->enable = true;
1300
1301 if (misc_config->high_speed_memory_port)
1302 ((struct nds32_reg *)reg_cache->reg_list[MR9].arch_info)->enable = true;
1303
1304 if (mr10_exist)
1305 ((struct nds32_reg *)reg_cache->reg_list[MR10].arch_info)->enable = true;
1306
1307 if (misc_config->edm) {
1308 int dr_reg_n = nds32->edm.breakpoint_num * 5;
1309
1310 for (int i = 0 ; i < dr_reg_n ; i++)
1311 ((struct nds32_reg *)reg_cache->reg_list[DR0 + i].arch_info)->enable = true;
1312
1313 ((struct nds32_reg *)reg_cache->reg_list[DR41].arch_info)->enable = true;
1314 ((struct nds32_reg *)reg_cache->reg_list[DR43].arch_info)->enable = true;
1315 ((struct nds32_reg *)reg_cache->reg_list[DR44].arch_info)->enable = true;
1316 ((struct nds32_reg *)reg_cache->reg_list[DR45].arch_info)->enable = true;
1317 }
1318
1319 if (misc_config->debug_tracer) {
1320 ((struct nds32_reg *)reg_cache->reg_list[DR46].arch_info)->enable = true;
1321 ((struct nds32_reg *)reg_cache->reg_list[DR47].arch_info)->enable = true;
1322 }
1323
1324 if (misc_config->performance_monitor) {
1325 ((struct nds32_reg *)reg_cache->reg_list[PFR0].arch_info)->enable = true;
1326 ((struct nds32_reg *)reg_cache->reg_list[PFR1].arch_info)->enable = true;
1327 ((struct nds32_reg *)reg_cache->reg_list[PFR2].arch_info)->enable = true;
1328 ((struct nds32_reg *)reg_cache->reg_list[PFR3].arch_info)->enable = true;
1329 }
1330
1331 if (misc_config->local_memory_dma) {
1332 ((struct nds32_reg *)reg_cache->reg_list[DMAR0].arch_info)->enable = true;
1333 ((struct nds32_reg *)reg_cache->reg_list[DMAR1].arch_info)->enable = true;
1334 ((struct nds32_reg *)reg_cache->reg_list[DMAR2].arch_info)->enable = true;
1335 ((struct nds32_reg *)reg_cache->reg_list[DMAR3].arch_info)->enable = true;
1336 ((struct nds32_reg *)reg_cache->reg_list[DMAR4].arch_info)->enable = true;
1337 ((struct nds32_reg *)reg_cache->reg_list[DMAR5].arch_info)->enable = true;
1338 ((struct nds32_reg *)reg_cache->reg_list[DMAR6].arch_info)->enable = true;
1339 ((struct nds32_reg *)reg_cache->reg_list[DMAR7].arch_info)->enable = true;
1340 ((struct nds32_reg *)reg_cache->reg_list[DMAR8].arch_info)->enable = true;
1341 ((struct nds32_reg *)reg_cache->reg_list[DMAR9].arch_info)->enable = true;
1342 ((struct nds32_reg *)reg_cache->reg_list[DMAR10].arch_info)->enable = true;
1343 }
1344
1345 if ((misc_config->local_memory_dma || misc_config->performance_monitor) &&
1346 (no_racr0 == false))
1347 ((struct nds32_reg *)reg_cache->reg_list[RACR].arch_info)->enable = true;
1348
1349 if (cpu_version->cop_fpu_extension || (misc_config->audio_isa != 0))
1350 ((struct nds32_reg *)reg_cache->reg_list[FUCPR].arch_info)->enable = true;
1351
1352 if (misc_config->audio_isa != 0) {
1353 if (misc_config->audio_isa > 1) {
1354 ((struct nds32_reg *)reg_cache->reg_list[D0L24].arch_info)->enable = true;
1355 ((struct nds32_reg *)reg_cache->reg_list[D1L24].arch_info)->enable = true;
1356 }
1357
1358 ((struct nds32_reg *)reg_cache->reg_list[I0].arch_info)->enable = true;
1359 ((struct nds32_reg *)reg_cache->reg_list[I1].arch_info)->enable = true;
1360 ((struct nds32_reg *)reg_cache->reg_list[I2].arch_info)->enable = true;
1361 ((struct nds32_reg *)reg_cache->reg_list[I3].arch_info)->enable = true;
1362 ((struct nds32_reg *)reg_cache->reg_list[I4].arch_info)->enable = true;
1363 ((struct nds32_reg *)reg_cache->reg_list[I5].arch_info)->enable = true;
1364 ((struct nds32_reg *)reg_cache->reg_list[I6].arch_info)->enable = true;
1365 ((struct nds32_reg *)reg_cache->reg_list[I7].arch_info)->enable = true;
1366 ((struct nds32_reg *)reg_cache->reg_list[M1].arch_info)->enable = true;
1367 ((struct nds32_reg *)reg_cache->reg_list[M2].arch_info)->enable = true;
1368 ((struct nds32_reg *)reg_cache->reg_list[M3].arch_info)->enable = true;
1369 ((struct nds32_reg *)reg_cache->reg_list[M5].arch_info)->enable = true;
1370 ((struct nds32_reg *)reg_cache->reg_list[M6].arch_info)->enable = true;
1371 ((struct nds32_reg *)reg_cache->reg_list[M7].arch_info)->enable = true;
1372 ((struct nds32_reg *)reg_cache->reg_list[MOD].arch_info)->enable = true;
1373 ((struct nds32_reg *)reg_cache->reg_list[LBE].arch_info)->enable = true;
1374 ((struct nds32_reg *)reg_cache->reg_list[LE].arch_info)->enable = true;
1375 ((struct nds32_reg *)reg_cache->reg_list[LC].arch_info)->enable = true;
1376 ((struct nds32_reg *)reg_cache->reg_list[ADM_VBASE].arch_info)->enable = true;
1377 ((struct nds32_reg *)reg_cache->reg_list[SHFT_CTL0].arch_info)->enable = true;
1378 ((struct nds32_reg *)reg_cache->reg_list[SHFT_CTL1].arch_info)->enable = true;
1379
1380 uint32_t value_mod;
1381 uint32_t fucpr_backup;
1382 /* enable fpu and get configuration */
1383 nds32_get_mapped_reg(nds32, FUCPR, &fucpr_backup);
1384 if ((fucpr_backup & 0x80000000) == 0)
1385 nds32_set_mapped_reg(nds32, FUCPR, fucpr_backup | 0x80000000);
1386 nds32_get_mapped_reg(nds32, MOD, &value_mod);
1387 /* restore origin fucpr value */
1388 if ((fucpr_backup & 0x80000000) == 0)
1389 nds32_set_mapped_reg(nds32, FUCPR, fucpr_backup);
1390
1391 if ((value_mod >> 6) & 0x1) {
1392 ((struct nds32_reg *)reg_cache->reg_list[CB_CTL].arch_info)->enable = true;
1393 ((struct nds32_reg *)reg_cache->reg_list[CBB0].arch_info)->enable = true;
1394 ((struct nds32_reg *)reg_cache->reg_list[CBB1].arch_info)->enable = true;
1395 ((struct nds32_reg *)reg_cache->reg_list[CBB2].arch_info)->enable = true;
1396 ((struct nds32_reg *)reg_cache->reg_list[CBB3].arch_info)->enable = true;
1397 ((struct nds32_reg *)reg_cache->reg_list[CBE0].arch_info)->enable = true;
1398 ((struct nds32_reg *)reg_cache->reg_list[CBE1].arch_info)->enable = true;
1399 ((struct nds32_reg *)reg_cache->reg_list[CBE2].arch_info)->enable = true;
1400 ((struct nds32_reg *)reg_cache->reg_list[CBE3].arch_info)->enable = true;
1401 }
1402 }
1403
1404 if ((cpu_version->cpu_id_family == 0x9) ||
1405 (cpu_version->cpu_id_family == 0xA) ||
1406 (cpu_version->cpu_id_family == 0xC)) {
1407
1408 ((struct nds32_reg *)reg_cache->reg_list[IDR0].arch_info)->enable = true;
1409 ((struct nds32_reg *)reg_cache->reg_list[IDR1].arch_info)->enable = true;
1410
1411 if ((cpu_version->cpu_id_family == 0xC) && (cpu_version->revision == 0x0C))
1412 ((struct nds32_reg *)reg_cache->reg_list[IDR0].arch_info)->enable = false;
1413 }
1414
1415 uint32_t ir3_value;
1416 uint32_t ivb_prog_pri_lvl;
1417 uint32_t ivb_ivic_ver;
1418
1419 nds32_get_mapped_reg(nds32, IR3, &ir3_value);
1420 ivb_prog_pri_lvl = ir3_value & 0x1;
1421 ivb_ivic_ver = (ir3_value >> 11) & 0x3;
1422
1423 if ((ivb_prog_pri_lvl == 1) || (ivb_ivic_ver >= 1)) {
1424 ((struct nds32_reg *)reg_cache->reg_list[IR18].arch_info)->enable = true;
1425 ((struct nds32_reg *)reg_cache->reg_list[IR19].arch_info)->enable = true;
1426 }
1427
1428 if (ivb_ivic_ver >= 1) {
1429 ((struct nds32_reg *)reg_cache->reg_list[IR26].arch_info)->enable = true;
1430 ((struct nds32_reg *)reg_cache->reg_list[IR27].arch_info)->enable = true;
1431 ((struct nds32_reg *)reg_cache->reg_list[IR28].arch_info)->enable = true;
1432 ((struct nds32_reg *)reg_cache->reg_list[IR29].arch_info)->enable = true;
1433 }
1434
1435 return ERROR_OK;
1436 }
1437
1438 int nds32_init_register_table(struct nds32 *nds32)
1439 {
1440 nds32_init_must_have_registers(nds32);
1441
1442 return ERROR_OK;
1443 }
1444
1445 int nds32_add_software_breakpoint(struct target *target,
1446 struct breakpoint *breakpoint)
1447 {
1448 uint32_t data;
1449 uint32_t check_data;
1450 uint32_t break_insn;
1451
1452 /* check the breakpoint size */
1453 target->type->read_buffer(target, breakpoint->address, 4, (uint8_t *)&data);
1454
1455 /* backup origin instruction
1456 * instruction is big-endian */
1457 if (*(char *)&data & 0x80) { /* 16-bits instruction */
1458 breakpoint->length = 2;
1459 break_insn = NDS32_BREAK_16;
1460 } else { /* 32-bits instruction */
1461 breakpoint->length = 4;
1462 break_insn = NDS32_BREAK_32;
1463 }
1464
1465 if (breakpoint->orig_instr != NULL)
1466 free(breakpoint->orig_instr);
1467
1468 breakpoint->orig_instr = malloc(breakpoint->length);
1469 memcpy(breakpoint->orig_instr, &data, breakpoint->length);
1470
1471 /* self-modified code */
1472 target->type->write_buffer(target, breakpoint->address, breakpoint->length, (const uint8_t *)&break_insn);
1473 /* write_back & invalidate dcache & invalidate icache */
1474 nds32_cache_sync(target, breakpoint->address, breakpoint->length);
1475
1476 /* read back to check */
1477 target->type->read_buffer(target, breakpoint->address, breakpoint->length, (uint8_t *)&check_data);
1478 if (memcmp(&check_data, &break_insn, breakpoint->length) == 0)
1479 return ERROR_OK;
1480
1481 return ERROR_FAIL;
1482 }
1483
1484 int nds32_remove_software_breakpoint(struct target *target,
1485 struct breakpoint *breakpoint)
1486 {
1487 uint32_t check_data;
1488 uint32_t break_insn;
1489
1490 if (breakpoint->length == 2)
1491 break_insn = NDS32_BREAK_16;
1492 else if (breakpoint->length == 4)
1493 break_insn = NDS32_BREAK_32;
1494 else
1495 return ERROR_FAIL;
1496
1497 target->type->read_buffer(target, breakpoint->address, breakpoint->length,
1498 (uint8_t *)&check_data);
1499
1500 /* break instruction is modified */
1501 if (memcmp(&check_data, &break_insn, breakpoint->length) != 0)
1502 return ERROR_FAIL;
1503
1504 /* self-modified code */
1505 target->type->write_buffer(target, breakpoint->address, breakpoint->length,
1506 breakpoint->orig_instr);
1507
1508 /* write_back & invalidate dcache & invalidate icache */
1509 nds32_cache_sync(target, breakpoint->address, breakpoint->length);
1510
1511 return ERROR_OK;
1512 }
1513
1514 /**
1515 * Restore the processor context on an Andes target. The full processor
1516 * context is analyzed to see if any of the registers are dirty on this end, but
1517 * have a valid new value. If this is the case, the processor is changed to the
1518 * appropriate mode and the new register values are written out to the
1519 * processor. If there happens to be a dirty register with an invalid value, an
1520 * error will be logged.
1521 *
1522 * @param target Pointer to the Andes target to have its context restored
1523 * @return Error status if the target is not halted.
1524 */
1525 int nds32_restore_context(struct target *target)
1526 {
1527 struct nds32 *nds32 = target_to_nds32(target);
1528 struct aice_port_s *aice = target_to_aice(target);
1529 struct reg_cache *reg_cache = nds32->core_cache;
1530 struct reg *reg;
1531 struct nds32_reg *reg_arch_info;
1532 unsigned int i;
1533
1534 LOG_DEBUG("-");
1535
1536 if (target->state != TARGET_HALTED) {
1537 LOG_WARNING("target not halted");
1538 return ERROR_TARGET_NOT_HALTED;
1539 }
1540
1541 /* check if there are dirty registers */
1542 for (i = 0; i < reg_cache->num_regs; i++) {
1543 reg = &(reg_cache->reg_list[i]);
1544 if (reg->dirty == true) {
1545 if (reg->valid == true) {
1546
1547 LOG_DEBUG("examining dirty reg: %s", reg->name);
1548 LOG_DEBUG("writing register %d with value 0x%8.8" PRIx32,
1549 i, buf_get_u32(reg->value, 0, 32));
1550
1551 reg_arch_info = reg->arch_info;
1552 if (FD0 <= reg_arch_info->num && reg_arch_info->num <= FD31) {
1553 uint64_t val = buf_get_u64(reg_arch_info->value, 0, 64);
1554 aice_write_reg_64(aice, reg_arch_info->num, val);
1555 } else {
1556 uint32_t val = buf_get_u32(reg_arch_info->value, 0, 32);
1557 aice_write_register(aice, reg_arch_info->num, val);
1558 }
1559
1560 reg->valid = true;
1561 reg->dirty = false;
1562 }
1563 }
1564 }
1565
1566 return ERROR_OK;
1567 }
1568
1569 int nds32_edm_config(struct nds32 *nds32)
1570 {
1571 struct target *target = nds32->target;
1572 struct aice_port_s *aice = target_to_aice(target);
1573 uint32_t edm_cfg;
1574 uint32_t edm_ctl;
1575
1576 aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
1577
1578 nds32->edm.version = (edm_cfg >> 16) & 0xFFFF;
1579 LOG_INFO("EDM version 0x%04x", nds32->edm.version);
1580
1581 nds32->edm.breakpoint_num = (edm_cfg & 0x7) + 1;
1582
1583 if ((nds32->edm.version & 0x1000) || (0x60 <= nds32->edm.version))
1584 nds32->edm.access_control = true;
1585 else
1586 nds32->edm.access_control = false;
1587
1588 if ((edm_cfg >> 4) & 0x1)
1589 nds32->edm.direct_access_local_memory = true;
1590 else
1591 nds32->edm.direct_access_local_memory = false;
1592
1593 if (nds32->edm.version <= 0x20)
1594 nds32->edm.direct_access_local_memory = false;
1595
1596 aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl);
1597 if (edm_ctl & (0x1 << 29))
1598 nds32->edm.support_max_stop = true;
1599 else
1600 nds32->edm.support_max_stop = false;
1601
1602 /* set passcode for secure MCU */
1603 nds32_login(nds32);
1604
1605 return ERROR_OK;
1606 }
1607
1608 int nds32_config(struct nds32 *nds32)
1609 {
1610 nds32_init_config(nds32);
1611
1612 /* init optional system registers according to config registers */
1613 nds32_init_option_registers(nds32);
1614
1615 /* get max interrupt level */
1616 if (nds32->misc_config.interruption_level)
1617 nds32->max_interrupt_level = 2;
1618 else
1619 nds32->max_interrupt_level = 3;
1620
1621 /* get ILM/DLM size from MR6/MR7 */
1622 uint32_t value_mr6, value_mr7;
1623 uint32_t size_index;
1624 nds32_get_mapped_reg(nds32, MR6, &value_mr6);
1625 size_index = (value_mr6 >> 1) & 0xF;
1626 nds32->memory.ilm_size = NDS32_LM_SIZE_TABLE[size_index];
1627
1628 nds32_get_mapped_reg(nds32, MR7, &value_mr7);
1629 size_index = (value_mr7 >> 1) & 0xF;
1630 nds32->memory.dlm_size = NDS32_LM_SIZE_TABLE[size_index];
1631
1632 return ERROR_OK;
1633 }
1634
1635 int nds32_init_arch_info(struct target *target, struct nds32 *nds32)
1636 {
1637 target->arch_info = nds32;
1638 nds32->target = target;
1639
1640 nds32->common_magic = NDS32_COMMON_MAGIC;
1641 nds32->init_arch_info_after_halted = false;
1642 nds32->auto_convert_hw_bp = true;
1643 nds32->global_stop = false;
1644 nds32->soft_reset_halt = false;
1645 nds32->edm_passcode = NULL;
1646 nds32->privilege_level = 0;
1647 nds32->boot_time = 1500;
1648 nds32->reset_halt_as_examine = false;
1649 nds32->keep_target_edm_ctl = false;
1650 nds32->word_access_mem = false;
1651 nds32->virtual_hosting = true;
1652 nds32->hit_syscall = false;
1653 nds32->active_syscall_id = NDS32_SYSCALL_UNDEFINED;
1654 nds32->virtual_hosting_errno = 0;
1655 nds32->virtual_hosting_ctrl_c = false;
1656 nds32->attached = false;
1657
1658 nds32->syscall_break.asid = 0;
1659 nds32->syscall_break.length = 4;
1660 nds32->syscall_break.set = 0;
1661 nds32->syscall_break.orig_instr = NULL;
1662 nds32->syscall_break.next = NULL;
1663 nds32->syscall_break.unique_id = 0x515CAll + target->target_number;
1664 nds32->syscall_break.linked_BRP = 0;
1665
1666 nds32_reg_init();
1667
1668 if (ERROR_FAIL == nds32_reg_cache_init(target, nds32))
1669 return ERROR_FAIL;
1670
1671 if (ERROR_OK != nds32_init_register_table(nds32))
1672 return ERROR_FAIL;
1673
1674 return ERROR_OK;
1675 }
1676
1677 int nds32_virtual_to_physical(struct target *target, target_addr_t address, target_addr_t *physical)
1678 {
1679 struct nds32 *nds32 = target_to_nds32(target);
1680
1681 if (nds32->memory.address_translation == false) {
1682 *physical = address;
1683 return ERROR_OK;
1684 }
1685
1686 if (ERROR_OK == nds32_probe_tlb(nds32, address, physical))
1687 return ERROR_OK;
1688
1689 if (ERROR_OK == nds32_walk_page_table(nds32, address, physical))
1690 return ERROR_OK;
1691
1692 return ERROR_FAIL;
1693 }
1694
1695 int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t length)
1696 {
1697 struct aice_port_s *aice = target_to_aice(target);
1698 struct nds32 *nds32 = target_to_nds32(target);
1699 struct nds32_cache *dcache = &(nds32->memory.dcache);
1700 struct nds32_cache *icache = &(nds32->memory.icache);
1701 uint32_t dcache_line_size = NDS32_LINE_SIZE_TABLE[dcache->line_size];
1702 uint32_t icache_line_size = NDS32_LINE_SIZE_TABLE[icache->line_size];
1703 uint32_t cur_address;
1704 int result;
1705 uint32_t start_line, end_line;
1706 uint32_t cur_line;
1707
1708 if ((dcache->line_size != 0) && (dcache->enable == true)) {
1709 /* address / dcache_line_size */
1710 start_line = address >> (dcache->line_size + 2);
1711 /* (address + length - 1) / dcache_line_size */
1712 end_line = (address + length - 1) >> (dcache->line_size + 2);
1713
1714 for (cur_address = address, cur_line = start_line ;
1715 cur_line <= end_line ;
1716 cur_address += dcache_line_size, cur_line++) {
1717 /* D$ write back */
1718 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_VA_WB, cur_address);
1719 if (result != ERROR_OK)
1720 return result;
1721
1722 /* D$ invalidate */
1723 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_VA_INVAL, cur_address);
1724 if (result != ERROR_OK)
1725 return result;
1726 }
1727 }
1728
1729 if ((icache->line_size != 0) && (icache->enable == true)) {
1730 /* address / icache_line_size */
1731 start_line = address >> (icache->line_size + 2);
1732 /* (address + length - 1) / icache_line_size */
1733 end_line = (address + length - 1) >> (icache->line_size + 2);
1734
1735 for (cur_address = address, cur_line = start_line ;
1736 cur_line <= end_line ;
1737 cur_address += icache_line_size, cur_line++) {
1738 /* Because PSW.IT is turned off under debug exception, address MUST
1739 * be physical address. L1I_VA_INVALIDATE uses PSW.IT to decide
1740 * address translation or not. */
1741 target_addr_t physical_addr;
1742 if (ERROR_FAIL == target->type->virt2phys(target, cur_address,
1743 &physical_addr))
1744 return ERROR_FAIL;
1745
1746 /* I$ invalidate */
1747 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_VA_INVAL, physical_addr);
1748 if (result != ERROR_OK)
1749 return result;
1750 }
1751 }
1752
1753 return ERROR_OK;
1754 }
1755
1756 uint32_t nds32_nextpc(struct nds32 *nds32, int current, uint32_t address)
1757 {
1758 if (!current)
1759 nds32_set_mapped_reg(nds32, PC, address);
1760 else
1761 nds32_get_mapped_reg(nds32, PC, &address);
1762
1763 return address;
1764 }
1765
1766 int nds32_step(struct target *target, int current,
1767 target_addr_t address, int handle_breakpoints)
1768 {
1769 LOG_DEBUG("target->state: %s",
1770 target_state_name(target));
1771
1772 if (target->state != TARGET_HALTED) {
1773 LOG_WARNING("target was not halted");
1774 return ERROR_TARGET_NOT_HALTED;
1775 }
1776
1777 struct nds32 *nds32 = target_to_nds32(target);
1778
1779 address = nds32_nextpc(nds32, current, address);
1780
1781 LOG_DEBUG("STEP PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : "");
1782
1783 /** set DSSIM */
1784 uint32_t ir14_value;
1785 nds32_get_mapped_reg(nds32, IR14, &ir14_value);
1786 if (nds32->step_isr_enable)
1787 ir14_value |= (0x1 << 31);
1788 else
1789 ir14_value &= ~(0x1 << 31);
1790 nds32_set_mapped_reg(nds32, IR14, ir14_value);
1791
1792 /* check hit_syscall before leave_debug_state() because
1793 * leave_debug_state() may clear hit_syscall flag */
1794 bool no_step = false;
1795 if (nds32->hit_syscall)
1796 /* step after hit_syscall should be ignored because
1797 * leave_debug_state will step implicitly to skip the
1798 * syscall */
1799 no_step = true;
1800
1801 /********* TODO: maybe create another function to handle this part */
1802 CHECK_RETVAL(nds32->leave_debug_state(nds32, true));
1803 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
1804
1805 if (no_step == false) {
1806 struct aice_port_s *aice = target_to_aice(target);
1807 if (ERROR_OK != aice_step(aice))
1808 return ERROR_FAIL;
1809 }
1810
1811 /* save state */
1812 CHECK_RETVAL(nds32->enter_debug_state(nds32, true));
1813 /********* TODO: maybe create another function to handle this part */
1814
1815 /* restore DSSIM */
1816 if (nds32->step_isr_enable) {
1817 nds32_get_mapped_reg(nds32, IR14, &ir14_value);
1818 ir14_value &= ~(0x1 << 31);
1819 nds32_set_mapped_reg(nds32, IR14, ir14_value);
1820 }
1821
1822 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1823
1824 return ERROR_OK;
1825 }
1826
1827 static int nds32_step_without_watchpoint(struct nds32 *nds32)
1828 {
1829 struct target *target = nds32->target;
1830
1831 if (target->state != TARGET_HALTED) {
1832 LOG_WARNING("target was not halted");
1833 return ERROR_TARGET_NOT_HALTED;
1834 }
1835
1836 /** set DSSIM */
1837 uint32_t ir14_value;
1838 nds32_get_mapped_reg(nds32, IR14, &ir14_value);
1839 if (nds32->step_isr_enable)
1840 ir14_value |= (0x1 << 31);
1841 else
1842 ir14_value &= ~(0x1 << 31);
1843 nds32_set_mapped_reg(nds32, IR14, ir14_value);
1844
1845 /********* TODO: maybe create another function to handle this part */
1846 CHECK_RETVAL(nds32->leave_debug_state(nds32, false));
1847
1848 struct aice_port_s *aice = target_to_aice(target);
1849
1850 if (ERROR_OK != aice_step(aice))
1851 return ERROR_FAIL;
1852
1853 /* save state */
1854 CHECK_RETVAL(nds32->enter_debug_state(nds32, false));
1855 /********* TODO: maybe create another function to handle this part */
1856
1857 /* restore DSSIM */
1858 if (nds32->step_isr_enable) {
1859 nds32_get_mapped_reg(nds32, IR14, &ir14_value);
1860 ir14_value &= ~(0x1 << 31);
1861 nds32_set_mapped_reg(nds32, IR14, ir14_value);
1862 }
1863
1864 return ERROR_OK;
1865 }
1866
1867 int nds32_target_state(struct nds32 *nds32, enum target_state *state)
1868 {
1869 struct aice_port_s *aice = target_to_aice(nds32->target);
1870 enum aice_target_state_s nds32_state;
1871
1872 if (aice_state(aice, &nds32_state) != ERROR_OK)
1873 return ERROR_FAIL;
1874
1875 switch (nds32_state) {
1876 case AICE_DISCONNECT:
1877 LOG_INFO("USB is disconnected");
1878 return ERROR_FAIL;
1879 case AICE_TARGET_DETACH:
1880 LOG_INFO("Target is disconnected");
1881 return ERROR_FAIL;
1882 case AICE_TARGET_UNKNOWN:
1883 *state = TARGET_UNKNOWN;
1884 break;
1885 case AICE_TARGET_RUNNING:
1886 *state = TARGET_RUNNING;
1887 break;
1888 case AICE_TARGET_HALTED:
1889 *state = TARGET_HALTED;
1890 break;
1891 case AICE_TARGET_RESET:
1892 *state = TARGET_RESET;
1893 break;
1894 case AICE_TARGET_DEBUG_RUNNING:
1895 *state = TARGET_DEBUG_RUNNING;
1896 break;
1897 default:
1898 return ERROR_FAIL;
1899 }
1900
1901 return ERROR_OK;
1902 }
1903
1904 int nds32_examine_debug_reason(struct nds32 *nds32)
1905 {
1906 uint32_t reason;
1907 struct target *target = nds32->target;
1908
1909 if (nds32->hit_syscall == true) {
1910 LOG_DEBUG("Hit syscall breakpoint");
1911 target->debug_reason = DBG_REASON_BREAKPOINT;
1912 return ERROR_OK;
1913 }
1914
1915 nds32->get_debug_reason(nds32, &reason);
1916
1917 LOG_DEBUG("nds32 examines debug reason: %s", nds32_debug_type_name[reason]);
1918
1919 /* Examine debug reason */
1920 switch (reason) {
1921 case NDS32_DEBUG_BREAK:
1922 case NDS32_DEBUG_BREAK_16:
1923 case NDS32_DEBUG_INST_BREAK:
1924 {
1925 uint32_t value_pc;
1926 uint32_t opcode;
1927 struct nds32_instruction instruction;
1928
1929 nds32_get_mapped_reg(nds32, PC, &value_pc);
1930
1931 if (ERROR_OK != nds32_read_opcode(nds32, value_pc, &opcode))
1932 return ERROR_FAIL;
1933 if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode, value_pc,
1934 &instruction))
1935 return ERROR_FAIL;
1936
1937 /* hit 'break 0x7FFF' */
1938 if ((instruction.info.opc_6 == 0x32) &&
1939 (instruction.info.sub_opc == 0xA) &&
1940 (instruction.info.imm == 0x7FFF)) {
1941 target->debug_reason = DBG_REASON_EXIT;
1942 } else
1943 target->debug_reason = DBG_REASON_BREAKPOINT;
1944 }
1945 break;
1946 case NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE:
1947 case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE:
1948 case NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP: /* GLOBAL_STOP is precise exception */
1949 {
1950 int result;
1951
1952 result = nds32->get_watched_address(nds32,
1953 &(nds32->watched_address), reason);
1954 /* do single step(without watchpoints) to skip the "watched" instruction */
1955 nds32_step_without_watchpoint(nds32);
1956
1957 /* before single_step, save exception address */
1958 if (ERROR_OK != result)
1959 return ERROR_FAIL;
1960
1961 target->debug_reason = DBG_REASON_WATCHPOINT;
1962 }
1963 break;
1964 case NDS32_DEBUG_DEBUG_INTERRUPT:
1965 target->debug_reason = DBG_REASON_DBGRQ;
1966 break;
1967 case NDS32_DEBUG_HARDWARE_SINGLE_STEP:
1968 target->debug_reason = DBG_REASON_SINGLESTEP;
1969 break;
1970 case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE:
1971 case NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE:
1972 case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE:
1973 if (ERROR_OK != nds32->get_watched_address(nds32,
1974 &(nds32->watched_address), reason))
1975 return ERROR_FAIL;
1976
1977 target->debug_reason = DBG_REASON_WATCHPOINT;
1978 break;
1979 default:
1980 target->debug_reason = DBG_REASON_UNDEFINED;
1981 break;
1982 }
1983
1984 return ERROR_OK;
1985 }
1986
1987 int nds32_login(struct nds32 *nds32)
1988 {
1989 struct target *target = nds32->target;
1990 struct aice_port_s *aice = target_to_aice(target);
1991 uint32_t passcode_length;
1992 char command_sequence[129];
1993 char command_str[33];
1994 char code_str[9];
1995 uint32_t copy_length;
1996 uint32_t code;
1997 uint32_t i;
1998
1999 LOG_DEBUG("nds32_login");
2000
2001 if (nds32->edm_passcode != NULL) {
2002 /* convert EDM passcode to command sequences */
2003 passcode_length = strlen(nds32->edm_passcode);
2004 command_sequence[0] = '\0';
2005 for (i = 0; i < passcode_length; i += 8) {
2006 if (passcode_length - i < 8)
2007 copy_length = passcode_length - i;
2008 else
2009 copy_length = 8;
2010
2011 strncpy(code_str, nds32->edm_passcode + i, copy_length);
2012 code_str[copy_length] = '\0';
2013 code = strtoul(code_str, NULL, 16);
2014
2015 sprintf(command_str, "write_misc gen_port0 0x%" PRIx32 ";", code);
2016 strcat(command_sequence, command_str);
2017 }
2018
2019 if (ERROR_OK != aice_program_edm(aice, command_sequence))
2020 return ERROR_FAIL;
2021
2022 /* get current privilege level */
2023 uint32_t value_edmsw;
2024 aice_read_debug_reg(aice, NDS_EDM_SR_EDMSW, &value_edmsw);
2025 nds32->privilege_level = (value_edmsw >> 16) & 0x3;
2026 LOG_INFO("Current privilege level: %d", nds32->privilege_level);
2027 }
2028
2029 if (nds32_edm_ops_num > 0) {
2030 const char *reg_name;
2031 for (i = 0 ; i < nds32_edm_ops_num ; i++) {
2032 code = nds32_edm_ops[i].value;
2033 if (nds32_edm_ops[i].reg_no == 6)
2034 reg_name = "gen_port0";
2035 else if (nds32_edm_ops[i].reg_no == 7)
2036 reg_name = "gen_port1";
2037 else
2038 return ERROR_FAIL;
2039
2040 sprintf(command_str, "write_misc %s 0x%" PRIx32 ";", reg_name, code);
2041 if (ERROR_OK != aice_program_edm(aice, command_str))
2042 return ERROR_FAIL;
2043 }
2044 }
2045
2046 return ERROR_OK;
2047 }
2048
2049 int nds32_halt(struct target *target)
2050 {
2051 struct nds32 *nds32 = target_to_nds32(target);
2052 struct aice_port_s *aice = target_to_aice(target);
2053 enum target_state state;
2054
2055 LOG_DEBUG("target->state: %s",
2056 target_state_name(target));
2057
2058 if (target->state == TARGET_HALTED) {
2059 LOG_DEBUG("target was already halted");
2060 return ERROR_OK;
2061 }
2062
2063 if (nds32_target_state(nds32, &state) != ERROR_OK)
2064 return ERROR_FAIL;
2065
2066 if (TARGET_HALTED != state)
2067 /* TODO: if state == TARGET_HALTED, check ETYPE is DBGI or not */
2068 if (ERROR_OK != aice_halt(aice))
2069 return ERROR_FAIL;
2070
2071 CHECK_RETVAL(nds32->enter_debug_state(nds32, true));
2072
2073 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
2074
2075 return ERROR_OK;
2076 }
2077
2078 /* poll current target status */
2079 int nds32_poll(struct target *target)
2080 {
2081 struct nds32 *nds32 = target_to_nds32(target);
2082 enum target_state state;
2083
2084 if (nds32_target_state(nds32, &state) != ERROR_OK)
2085 return ERROR_FAIL;
2086
2087 if (state == TARGET_HALTED) {
2088 if (target->state != TARGET_HALTED) {
2089 /* if false_hit, continue free_run */
2090 if (ERROR_OK != nds32->enter_debug_state(nds32, true)) {
2091 struct aice_port_s *aice = target_to_aice(target);
2092 aice_run(aice);
2093 return ERROR_OK;
2094 }
2095
2096 LOG_DEBUG("Change target state to TARGET_HALTED.");
2097
2098 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2099 }
2100 } else if (state == TARGET_RESET) {
2101 if (target->state == TARGET_HALTED) {
2102 /* similar to assert srst */
2103 register_cache_invalidate(nds32->core_cache);
2104 target->state = TARGET_RESET;
2105
2106 /* TODO: deassert srst */
2107 } else if (target->state == TARGET_RUNNING) {
2108 /* reset as running */
2109 LOG_WARNING("<-- TARGET WARNING! The debug target has been reset. -->");
2110 }
2111 } else {
2112 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) {
2113 LOG_DEBUG("Change target state to TARGET_RUNNING.");
2114 target->state = TARGET_RUNNING;
2115 target->debug_reason = DBG_REASON_NOTHALTED;
2116 }
2117 }
2118
2119 return ERROR_OK;
2120 }
2121
2122 int nds32_resume(struct target *target, int current,
2123 target_addr_t address, int handle_breakpoints, int debug_execution)
2124 {
2125 LOG_DEBUG("current %d address %08" TARGET_PRIxADDR
2126 " handle_breakpoints %d"
2127 " debug_execution %d",
2128 current, address, handle_breakpoints, debug_execution);
2129
2130 struct nds32 *nds32 = target_to_nds32(target);
2131
2132 if (target->state != TARGET_HALTED) {
2133 LOG_ERROR("Target not halted");
2134 return ERROR_TARGET_NOT_HALTED;
2135 }
2136
2137 address = nds32_nextpc(nds32, current, address);
2138
2139 LOG_DEBUG("RESUME PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : "");
2140
2141 if (!debug_execution)
2142 target_free_all_working_areas(target);
2143
2144 /* Disable HSS to avoid users misuse HSS */
2145 if (nds32_reach_max_interrupt_level(nds32) == false) {
2146 uint32_t value_ir0;
2147 nds32_get_mapped_reg(nds32, IR0, &value_ir0);
2148 value_ir0 &= ~(0x1 << 11);
2149 nds32_set_mapped_reg(nds32, IR0, value_ir0);
2150 }
2151
2152 CHECK_RETVAL(nds32->leave_debug_state(nds32, true));
2153 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
2154
2155 if (nds32->virtual_hosting_ctrl_c == false) {
2156 struct aice_port_s *aice = target_to_aice(target);
2157 aice_run(aice);
2158 } else
2159 nds32->virtual_hosting_ctrl_c = false;
2160
2161 target->debug_reason = DBG_REASON_NOTHALTED;
2162 if (!debug_execution)
2163 target->state = TARGET_RUNNING;
2164 else
2165 target->state = TARGET_DEBUG_RUNNING;
2166
2167 LOG_DEBUG("target->state: %s",
2168 target_state_name(target));
2169
2170 return ERROR_OK;
2171 }
2172
2173 static int nds32_soft_reset_halt(struct target *target)
2174 {
2175 /* TODO: test it */
2176 struct nds32 *nds32 = target_to_nds32(target);
2177 struct aice_port_s *aice = target_to_aice(target);
2178
2179 aice_assert_srst(aice, AICE_SRST);
2180
2181 /* halt core and set pc to 0x0 */
2182 int retval = target_halt(target);
2183 if (retval != ERROR_OK)
2184 return retval;
2185
2186 /* start fetching from IVB */
2187 uint32_t value_ir3;
2188 nds32_get_mapped_reg(nds32, IR3, &value_ir3);
2189 nds32_set_mapped_reg(nds32, PC, value_ir3 & 0xFFFF0000);
2190
2191 return ERROR_OK;
2192 }
2193
2194 int nds32_assert_reset(struct target *target)
2195 {
2196 struct nds32 *nds32 = target_to_nds32(target);
2197 struct aice_port_s *aice = target_to_aice(target);
2198 struct nds32_cpu_version *cpu_version = &(nds32->cpu_version);
2199
2200 /* TODO: apply hw reset signal in not examined state */
2201 if (!(target_was_examined(target))) {
2202 LOG_WARNING("Reset is not asserted because the target is not examined.");
2203 LOG_WARNING("Use a reset button or power cycle the target.");
2204 return ERROR_TARGET_NOT_EXAMINED;
2205 }
2206
2207 if (target->reset_halt) {
2208 if ((nds32->soft_reset_halt)
2209 || (nds32->edm.version < 0x51)
2210 || ((nds32->edm.version == 0x51)
2211 && (cpu_version->revision == 0x1C)
2212 && (cpu_version->cpu_id_family == 0xC)
2213 && (cpu_version->cpu_id_version == 0x0)))
2214 nds32_soft_reset_halt(target);
2215 else
2216 aice_assert_srst(aice, AICE_RESET_HOLD);
2217 } else {
2218 aice_assert_srst(aice, AICE_SRST);
2219 alive_sleep(nds32->boot_time);
2220 }
2221
2222 /* set passcode for secure MCU after core reset */
2223 nds32_login(nds32);
2224
2225 /* registers are now invalid */
2226 register_cache_invalidate(nds32->core_cache);
2227
2228 target->state = TARGET_RESET;
2229
2230 return ERROR_OK;
2231 }
2232
2233 static int nds32_gdb_attach(struct nds32 *nds32)
2234 {
2235 LOG_DEBUG("nds32_gdb_attach, target coreid: %" PRId32, nds32->target->coreid);
2236
2237 if (nds32->attached == false) {
2238
2239 if (nds32->keep_target_edm_ctl) {
2240 /* backup target EDM_CTL */
2241 struct aice_port_s *aice = target_to_aice(nds32->target);
2242 aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &nds32->backup_edm_ctl);
2243 }
2244
2245 target_halt(nds32->target);
2246
2247 nds32->attached = true;
2248 }
2249
2250 return ERROR_OK;
2251 }
2252
2253 static int nds32_gdb_detach(struct nds32 *nds32)
2254 {
2255 LOG_DEBUG("nds32_gdb_detach");
2256 bool backup_virtual_hosting_setting;
2257
2258 if (nds32->attached) {
2259
2260 backup_virtual_hosting_setting = nds32->virtual_hosting;
2261 /* turn off virtual hosting before resume as gdb-detach */
2262 nds32->virtual_hosting = false;
2263 target_resume(nds32->target, 1, 0, 0, 0);
2264 nds32->virtual_hosting = backup_virtual_hosting_setting;
2265
2266 if (nds32->keep_target_edm_ctl) {
2267 /* restore target EDM_CTL */
2268 struct aice_port_s *aice = target_to_aice(nds32->target);
2269 aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, nds32->backup_edm_ctl);
2270 }
2271
2272 nds32->attached = false;
2273 }
2274
2275 return ERROR_OK;
2276 }
2277
2278 static int nds32_callback_event_handler(struct target *target,
2279 enum target_event event, void *priv)
2280 {
2281 int retval = ERROR_OK;
2282 int target_number = *(int *)priv;
2283
2284 if (target_number != target->target_number)
2285 return ERROR_OK;
2286
2287 struct nds32 *nds32 = target_to_nds32(target);
2288
2289 switch (event) {
2290 case TARGET_EVENT_GDB_ATTACH:
2291 retval = nds32_gdb_attach(nds32);
2292 break;
2293 case TARGET_EVENT_GDB_DETACH:
2294 retval = nds32_gdb_detach(nds32);
2295 break;
2296 default:
2297 break;
2298 }
2299
2300 return retval;
2301 }
2302
2303 int nds32_init(struct nds32 *nds32)
2304 {
2305 /* Initialize anything we can set up without talking to the target */
2306 nds32->memory.access_channel = NDS_MEMORY_ACC_CPU;
2307
2308 /* register event callback */
2309 target_register_event_callback(nds32_callback_event_handler,
2310 &(nds32->target->target_number));
2311
2312 return ERROR_OK;
2313 }
2314
2315 int nds32_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info)
2316 {
2317 /* fill syscall parameters to file-I/O info */
2318 if (NULL == fileio_info) {
2319 LOG_ERROR("Target has not initial file-I/O data structure");
2320 return ERROR_FAIL;
2321 }
2322
2323 struct nds32 *nds32 = target_to_nds32(target);
2324 uint32_t value_ir6;
2325 uint32_t syscall_id;
2326
2327 if (nds32->hit_syscall == false)
2328 return ERROR_FAIL;
2329
2330 nds32_get_mapped_reg(nds32, IR6, &value_ir6);
2331 syscall_id = (value_ir6 >> 16) & 0x7FFF;
2332 nds32->active_syscall_id = syscall_id;
2333
2334 LOG_DEBUG("hit syscall ID: 0x%" PRIx32, syscall_id);
2335
2336 /* free previous identifier storage */
2337 if (NULL != fileio_info->identifier) {
2338 free(fileio_info->identifier);
2339 fileio_info->identifier = NULL;
2340 }
2341
2342 uint32_t reg_r0, reg_r1, reg_r2;
2343 nds32_get_mapped_reg(nds32, R0, &reg_r0);
2344 nds32_get_mapped_reg(nds32, R1, &reg_r1);
2345 nds32_get_mapped_reg(nds32, R2, &reg_r2);
2346
2347 switch (syscall_id) {
2348 case NDS32_SYSCALL_EXIT:
2349 fileio_info->identifier = malloc(5);
2350 sprintf(fileio_info->identifier, "exit");
2351 fileio_info->param_1 = reg_r0;
2352 break;
2353 case NDS32_SYSCALL_OPEN:
2354 {
2355 uint8_t filename[256];
2356 fileio_info->identifier = malloc(5);
2357 sprintf(fileio_info->identifier, "open");
2358 fileio_info->param_1 = reg_r0;
2359 /* reserve fileio_info->param_2 for length of path */
2360 fileio_info->param_3 = reg_r1;
2361 fileio_info->param_4 = reg_r2;
2362
2363 target->type->read_buffer(target, reg_r0, 256, filename);
2364 fileio_info->param_2 = strlen((char *)filename) + 1;
2365 }
2366 break;
2367 case NDS32_SYSCALL_CLOSE:
2368 fileio_info->identifier = malloc(6);
2369 sprintf(fileio_info->identifier, "close");
2370 fileio_info->param_1 = reg_r0;
2371 break;
2372 case NDS32_SYSCALL_READ:
2373 fileio_info->identifier = malloc(5);
2374 sprintf(fileio_info->identifier, "read");
2375 fileio_info->param_1 = reg_r0;
2376 fileio_info->param_2 = reg_r1;
2377 fileio_info->param_3 = reg_r2;
2378 break;
2379 case NDS32_SYSCALL_WRITE:
2380 fileio_info->identifier = malloc(6);
2381 sprintf(fileio_info->identifier, "write");
2382 fileio_info->param_1 = reg_r0;
2383 fileio_info->param_2 = reg_r1;
2384 fileio_info->param_3 = reg_r2;
2385 break;
2386 case NDS32_SYSCALL_LSEEK:
2387 fileio_info->identifier = malloc(6);
2388 sprintf(fileio_info->identifier, "lseek");
2389 fileio_info->param_1 = reg_r0;
2390 fileio_info->param_2 = reg_r1;
2391 fileio_info->param_3 = reg_r2;
2392 break;
2393 case NDS32_SYSCALL_UNLINK:
2394 {
2395 uint8_t filename[256];
2396 fileio_info->identifier = malloc(7);
2397 sprintf(fileio_info->identifier, "unlink");
2398 fileio_info->param_1 = reg_r0;
2399 /* reserve fileio_info->param_2 for length of path */
2400
2401 target->type->read_buffer(target, reg_r0, 256, filename);
2402 fileio_info->param_2 = strlen((char *)filename) + 1;
2403 }
2404 break;
2405 case NDS32_SYSCALL_RENAME:
2406 {
2407 uint8_t filename[256];
2408 fileio_info->identifier = malloc(7);
2409 sprintf(fileio_info->identifier, "rename");
2410 fileio_info->param_1 = reg_r0;
2411 /* reserve fileio_info->param_2 for length of old path */
2412 fileio_info->param_3 = reg_r1;
2413 /* reserve fileio_info->param_4 for length of new path */
2414
2415 target->type->read_buffer(target, reg_r0, 256, filename);
2416 fileio_info->param_2 = strlen((char *)filename) + 1;
2417
2418 target->type->read_buffer(target, reg_r1, 256, filename);
2419 fileio_info->param_4 = strlen((char *)filename) + 1;
2420 }
2421 break;
2422 case NDS32_SYSCALL_FSTAT:
2423 fileio_info->identifier = malloc(6);
2424 sprintf(fileio_info->identifier, "fstat");
2425 fileio_info->param_1 = reg_r0;
2426 fileio_info->param_2 = reg_r1;
2427 break;
2428 case NDS32_SYSCALL_STAT:
2429 {
2430 uint8_t filename[256];
2431 fileio_info->identifier = malloc(5);
2432 sprintf(fileio_info->identifier, "stat");
2433 fileio_info->param_1 = reg_r0;
2434 /* reserve fileio_info->param_2 for length of old path */
2435 fileio_info->param_3 = reg_r1;
2436
2437 target->type->read_buffer(target, reg_r0, 256, filename);
2438 fileio_info->param_2 = strlen((char *)filename) + 1;
2439 }
2440 break;
2441 case NDS32_SYSCALL_GETTIMEOFDAY:
2442 fileio_info->identifier = malloc(13);
2443 sprintf(fileio_info->identifier, "gettimeofday");
2444 fileio_info->param_1 = reg_r0;
2445 fileio_info->param_2 = reg_r1;
2446 break;
2447 case NDS32_SYSCALL_ISATTY:
2448 fileio_info->identifier = malloc(7);
2449 sprintf(fileio_info->identifier, "isatty");
2450 fileio_info->param_1 = reg_r0;
2451 break;
2452 case NDS32_SYSCALL_SYSTEM:
2453 {
2454 uint8_t command[256];
2455 fileio_info->identifier = malloc(7);
2456 sprintf(fileio_info->identifier, "system");
2457 fileio_info->param_1 = reg_r0;
2458 /* reserve fileio_info->param_2 for length of old path */
2459
2460 target->type->read_buffer(target, reg_r0, 256, command);
2461 fileio_info->param_2 = strlen((char *)command) + 1;
2462 }
2463 break;
2464 case NDS32_SYSCALL_ERRNO:
2465 fileio_info->identifier = malloc(6);
2466 sprintf(fileio_info->identifier, "errno");
2467 nds32_set_mapped_reg(nds32, R0, nds32->virtual_hosting_errno);
2468 break;
2469 default:
2470 fileio_info->identifier = malloc(8);
2471 sprintf(fileio_info->identifier, "unknown");
2472 break;
2473 }
2474
2475 return ERROR_OK;
2476 }
2477
2478 int nds32_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c)
2479 {
2480 LOG_DEBUG("syscall return code: 0x%x, errno: 0x%x , ctrl_c: %s",
2481 retcode, fileio_errno, ctrl_c ? "true" : "false");
2482
2483 struct nds32 *nds32 = target_to_nds32(target);
2484
2485 nds32_set_mapped_reg(nds32, R0, (uint32_t)retcode);
2486
2487 nds32->virtual_hosting_errno = fileio_errno;
2488 nds32->virtual_hosting_ctrl_c = ctrl_c;
2489 nds32->active_syscall_id = NDS32_SYSCALL_UNDEFINED;
2490
2491 return ERROR_OK;
2492 }
2493
2494 int nds32_profiling(struct target *target, uint32_t *samples,
2495 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
2496 {
2497 /* sample $PC every 10 milliseconds */
2498 uint32_t iteration = seconds * 100;
2499 struct aice_port_s *aice = target_to_aice(target);
2500 struct nds32 *nds32 = target_to_nds32(target);
2501
2502 if (max_num_samples < iteration)
2503 iteration = max_num_samples;
2504
2505 int pc_regnum = nds32->register_map(nds32, PC);
2506 aice_profiling(aice, 10, iteration, pc_regnum, samples, num_samples);
2507
2508 register_cache_invalidate(nds32->core_cache);
2509
2510 return ERROR_OK;
2511 }
2512
2513 int nds32_gdb_fileio_write_memory(struct nds32 *nds32, uint32_t address,
2514 uint32_t size, const uint8_t *buffer)
2515 {
2516 if ((NDS32_SYSCALL_FSTAT == nds32->active_syscall_id) ||
2517 (NDS32_SYSCALL_STAT == nds32->active_syscall_id)) {
2518 /* If doing GDB file-I/O, target should convert 'struct stat'
2519 * from gdb-format to target-format */
2520 uint8_t stat_buffer[NDS32_STRUCT_STAT_SIZE];
2521 /* st_dev 2 */
2522 stat_buffer[0] = buffer[3];
2523 stat_buffer[1] = buffer[2];
2524 /* st_ino 2 */
2525 stat_buffer[2] = buffer[7];
2526 stat_buffer[3] = buffer[6];
2527 /* st_mode 4 */
2528 stat_buffer[4] = buffer[11];
2529 stat_buffer[5] = buffer[10];
2530 stat_buffer[6] = buffer[9];
2531 stat_buffer[7] = buffer[8];
2532 /* st_nlink 2 */
2533 stat_buffer[8] = buffer[15];
2534 stat_buffer[9] = buffer[16];
2535 /* st_uid 2 */
2536 stat_buffer[10] = buffer[19];
2537 stat_buffer[11] = buffer[18];
2538 /* st_gid 2 */
2539 stat_buffer[12] = buffer[23];
2540 stat_buffer[13] = buffer[22];
2541 /* st_rdev 2 */
2542 stat_buffer[14] = buffer[27];
2543 stat_buffer[15] = buffer[26];
2544 /* st_size 4 */
2545 stat_buffer[16] = buffer[35];
2546 stat_buffer[17] = buffer[34];
2547 stat_buffer[18] = buffer[33];
2548 stat_buffer[19] = buffer[32];
2549 /* st_atime 4 */
2550 stat_buffer[20] = buffer[55];
2551 stat_buffer[21] = buffer[54];
2552 stat_buffer[22] = buffer[53];
2553 stat_buffer[23] = buffer[52];
2554 /* st_spare1 4 */
2555 stat_buffer[24] = 0;
2556 stat_buffer[25] = 0;
2557 stat_buffer[26] = 0;
2558 stat_buffer[27] = 0;
2559 /* st_mtime 4 */
2560 stat_buffer[28] = buffer[59];
2561 stat_buffer[29] = buffer[58];
2562 stat_buffer[30] = buffer[57];
2563 stat_buffer[31] = buffer[56];
2564 /* st_spare2 4 */
2565 stat_buffer[32] = 0;
2566 stat_buffer[33] = 0;
2567 stat_buffer[34] = 0;
2568 stat_buffer[35] = 0;
2569 /* st_ctime 4 */
2570 stat_buffer[36] = buffer[63];
2571 stat_buffer[37] = buffer[62];
2572 stat_buffer[38] = buffer[61];
2573 stat_buffer[39] = buffer[60];
2574 /* st_spare3 4 */
2575 stat_buffer[40] = 0;
2576 stat_buffer[41] = 0;
2577 stat_buffer[42] = 0;
2578 stat_buffer[43] = 0;
2579 /* st_blksize 4 */
2580 stat_buffer[44] = buffer[43];
2581 stat_buffer[45] = buffer[42];
2582 stat_buffer[46] = buffer[41];
2583 stat_buffer[47] = buffer[40];
2584 /* st_blocks 4 */
2585 stat_buffer[48] = buffer[51];
2586 stat_buffer[49] = buffer[50];
2587 stat_buffer[50] = buffer[49];
2588 stat_buffer[51] = buffer[48];
2589 /* st_spare4 8 */
2590 stat_buffer[52] = 0;
2591 stat_buffer[53] = 0;
2592 stat_buffer[54] = 0;
2593 stat_buffer[55] = 0;
2594 stat_buffer[56] = 0;
2595 stat_buffer[57] = 0;
2596 stat_buffer[58] = 0;
2597 stat_buffer[59] = 0;
2598
2599 return nds32_write_buffer(nds32->target, address, NDS32_STRUCT_STAT_SIZE, stat_buffer);
2600 } else if (NDS32_SYSCALL_GETTIMEOFDAY == nds32->active_syscall_id) {
2601 /* If doing GDB file-I/O, target should convert 'struct timeval'
2602 * from gdb-format to target-format */
2603 uint8_t timeval_buffer[NDS32_STRUCT_TIMEVAL_SIZE];
2604 timeval_buffer[0] = buffer[3];
2605 timeval_buffer[1] = buffer[2];
2606 timeval_buffer[2] = buffer[1];
2607 timeval_buffer[3] = buffer[0];
2608 timeval_buffer[4] = buffer[11];
2609 timeval_buffer[5] = buffer[10];
2610 timeval_buffer[6] = buffer[9];
2611 timeval_buffer[7] = buffer[8];
2612
2613 return nds32_write_buffer(nds32->target, address, NDS32_STRUCT_TIMEVAL_SIZE, timeval_buffer);
2614 }
2615
2616 return nds32_write_buffer(nds32->target, address, size, buffer);
2617 }
2618
2619 int nds32_reset_halt(struct nds32 *nds32)
2620 {
2621 LOG_INFO("reset halt as init");
2622
2623 struct aice_port_s *aice = target_to_aice(nds32->target);
2624 aice_assert_srst(aice, AICE_RESET_HOLD);
2625
2626 return ERROR_OK;
2627 }
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