1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
28 #include "breakpoints.h"
31 #include "mips32_dmaacc.h"
32 #include "target_type.h"
35 int mips_m4k_examine_debug_reason(struct target
*target
)
37 uint32_t break_status
;
40 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
41 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
43 /* get info about inst breakpoint support */
44 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &break_status
)) != ERROR_OK
)
46 if (break_status
& 0x1f)
48 /* we have halted on a breakpoint */
49 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
51 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
54 /* get info about data breakpoint support */
55 if ((retval
= target_read_u32(target
, EJTAG_DBS
, &break_status
)) != ERROR_OK
)
57 if (break_status
& 0x1f)
59 /* we have halted on a breakpoint */
60 if ((retval
= target_write_u32(target
, EJTAG_DBS
, 0)) != ERROR_OK
)
62 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
69 int mips_m4k_debug_entry(struct target
*target
)
71 struct mips32_common
*mips32
= target_to_mips32(target
);
72 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
75 /* read debug register */
76 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
78 /* make sure break unit configured */
79 mips32_configure_break_unit(target
);
81 /* attempt to find halt reason */
82 mips_m4k_examine_debug_reason(target
);
84 /* clear single step if active */
85 if (debug_reg
& EJTAG_DEBUG_DSS
)
87 /* stopped due to single step - clear step bit */
88 mips_ejtag_config_step(ejtag_info
, 0);
91 mips32_save_context(target
);
93 /* default to mips32 isa, it will be changed below if required */
94 mips32
->isa_mode
= MIPS32_ISA_MIPS32
;
96 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
) {
97 mips32
->isa_mode
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1);
100 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
101 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32),
102 target_state_name(target
));
107 int mips_m4k_poll(struct target
*target
)
110 struct mips32_common
*mips32
= target_to_mips32(target
);
111 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
112 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
114 /* read ejtag control reg */
115 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
116 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
118 /* clear this bit before handling polling
119 * as after reset registers will read zero */
120 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
122 /* we have detected a reset, clear flag
123 * otherwise ejtag will not work */
124 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
126 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
127 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
128 LOG_DEBUG("Reset Detected");
131 /* check for processor halted */
132 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
134 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
136 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
138 target
->state
= TARGET_HALTED
;
140 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
143 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
145 else if (target
->state
== TARGET_DEBUG_RUNNING
)
147 target
->state
= TARGET_HALTED
;
149 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
152 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
157 target
->state
= TARGET_RUNNING
;
160 // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
165 int mips_m4k_halt(struct target
*target
)
167 struct mips32_common
*mips32
= target_to_mips32(target
);
168 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
170 LOG_DEBUG("target->state: %s",
171 target_state_name(target
));
173 if (target
->state
== TARGET_HALTED
)
175 LOG_DEBUG("target was already halted");
179 if (target
->state
== TARGET_UNKNOWN
)
181 LOG_WARNING("target was in unknown state when halt was requested");
184 if (target
->state
== TARGET_RESET
)
186 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
188 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
189 return ERROR_TARGET_FAILURE
;
193 /* we came here in a reset_halt or reset_init sequence
194 * debug entry was already prepared in mips32_prepare_reset_halt()
196 target
->debug_reason
= DBG_REASON_DBGRQ
;
202 /* break processor */
203 mips_ejtag_enter_debug(ejtag_info
);
205 target
->debug_reason
= DBG_REASON_DBGRQ
;
210 int mips_m4k_assert_reset(struct target
*target
)
212 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
213 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
216 LOG_DEBUG("target->state: %s",
217 target_state_name(target
));
219 enum reset_types jtag_reset_config
= jtag_get_reset_config();
221 if (!(jtag_reset_config
& RESET_HAS_SRST
))
224 if (target
->reset_halt
)
226 /* use hardware to catch reset */
227 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
);
231 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
236 /* here we should issue a srst only, but we may have to assert trst as well */
237 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
239 jtag_add_reset(1, 1);
243 jtag_add_reset(0, 1);
248 if (mips_m4k
->is_pic32mx
)
252 LOG_DEBUG("Using MTAP reset to reset processor...");
254 /* use microchip specific MTAP reset */
255 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_MTAP
);
256 mips_ejtag_set_instr(ejtag_info
, MTAP_COMMAND
);
258 mchip_cmd
= MCHP_ASERT_RST
;
259 mips_ejtag_drscan_8(ejtag_info
, &mchip_cmd
);
260 mchip_cmd
= MCHP_DE_ASSERT_RST
;
261 mips_ejtag_drscan_8(ejtag_info
, &mchip_cmd
);
262 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
266 /* use ejtag reset - not supported by all cores */
267 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
268 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
269 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
270 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
274 target
->state
= TARGET_RESET
;
275 jtag_add_sleep(50000);
277 register_cache_invalidate(mips_m4k
->mips32
.core_cache
);
279 if (target
->reset_halt
)
282 if ((retval
= target_halt(target
)) != ERROR_OK
)
289 int mips_m4k_deassert_reset(struct target
*target
)
291 LOG_DEBUG("target->state: %s",
292 target_state_name(target
));
294 /* deassert reset lines */
295 jtag_add_reset(0, 0);
300 int mips_m4k_soft_reset_halt(struct target
*target
)
306 int mips_m4k_single_step_core(struct target
*target
)
308 struct mips32_common
*mips32
= target_to_mips32(target
);
309 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
311 /* configure single step mode */
312 mips_ejtag_config_step(ejtag_info
, 1);
314 /* disable interrupts while stepping */
315 mips32_enable_interrupts(target
, 0);
317 /* exit debug mode */
318 mips_ejtag_exit_debug(ejtag_info
);
320 mips_m4k_debug_entry(target
);
325 int mips_m4k_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
327 struct mips32_common
*mips32
= target_to_mips32(target
);
328 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
329 struct breakpoint
*breakpoint
= NULL
;
332 if (target
->state
!= TARGET_HALTED
)
334 LOG_WARNING("target not halted");
335 return ERROR_TARGET_NOT_HALTED
;
338 if (!debug_execution
)
340 target_free_all_working_areas(target
);
341 mips_m4k_enable_breakpoints(target
);
342 mips_m4k_enable_watchpoints(target
);
345 /* current = 1: continue on current pc, otherwise continue at <address> */
348 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
349 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
350 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
353 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
) {
354 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1, mips32
->isa_mode
);
357 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
359 mips32_restore_context(target
);
361 /* the front-end may request us not to handle breakpoints */
362 if (handle_breakpoints
)
364 /* Single step past breakpoint at current address */
365 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
367 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
368 mips_m4k_unset_breakpoint(target
, breakpoint
);
369 mips_m4k_single_step_core(target
);
370 mips_m4k_set_breakpoint(target
, breakpoint
);
374 /* enable interrupts if we are running */
375 mips32_enable_interrupts(target
, !debug_execution
);
377 /* exit debug mode */
378 mips_ejtag_exit_debug(ejtag_info
);
379 target
->debug_reason
= DBG_REASON_NOTHALTED
;
381 /* registers are now invalid */
382 register_cache_invalidate(mips32
->core_cache
);
384 if (!debug_execution
)
386 target
->state
= TARGET_RUNNING
;
387 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
388 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
392 target
->state
= TARGET_DEBUG_RUNNING
;
393 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
394 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
400 int mips_m4k_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
402 /* get pointers to arch-specific information */
403 struct mips32_common
*mips32
= target_to_mips32(target
);
404 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
405 struct breakpoint
*breakpoint
= NULL
;
407 if (target
->state
!= TARGET_HALTED
)
409 LOG_WARNING("target not halted");
410 return ERROR_TARGET_NOT_HALTED
;
413 /* current = 1: continue on current pc, otherwise continue at <address> */
415 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
417 /* the front-end may request us not to handle breakpoints */
418 if (handle_breakpoints
) {
419 breakpoint
= breakpoint_find(target
,
420 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
422 mips_m4k_unset_breakpoint(target
, breakpoint
);
425 /* restore context */
426 mips32_restore_context(target
);
428 /* configure single step mode */
429 mips_ejtag_config_step(ejtag_info
, 1);
431 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
433 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
435 /* disable interrupts while stepping */
436 mips32_enable_interrupts(target
, 0);
438 /* exit debug mode */
439 mips_ejtag_exit_debug(ejtag_info
);
441 /* registers are now invalid */
442 register_cache_invalidate(mips32
->core_cache
);
445 mips_m4k_set_breakpoint(target
, breakpoint
);
447 LOG_DEBUG("target stepped ");
449 mips_m4k_debug_entry(target
);
450 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
455 void mips_m4k_enable_breakpoints(struct target
*target
)
457 struct breakpoint
*breakpoint
= target
->breakpoints
;
459 /* set any pending breakpoints */
462 if (breakpoint
->set
== 0)
463 mips_m4k_set_breakpoint(target
, breakpoint
);
464 breakpoint
= breakpoint
->next
;
468 int mips_m4k_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
470 struct mips32_common
*mips32
= target_to_mips32(target
);
471 struct mips32_comparator
* comparator_list
= mips32
->inst_break_list
;
476 LOG_WARNING("breakpoint already set");
480 if (breakpoint
->type
== BKPT_HARD
)
484 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
486 if (bp_num
>= mips32
->num_inst_bpoints
)
488 LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
489 breakpoint
->unique_id
);
492 breakpoint
->set
= bp_num
+ 1;
493 comparator_list
[bp_num
].used
= 1;
494 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
495 target_write_u32(target
, comparator_list
[bp_num
].reg_address
, comparator_list
[bp_num
].bp_value
);
496 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x08, 0x00000000);
497 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 1);
498 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32
"",
499 breakpoint
->unique_id
,
500 bp_num
, comparator_list
[bp_num
].bp_value
);
502 else if (breakpoint
->type
== BKPT_SOFT
)
504 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
505 if (breakpoint
->length
== 4)
507 uint32_t verify
= 0xffffffff;
509 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
510 breakpoint
->orig_instr
)) != ERROR_OK
)
514 if ((retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP
)) != ERROR_OK
)
519 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
523 if (verify
!= MIPS32_SDBBP
)
525 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
531 uint16_t verify
= 0xffff;
533 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
534 breakpoint
->orig_instr
)) != ERROR_OK
)
538 if ((retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP
)) != ERROR_OK
)
543 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
547 if (verify
!= MIPS16_SDBBP
)
549 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
554 breakpoint
->set
= 20; /* Any nice value but 0 */
560 int mips_m4k_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
562 /* get pointers to arch-specific information */
563 struct mips32_common
*mips32
= target_to_mips32(target
);
564 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
567 if (!breakpoint
->set
)
569 LOG_WARNING("breakpoint not set");
573 if (breakpoint
->type
== BKPT_HARD
)
575 int bp_num
= breakpoint
->set
- 1;
576 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
))
578 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
579 breakpoint
->unique_id
);
582 LOG_DEBUG("bpid: %d - releasing hw: %d",
583 breakpoint
->unique_id
,
585 comparator_list
[bp_num
].used
= 0;
586 comparator_list
[bp_num
].bp_value
= 0;
587 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 0);
592 /* restore original instruction (kept in target endianness) */
593 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
594 if (breakpoint
->length
== 4)
596 uint32_t current_instr
;
598 /* check that user program has not modified breakpoint instruction */
599 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1,
600 (uint8_t*)¤t_instr
)) != ERROR_OK
)
604 if (current_instr
== MIPS32_SDBBP
)
606 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1,
607 breakpoint
->orig_instr
)) != ERROR_OK
)
615 uint16_t current_instr
;
617 /* check that user program has not modified breakpoint instruction */
618 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1,
619 (uint8_t*)¤t_instr
)) != ERROR_OK
)
624 if (current_instr
== MIPS16_SDBBP
)
626 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1,
627 breakpoint
->orig_instr
)) != ERROR_OK
)
639 int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
641 struct mips32_common
*mips32
= target_to_mips32(target
);
643 if (breakpoint
->type
== BKPT_HARD
)
645 if (mips32
->num_inst_bpoints_avail
< 1)
647 LOG_INFO("no hardware breakpoint available");
648 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
651 mips32
->num_inst_bpoints_avail
--;
654 mips_m4k_set_breakpoint(target
, breakpoint
);
659 int mips_m4k_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
661 /* get pointers to arch-specific information */
662 struct mips32_common
*mips32
= target_to_mips32(target
);
664 if (target
->state
!= TARGET_HALTED
)
666 LOG_WARNING("target not halted");
667 return ERROR_TARGET_NOT_HALTED
;
672 mips_m4k_unset_breakpoint(target
, breakpoint
);
675 if (breakpoint
->type
== BKPT_HARD
)
676 mips32
->num_inst_bpoints_avail
++;
681 int mips_m4k_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
683 struct mips32_common
*mips32
= target_to_mips32(target
);
684 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
687 * watchpoint enabled, ignore all byte lanes in value register
688 * and exclude both load and store accesses from watchpoint
689 * condition evaluation
691 int enable
= EJTAG_DBCn_NOSB
| EJTAG_DBCn_NOLB
| EJTAG_DBCn_BE
|
692 (0xff << EJTAG_DBCn_BLM_SHIFT
);
696 LOG_WARNING("watchpoint already set");
700 while(comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
702 if (wp_num
>= mips32
->num_data_bpoints
)
704 LOG_ERROR("Can not find free FP Comparator");
708 if (watchpoint
->length
!= 4)
710 LOG_ERROR("Only watchpoints of length 4 are supported");
711 return ERROR_TARGET_UNALIGNED_ACCESS
;
714 if (watchpoint
->address
% 4)
716 LOG_ERROR("Watchpoints address should be word aligned");
717 return ERROR_TARGET_UNALIGNED_ACCESS
;
720 switch (watchpoint
->rw
)
723 enable
&= ~EJTAG_DBCn_NOLB
;
726 enable
&= ~EJTAG_DBCn_NOSB
;
729 enable
&= ~(EJTAG_DBCn_NOLB
| EJTAG_DBCn_NOSB
);
732 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
735 watchpoint
->set
= wp_num
+ 1;
736 comparator_list
[wp_num
].used
= 1;
737 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
738 target_write_u32(target
, comparator_list
[wp_num
].reg_address
, comparator_list
[wp_num
].bp_value
);
739 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x08, 0x00000000);
740 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x10, 0x00000000);
741 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, enable
);
742 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x20, 0);
743 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
748 int mips_m4k_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
750 /* get pointers to arch-specific information */
751 struct mips32_common
*mips32
= target_to_mips32(target
);
752 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
754 if (!watchpoint
->set
)
756 LOG_WARNING("watchpoint not set");
760 int wp_num
= watchpoint
->set
- 1;
761 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
))
763 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
766 comparator_list
[wp_num
].used
= 0;
767 comparator_list
[wp_num
].bp_value
= 0;
768 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, 0);
774 int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
776 struct mips32_common
*mips32
= target_to_mips32(target
);
778 if (mips32
->num_data_bpoints_avail
< 1)
780 LOG_INFO("no hardware watchpoints available");
781 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
784 mips32
->num_data_bpoints_avail
--;
786 mips_m4k_set_watchpoint(target
, watchpoint
);
790 int mips_m4k_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
792 /* get pointers to arch-specific information */
793 struct mips32_common
*mips32
= target_to_mips32(target
);
795 if (target
->state
!= TARGET_HALTED
)
797 LOG_WARNING("target not halted");
798 return ERROR_TARGET_NOT_HALTED
;
803 mips_m4k_unset_watchpoint(target
, watchpoint
);
806 mips32
->num_data_bpoints_avail
++;
811 void mips_m4k_enable_watchpoints(struct target
*target
)
813 struct watchpoint
*watchpoint
= target
->watchpoints
;
815 /* set any pending watchpoints */
818 if (watchpoint
->set
== 0)
819 mips_m4k_set_watchpoint(target
, watchpoint
);
820 watchpoint
= watchpoint
->next
;
824 int mips_m4k_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
826 struct mips32_common
*mips32
= target_to_mips32(target
);
827 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
829 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
831 if (target
->state
!= TARGET_HALTED
)
833 LOG_WARNING("target not halted");
834 return ERROR_TARGET_NOT_HALTED
;
837 /* sanitize arguments */
838 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
839 return ERROR_INVALID_ARGUMENTS
;
841 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
842 return ERROR_TARGET_UNALIGNED_ACCESS
;
844 /* if noDMA off, use DMAACC mode for memory read */
846 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
847 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
849 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
850 if (ERROR_OK
!= retval
)
856 int mips_m4k_write_memory(struct target
*target
, uint32_t address
, uint32_t size
,
857 uint32_t count
, uint8_t *buffer
)
859 struct mips32_common
*mips32
= target_to_mips32(target
);
860 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
862 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
863 address
, size
, count
);
865 if (target
->state
!= TARGET_HALTED
)
867 LOG_WARNING("target not halted");
868 return ERROR_TARGET_NOT_HALTED
;
871 /* sanitize arguments */
872 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
873 return ERROR_INVALID_ARGUMENTS
;
875 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
876 return ERROR_TARGET_UNALIGNED_ACCESS
;
878 /* if noDMA off, use DMAACC mode for memory write */
879 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
880 return mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
882 return mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
885 int mips_m4k_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
887 mips32_build_reg_cache(target
);
892 int mips_m4k_init_arch_info(struct target
*target
, struct mips_m4k_common
*mips_m4k
,
893 struct jtag_tap
*tap
)
895 struct mips32_common
*mips32
= &mips_m4k
->mips32
;
897 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
899 /* initialize mips4k specific info */
900 mips32_init_arch_info(target
, mips32
, tap
);
901 mips32
->arch_info
= mips_m4k
;
906 int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
908 struct mips_m4k_common
*mips_m4k
= calloc(1, sizeof(struct mips_m4k_common
));
910 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
915 int mips_m4k_examine(struct target
*target
)
918 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
919 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
922 if (!target_was_examined(target
))
924 mips_ejtag_get_idcode(ejtag_info
, &idcode
);
925 ejtag_info
->idcode
= idcode
;
927 if (((idcode
>> 1) & 0x7FF) == 0x29)
929 /* we are using a pic32mx so select ejtag port
930 * as it is not selected by default */
931 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
932 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
933 mips_m4k
->is_pic32mx
= true;
937 /* init rest of ejtag interface */
938 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
941 if ((retval
= mips32_examine(target
)) != ERROR_OK
)
947 int mips_m4k_bulk_write_memory(struct target
*target
, uint32_t address
,
948 uint32_t count
, uint8_t *buffer
)
950 struct mips32_common
*mips32
= target_to_mips32(target
);
951 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
952 struct working_area
*source
;
956 LOG_DEBUG("address: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, count
);
958 if (target
->state
!= TARGET_HALTED
)
960 LOG_WARNING("target not halted");
961 return ERROR_TARGET_NOT_HALTED
;
964 /* check alignment */
966 return ERROR_TARGET_UNALIGNED_ACCESS
;
968 /* Get memory for block write handler */
969 retval
= target_alloc_working_area(target
, MIPS32_FASTDATA_HANDLER_SIZE
, &source
);
970 if (retval
!= ERROR_OK
)
972 LOG_WARNING("No working area available, falling back to non-bulk write");
973 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
976 /* TAP data register is loaded LSB first (little endian) */
977 if (target
->endianness
== TARGET_BIG_ENDIAN
)
980 for(i
= 0; i
< (count
* 4); i
+= 4)
982 t32
= be_to_h_u32((uint8_t *) &buffer
[i
]);
983 h_u32_to_le(&buffer
[i
], t32
);
987 retval
= mips32_pracc_fastdata_xfer(ejtag_info
, source
, write_t
, address
,
988 count
, (uint32_t*) buffer
);
989 if (retval
!= ERROR_OK
)
991 /* FASTDATA access failed, try normal memory write */
992 LOG_DEBUG("Fastdata access Failed, falling back to non-bulk write");
993 retval
= mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
997 target_free_working_area(target
, source
);
1002 struct target_type mips_m4k_target
=
1006 .poll
= mips_m4k_poll
,
1007 .arch_state
= mips32_arch_state
,
1009 .target_request_data
= NULL
,
1011 .halt
= mips_m4k_halt
,
1012 .resume
= mips_m4k_resume
,
1013 .step
= mips_m4k_step
,
1015 .assert_reset
= mips_m4k_assert_reset
,
1016 .deassert_reset
= mips_m4k_deassert_reset
,
1017 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
1019 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
1021 .read_memory
= mips_m4k_read_memory
,
1022 .write_memory
= mips_m4k_write_memory
,
1023 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
1024 .checksum_memory
= mips32_checksum_memory
,
1025 .blank_check_memory
= mips32_blank_check_memory
,
1027 .run_algorithm
= mips32_run_algorithm
,
1029 .add_breakpoint
= mips_m4k_add_breakpoint
,
1030 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
1031 .add_watchpoint
= mips_m4k_add_watchpoint
,
1032 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
1034 .target_create
= mips_m4k_target_create
,
1035 .init_target
= mips_m4k_init_target
,
1036 .examine
= mips_m4k_examine
,
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