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Audit and eliminate redundant #include directives in other target files.
[openocd.git] / src / target / mips_m4k.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "mips32.h"
27 #include "mips_m4k.h"
28 #include "mips32_dmaacc.h"
29
30
31 /* cli handling */
32
33 /* forward declarations */
34 int mips_m4k_poll(target_t *target);
35 int mips_m4k_halt(struct target_s *target);
36 int mips_m4k_soft_reset_halt(struct target_s *target);
37 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
38 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
39 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
40 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
41 int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
42 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
43 int mips_m4k_quit(void);
44 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp);
45
46 int mips_m4k_examine(struct target_s *target);
47 int mips_m4k_assert_reset(target_t *target);
48 int mips_m4k_deassert_reset(target_t *target);
49 int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum);
50
51 target_type_t mips_m4k_target =
52 {
53 .name = "mips_m4k",
54
55 .poll = mips_m4k_poll,
56 .arch_state = mips32_arch_state,
57
58 .target_request_data = NULL,
59
60 .halt = mips_m4k_halt,
61 .resume = mips_m4k_resume,
62 .step = mips_m4k_step,
63
64 .assert_reset = mips_m4k_assert_reset,
65 .deassert_reset = mips_m4k_deassert_reset,
66 .soft_reset_halt = mips_m4k_soft_reset_halt,
67
68 .get_gdb_reg_list = mips32_get_gdb_reg_list,
69
70 .read_memory = mips_m4k_read_memory,
71 .write_memory = mips_m4k_write_memory,
72 .bulk_write_memory = mips_m4k_bulk_write_memory,
73 .checksum_memory = mips_m4k_checksum_memory,
74 .blank_check_memory = NULL,
75
76 .run_algorithm = mips32_run_algorithm,
77
78 .add_breakpoint = mips_m4k_add_breakpoint,
79 .remove_breakpoint = mips_m4k_remove_breakpoint,
80 .add_watchpoint = mips_m4k_add_watchpoint,
81 .remove_watchpoint = mips_m4k_remove_watchpoint,
82
83 .register_commands = mips_m4k_register_commands,
84 .target_create = mips_m4k_target_create,
85 .init_target = mips_m4k_init_target,
86 .examine = mips_m4k_examine,
87 .quit = mips_m4k_quit
88 };
89
90 int mips_m4k_examine_debug_reason(target_t *target)
91 {
92 u32 break_status;
93 int retval;
94
95 if ((target->debug_reason != DBG_REASON_DBGRQ)
96 && (target->debug_reason != DBG_REASON_SINGLESTEP))
97 {
98 /* get info about inst breakpoint support */
99 if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
100 return retval;
101 if (break_status & 0x1f)
102 {
103 /* we have halted on a breakpoint */
104 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
105 return retval;
106 target->debug_reason = DBG_REASON_BREAKPOINT;
107 }
108
109 /* get info about data breakpoint support */
110 if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
111 return retval;
112 if (break_status & 0x1f)
113 {
114 /* we have halted on a breakpoint */
115 if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
116 return retval;
117 target->debug_reason = DBG_REASON_WATCHPOINT;
118 }
119 }
120
121 return ERROR_OK;
122 }
123
124 int mips_m4k_debug_entry(target_t *target)
125 {
126 mips32_common_t *mips32 = target->arch_info;
127 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
128 u32 debug_reg;
129
130 /* read debug register */
131 mips_ejtag_read_debug(ejtag_info, &debug_reg);
132
133 /* make sure break uit configured */
134 mips32_configure_break_unit(target);
135
136 /* attempt to find halt reason */
137 mips_m4k_examine_debug_reason(target);
138
139 /* clear single step if active */
140 if (debug_reg & EJTAG_DEBUG_DSS)
141 {
142 /* stopped due to single step - clear step bit */
143 mips_ejtag_config_step(ejtag_info, 0);
144 }
145
146 mips32_save_context(target);
147
148 LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
149 *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
150 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
151
152 return ERROR_OK;
153 }
154
155 int mips_m4k_poll(target_t *target)
156 {
157 int retval;
158 mips32_common_t *mips32 = target->arch_info;
159 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
160 u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
161
162 /* read ejtag control reg */
163 jtag_add_end_state(TAP_IDLE);
164 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
165 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
166
167 /* clear this bit before handling polling
168 * as after reset registers will read zero */
169 if (ejtag_ctrl & EJTAG_CTRL_ROCC)
170 {
171 /* we have detected a reset, clear flag
172 * otherwise ejtag will not work */
173 jtag_add_end_state(TAP_IDLE);
174 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
175
176 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
177 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
178 LOG_DEBUG("Reset Detected");
179 }
180
181 /* check for processor halted */
182 if (ejtag_ctrl & EJTAG_CTRL_BRKST)
183 {
184 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
185 {
186 jtag_add_end_state(TAP_IDLE);
187 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
188
189 target->state = TARGET_HALTED;
190
191 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
192 return retval;
193
194 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
195 }
196 else if (target->state == TARGET_DEBUG_RUNNING)
197 {
198 target->state = TARGET_HALTED;
199
200 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
201 return retval;
202
203 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
204 }
205 }
206 else
207 {
208 target->state = TARGET_RUNNING;
209 }
210
211 // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
212
213 return ERROR_OK;
214 }
215
216 int mips_m4k_halt(struct target_s *target)
217 {
218 mips32_common_t *mips32 = target->arch_info;
219 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
220
221 LOG_DEBUG("target->state: %s",
222 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
223
224 if (target->state == TARGET_HALTED)
225 {
226 LOG_DEBUG("target was already halted");
227 return ERROR_OK;
228 }
229
230 if (target->state == TARGET_UNKNOWN)
231 {
232 LOG_WARNING("target was in unknown state when halt was requested");
233 }
234
235 if (target->state == TARGET_RESET)
236 {
237 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
238 {
239 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
240 return ERROR_TARGET_FAILURE;
241 }
242 else
243 {
244 /* we came here in a reset_halt or reset_init sequence
245 * debug entry was already prepared in mips32_prepare_reset_halt()
246 */
247 target->debug_reason = DBG_REASON_DBGRQ;
248
249 return ERROR_OK;
250 }
251 }
252
253 /* break processor */
254 mips_ejtag_enter_debug(ejtag_info);
255
256 target->debug_reason = DBG_REASON_DBGRQ;
257
258 return ERROR_OK;
259 }
260
261 int mips_m4k_assert_reset(target_t *target)
262 {
263 mips32_common_t *mips32 = target->arch_info;
264 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
265
266 LOG_DEBUG("target->state: %s",
267 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
268
269 if (!(jtag_reset_config & RESET_HAS_SRST))
270 {
271 LOG_ERROR("Can't assert SRST");
272 return ERROR_FAIL;
273 }
274
275 if (target->reset_halt)
276 {
277 /* use hardware to catch reset */
278 jtag_add_end_state(TAP_IDLE);
279 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
280 }
281 else
282 {
283 jtag_add_end_state(TAP_IDLE);
284 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
285 }
286
287 if (strcmp(target->variant, "ejtag_srst") == 0)
288 {
289 u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
290 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
291 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
292 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
293 }
294 else
295 {
296 /* here we should issue a srst only, but we may have to assert trst as well */
297 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
298 {
299 jtag_add_reset(1, 1);
300 }
301 else
302 {
303 jtag_add_reset(0, 1);
304 }
305 }
306
307 target->state = TARGET_RESET;
308 jtag_add_sleep(50000);
309
310 mips32_invalidate_core_regs(target);
311
312 if (target->reset_halt)
313 {
314 int retval;
315 if ((retval = target_halt(target))!=ERROR_OK)
316 return retval;
317 }
318
319 return ERROR_OK;
320 }
321
322 int mips_m4k_deassert_reset(target_t *target)
323 {
324 LOG_DEBUG("target->state: %s",
325 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
326
327 /* deassert reset lines */
328 jtag_add_reset(0, 0);
329
330 return ERROR_OK;
331 }
332
333 int mips_m4k_soft_reset_halt(struct target_s *target)
334 {
335 /* TODO */
336 return ERROR_OK;
337 }
338
339 int mips_m4k_single_step_core(target_t *target)
340 {
341 mips32_common_t *mips32 = target->arch_info;
342 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
343
344 /* configure single step mode */
345 mips_ejtag_config_step(ejtag_info, 1);
346
347 /* exit debug mode */
348 mips_ejtag_exit_debug(ejtag_info, 1);
349
350 mips_m4k_debug_entry(target);
351
352 return ERROR_OK;
353 }
354
355 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
356 {
357 mips32_common_t *mips32 = target->arch_info;
358 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
359 breakpoint_t *breakpoint = NULL;
360 u32 resume_pc;
361
362 if (target->state != TARGET_HALTED)
363 {
364 LOG_WARNING("target not halted");
365 return ERROR_TARGET_NOT_HALTED;
366 }
367
368 if (!debug_execution)
369 {
370 target_free_all_working_areas(target);
371 mips_m4k_enable_breakpoints(target);
372 mips_m4k_enable_watchpoints(target);
373 }
374
375 /* current = 1: continue on current pc, otherwise continue at <address> */
376 if (!current)
377 {
378 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
379 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
380 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
381 }
382
383 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
384
385 mips32_restore_context(target);
386
387 /* the front-end may request us not to handle breakpoints */
388 if (handle_breakpoints)
389 {
390 /* Single step past breakpoint at current address */
391 if ((breakpoint = breakpoint_find(target, resume_pc)))
392 {
393 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
394 mips_m4k_unset_breakpoint(target, breakpoint);
395 mips_m4k_single_step_core(target);
396 mips_m4k_set_breakpoint(target, breakpoint);
397 }
398 }
399
400 /* exit debug mode - enable interrupts if required */
401 mips_ejtag_exit_debug(ejtag_info, !debug_execution);
402 target->debug_reason = DBG_REASON_NOTHALTED;
403
404 /* registers are now invalid */
405 mips32_invalidate_core_regs(target);
406
407 if (!debug_execution)
408 {
409 target->state = TARGET_RUNNING;
410 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
411 LOG_DEBUG("target resumed at 0x%x", resume_pc);
412 }
413 else
414 {
415 target->state = TARGET_DEBUG_RUNNING;
416 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
417 LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
418 }
419
420 return ERROR_OK;
421 }
422
423 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
424 {
425 /* get pointers to arch-specific information */
426 mips32_common_t *mips32 = target->arch_info;
427 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
428 breakpoint_t *breakpoint = NULL;
429
430 if (target->state != TARGET_HALTED)
431 {
432 LOG_WARNING("target not halted");
433 return ERROR_TARGET_NOT_HALTED;
434 }
435
436 /* current = 1: continue on current pc, otherwise continue at <address> */
437 if (!current)
438 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
439
440 /* the front-end may request us not to handle breakpoints */
441 if (handle_breakpoints)
442 if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
443 mips_m4k_unset_breakpoint(target, breakpoint);
444
445 /* restore context */
446 mips32_restore_context(target);
447
448 /* configure single step mode */
449 mips_ejtag_config_step(ejtag_info, 1);
450
451 target->debug_reason = DBG_REASON_SINGLESTEP;
452
453 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
454
455 /* exit debug mode */
456 mips_ejtag_exit_debug(ejtag_info, 1);
457
458 /* registers are now invalid */
459 mips32_invalidate_core_regs(target);
460
461 if (breakpoint)
462 mips_m4k_set_breakpoint(target, breakpoint);
463
464 LOG_DEBUG("target stepped ");
465
466 mips_m4k_debug_entry(target);
467 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
468
469 return ERROR_OK;
470 }
471
472 void mips_m4k_enable_breakpoints(struct target_s *target)
473 {
474 breakpoint_t *breakpoint = target->breakpoints;
475
476 /* set any pending breakpoints */
477 while (breakpoint)
478 {
479 if (breakpoint->set == 0)
480 mips_m4k_set_breakpoint(target, breakpoint);
481 breakpoint = breakpoint->next;
482 }
483 }
484
485 int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
486 {
487 mips32_common_t *mips32 = target->arch_info;
488 mips32_comparator_t * comparator_list = mips32->inst_break_list;
489 int retval;
490
491 if (breakpoint->set)
492 {
493 LOG_WARNING("breakpoint already set");
494 return ERROR_OK;
495 }
496
497 if (breakpoint->type == BKPT_HARD)
498 {
499 int bp_num = 0;
500
501 while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
502 bp_num++;
503 if (bp_num >= mips32->num_inst_bpoints)
504 {
505 LOG_DEBUG("ERROR Can not find free FP Comparator");
506 LOG_WARNING("ERROR Can not find free FP Comparator");
507 exit(-1);
508 }
509 breakpoint->set = bp_num + 1;
510 comparator_list[bp_num].used = 1;
511 comparator_list[bp_num].bp_value = breakpoint->address;
512 target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
513 target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
514 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
515 LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num, comparator_list[bp_num].bp_value);
516 }
517 else if (breakpoint->type == BKPT_SOFT)
518 {
519 if (breakpoint->length == 4)
520 {
521 u32 verify = 0xffffffff;
522
523 if((retval = target->type->read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
524 {
525 return retval;
526 }
527 if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
528 {
529 return retval;
530 }
531
532 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
533 {
534 return retval;
535 }
536 if (verify != MIPS32_SDBBP)
537 {
538 LOG_ERROR("Unable to set 32bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
539 return ERROR_OK;
540 }
541 }
542 else
543 {
544 u16 verify = 0xffff;
545
546 if((retval = target->type->read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
547 {
548 return retval;
549 }
550 if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
551 {
552 return retval;
553 }
554
555 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
556 {
557 return retval;
558 }
559 if (verify != MIPS16_SDBBP)
560 {
561 LOG_ERROR("Unable to set 16bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
562 return ERROR_OK;
563 }
564 }
565
566 breakpoint->set = 20; /* Any nice value but 0 */
567 }
568
569 return ERROR_OK;
570 }
571
572 int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
573 {
574 /* get pointers to arch-specific information */
575 mips32_common_t *mips32 = target->arch_info;
576 mips32_comparator_t * comparator_list = mips32->inst_break_list;
577 int retval;
578
579 if (!breakpoint->set)
580 {
581 LOG_WARNING("breakpoint not set");
582 return ERROR_OK;
583 }
584
585 if (breakpoint->type == BKPT_HARD)
586 {
587 int bp_num = breakpoint->set - 1;
588 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
589 {
590 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
591 return ERROR_OK;
592 }
593 comparator_list[bp_num].used = 0;
594 comparator_list[bp_num].bp_value = 0;
595 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
596 }
597 else
598 {
599 /* restore original instruction (kept in target endianness) */
600 if (breakpoint->length == 4)
601 {
602 u32 current_instr;
603
604 /* check that user program has not modified breakpoint instruction */
605 if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr)) != ERROR_OK)
606 {
607 return retval;
608 }
609 if (current_instr == MIPS32_SDBBP)
610 {
611 if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
612 {
613 return retval;
614 }
615 }
616 }
617 else
618 {
619 u16 current_instr;
620
621 /* check that user program has not modified breakpoint instruction */
622 if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr)) != ERROR_OK)
623 {
624 return retval;
625 }
626
627 if (current_instr == MIPS16_SDBBP)
628 {
629 if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
630 {
631 return retval;
632 }
633 }
634 }
635 }
636 breakpoint->set = 0;
637
638 return ERROR_OK;
639 }
640
641 int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
642 {
643 mips32_common_t *mips32 = target->arch_info;
644
645 if (breakpoint->type == BKPT_HARD)
646 {
647 if (mips32->num_inst_bpoints_avail < 1)
648 {
649 LOG_INFO("no hardware breakpoint available");
650 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
651 }
652
653 mips32->num_inst_bpoints_avail--;
654 }
655
656 mips_m4k_set_breakpoint(target, breakpoint);
657
658 return ERROR_OK;
659 }
660
661 int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
662 {
663 /* get pointers to arch-specific information */
664 mips32_common_t *mips32 = target->arch_info;
665
666 if (target->state != TARGET_HALTED)
667 {
668 LOG_WARNING("target not halted");
669 return ERROR_TARGET_NOT_HALTED;
670 }
671
672 if (breakpoint->set)
673 {
674 mips_m4k_unset_breakpoint(target, breakpoint);
675 }
676
677 if (breakpoint->type == BKPT_HARD)
678 mips32->num_inst_bpoints_avail++;
679
680 return ERROR_OK;
681 }
682
683 int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
684 {
685 /* TODO */
686 return ERROR_OK;
687 }
688
689 int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
690 {
691 /* TODO */
692 return ERROR_OK;
693 }
694
695 int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
696 {
697 /* TODO */
698 return ERROR_OK;
699 }
700
701 int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
702 {
703 /* TODO */
704 return ERROR_OK;
705 }
706
707 void mips_m4k_enable_watchpoints(struct target_s *target)
708 {
709 watchpoint_t *watchpoint = target->watchpoints;
710
711 /* set any pending watchpoints */
712 while (watchpoint)
713 {
714 if (watchpoint->set == 0)
715 mips_m4k_set_watchpoint(target, watchpoint);
716 watchpoint = watchpoint->next;
717 }
718 }
719
720 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
721 {
722 mips32_common_t *mips32 = target->arch_info;
723 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
724
725 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
726
727 if (target->state != TARGET_HALTED)
728 {
729 LOG_WARNING("target not halted");
730 return ERROR_TARGET_NOT_HALTED;
731 }
732
733 /* sanitize arguments */
734 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
735 return ERROR_INVALID_ARGUMENTS;
736
737 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
738 return ERROR_TARGET_UNALIGNED_ACCESS;
739
740 switch (size)
741 {
742 case 4:
743 case 2:
744 case 1:
745 /* if noDMA off, use DMAACC mode for memory read */
746 if(ejtag_info->impcode & EJTAG_IMP_NODMA)
747 return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
748 else
749 return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
750 default:
751 LOG_ERROR("BUG: we shouldn't get here");
752 exit(-1);
753 break;
754 }
755
756 return ERROR_OK;
757 }
758
759 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
760 {
761 mips32_common_t *mips32 = target->arch_info;
762 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
763
764 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
765
766 if (target->state != TARGET_HALTED)
767 {
768 LOG_WARNING("target not halted");
769 return ERROR_TARGET_NOT_HALTED;
770 }
771
772 /* sanitize arguments */
773 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
774 return ERROR_INVALID_ARGUMENTS;
775
776 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
777 return ERROR_TARGET_UNALIGNED_ACCESS;
778
779 switch (size)
780 {
781 case 4:
782 case 2:
783 case 1:
784 /* if noDMA off, use DMAACC mode for memory write */
785 if(ejtag_info->impcode & EJTAG_IMP_NODMA)
786 mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
787 else
788 mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
789 break;
790 default:
791 LOG_ERROR("BUG: we shouldn't get here");
792 exit(-1);
793 break;
794 }
795
796 return ERROR_OK;
797 }
798
799 int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
800 {
801 int retval;
802
803 retval = mips32_register_commands(cmd_ctx);
804 return retval;
805 }
806
807 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
808 {
809 mips32_build_reg_cache(target);
810
811 return ERROR_OK;
812 }
813
814 int mips_m4k_quit(void)
815 {
816 return ERROR_OK;
817 }
818
819 int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
820 {
821 mips32_common_t *mips32 = &mips_m4k->mips32_common;
822
823 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
824
825 /* initialize mips4k specific info */
826 mips32_init_arch_info(target, mips32, tap);
827 mips32->arch_info = mips_m4k;
828
829 return ERROR_OK;
830 }
831
832 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
833 {
834 mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
835
836 mips_m4k_init_arch_info(target, mips_m4k, target->tap);
837
838 return ERROR_OK;
839 }
840
841 int mips_m4k_examine(struct target_s *target)
842 {
843 int retval;
844 mips32_common_t *mips32 = target->arch_info;
845 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
846 u32 idcode = 0;
847
848 if (!target->type->examined)
849 {
850 mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
851 ejtag_info->idcode = idcode;
852
853 if (((idcode >> 1) & 0x7FF) == 0x29)
854 {
855 /* we are using a pic32mx so select ejtag port
856 * as it is not selected by default */
857 mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
858 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
859 }
860 }
861
862 /* init rest of ejtag interface */
863 if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
864 return retval;
865
866 if ((retval = mips32_examine(target)) != ERROR_OK)
867 return retval;
868
869 return ERROR_OK;
870 }
871
872 int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
873 {
874 return mips_m4k_write_memory(target, address, 4, count, buffer);
875 }
876
877 int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum)
878 {
879 return ERROR_FAIL; /* use bulk read method */
880 }
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