1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
26 #include "breakpoints.h"
29 #include "mips32_dmaacc.h"
30 #include "target_type.h"
35 /* forward declarations */
36 int mips_m4k_poll(struct target
*target
);
37 int mips_m4k_halt(struct target
*target
);
38 int mips_m4k_soft_reset_halt(struct target
*target
);
39 int mips_m4k_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
);
40 int mips_m4k_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
);
41 int mips_m4k_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
42 int mips_m4k_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
43 int mips_m4k_register_commands(struct command_context
*cmd_ctx
);
44 int mips_m4k_init_target(struct command_context
*cmd_ctx
, struct target
*target
);
45 int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
);
47 int mips_m4k_examine(struct target
*target
);
48 int mips_m4k_assert_reset(struct target
*target
);
49 int mips_m4k_deassert_reset(struct target
*target
);
50 int mips_m4k_checksum_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t *checksum
);
52 struct target_type mips_m4k_target
=
56 .poll
= mips_m4k_poll
,
57 .arch_state
= mips32_arch_state
,
59 .target_request_data
= NULL
,
61 .halt
= mips_m4k_halt
,
62 .resume
= mips_m4k_resume
,
63 .step
= mips_m4k_step
,
65 .assert_reset
= mips_m4k_assert_reset
,
66 .deassert_reset
= mips_m4k_deassert_reset
,
67 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
69 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
71 .read_memory
= mips_m4k_read_memory
,
72 .write_memory
= mips_m4k_write_memory
,
73 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
74 .checksum_memory
= mips_m4k_checksum_memory
,
75 .blank_check_memory
= NULL
,
77 .run_algorithm
= mips32_run_algorithm
,
79 .add_breakpoint
= mips_m4k_add_breakpoint
,
80 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
81 .add_watchpoint
= mips_m4k_add_watchpoint
,
82 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
84 .register_commands
= mips_m4k_register_commands
,
85 .target_create
= mips_m4k_target_create
,
86 .init_target
= mips_m4k_init_target
,
87 .examine
= mips_m4k_examine
,
90 int mips_m4k_examine_debug_reason(struct target
*target
)
92 uint32_t break_status
;
95 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
96 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
98 /* get info about inst breakpoint support */
99 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &break_status
)) != ERROR_OK
)
101 if (break_status
& 0x1f)
103 /* we have halted on a breakpoint */
104 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
106 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
109 /* get info about data breakpoint support */
110 if ((retval
= target_read_u32(target
, 0xFF302000, &break_status
)) != ERROR_OK
)
112 if (break_status
& 0x1f)
114 /* we have halted on a breakpoint */
115 if ((retval
= target_write_u32(target
, 0xFF302000, 0)) != ERROR_OK
)
117 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
124 int mips_m4k_debug_entry(struct target
*target
)
126 struct mips32_common
*mips32
= target
->arch_info
;
127 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
130 /* read debug register */
131 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
133 /* make sure break uit configured */
134 mips32_configure_break_unit(target
);
136 /* attempt to find halt reason */
137 mips_m4k_examine_debug_reason(target
);
139 /* clear single step if active */
140 if (debug_reg
& EJTAG_DEBUG_DSS
)
142 /* stopped due to single step - clear step bit */
143 mips_ejtag_config_step(ejtag_info
, 0);
146 mips32_save_context(target
);
148 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
149 *(uint32_t*)(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
),
150 target_state_name(target
));
155 int mips_m4k_poll(struct target
*target
)
158 struct mips32_common
*mips32
= target
->arch_info
;
159 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
160 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
162 /* read ejtag control reg */
163 jtag_set_end_state(TAP_IDLE
);
164 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
165 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
167 /* clear this bit before handling polling
168 * as after reset registers will read zero */
169 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
171 /* we have detected a reset, clear flag
172 * otherwise ejtag will not work */
173 jtag_set_end_state(TAP_IDLE
);
174 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
176 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
177 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
178 LOG_DEBUG("Reset Detected");
181 /* check for processor halted */
182 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
184 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
186 jtag_set_end_state(TAP_IDLE
);
187 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
189 target
->state
= TARGET_HALTED
;
191 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
194 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
196 else if (target
->state
== TARGET_DEBUG_RUNNING
)
198 target
->state
= TARGET_HALTED
;
200 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
203 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
208 target
->state
= TARGET_RUNNING
;
211 // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
216 int mips_m4k_halt(struct target
*target
)
218 struct mips32_common
*mips32
= target
->arch_info
;
219 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
221 LOG_DEBUG("target->state: %s",
222 target_state_name(target
));
224 if (target
->state
== TARGET_HALTED
)
226 LOG_DEBUG("target was already halted");
230 if (target
->state
== TARGET_UNKNOWN
)
232 LOG_WARNING("target was in unknown state when halt was requested");
235 if (target
->state
== TARGET_RESET
)
237 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
239 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
240 return ERROR_TARGET_FAILURE
;
244 /* we came here in a reset_halt or reset_init sequence
245 * debug entry was already prepared in mips32_prepare_reset_halt()
247 target
->debug_reason
= DBG_REASON_DBGRQ
;
253 /* break processor */
254 mips_ejtag_enter_debug(ejtag_info
);
256 target
->debug_reason
= DBG_REASON_DBGRQ
;
261 int mips_m4k_assert_reset(struct target
*target
)
263 struct mips32_common
*mips32
= target
->arch_info
;
264 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
266 LOG_DEBUG("target->state: %s",
267 target_state_name(target
));
269 enum reset_types jtag_reset_config
= jtag_get_reset_config();
270 if (!(jtag_reset_config
& RESET_HAS_SRST
))
272 LOG_ERROR("Can't assert SRST");
276 if (target
->reset_halt
)
278 /* use hardware to catch reset */
279 jtag_set_end_state(TAP_IDLE
);
280 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
, NULL
);
284 jtag_set_end_state(TAP_IDLE
);
285 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
288 if (strcmp(target
->variant
, "ejtag_srst") == 0)
290 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
291 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
292 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
293 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
297 /* here we should issue a srst only, but we may have to assert trst as well */
298 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
300 jtag_add_reset(1, 1);
304 jtag_add_reset(0, 1);
308 target
->state
= TARGET_RESET
;
309 jtag_add_sleep(50000);
311 mips32_invalidate_core_regs(target
);
313 if (target
->reset_halt
)
316 if ((retval
= target_halt(target
)) != ERROR_OK
)
323 int mips_m4k_deassert_reset(struct target
*target
)
325 LOG_DEBUG("target->state: %s",
326 target_state_name(target
));
328 /* deassert reset lines */
329 jtag_add_reset(0, 0);
334 int mips_m4k_soft_reset_halt(struct target
*target
)
340 int mips_m4k_single_step_core(struct target
*target
)
342 struct mips32_common
*mips32
= target
->arch_info
;
343 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
345 /* configure single step mode */
346 mips_ejtag_config_step(ejtag_info
, 1);
348 /* disable interrupts while stepping */
349 mips32_enable_interrupts(target
, 0);
351 /* exit debug mode */
352 mips_ejtag_exit_debug(ejtag_info
);
354 mips_m4k_debug_entry(target
);
359 int mips_m4k_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
361 struct mips32_common
*mips32
= target
->arch_info
;
362 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
363 struct breakpoint
*breakpoint
= NULL
;
366 if (target
->state
!= TARGET_HALTED
)
368 LOG_WARNING("target not halted");
369 return ERROR_TARGET_NOT_HALTED
;
372 if (!debug_execution
)
374 target_free_all_working_areas(target
);
375 mips_m4k_enable_breakpoints(target
);
376 mips_m4k_enable_watchpoints(target
);
379 /* current = 1: continue on current pc, otherwise continue at <address> */
382 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
383 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
384 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
387 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
389 mips32_restore_context(target
);
391 /* the front-end may request us not to handle breakpoints */
392 if (handle_breakpoints
)
394 /* Single step past breakpoint at current address */
395 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
397 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
398 mips_m4k_unset_breakpoint(target
, breakpoint
);
399 mips_m4k_single_step_core(target
);
400 mips_m4k_set_breakpoint(target
, breakpoint
);
404 /* enable interrupts if we are running */
405 mips32_enable_interrupts(target
, !debug_execution
);
407 /* exit debug mode */
408 mips_ejtag_exit_debug(ejtag_info
);
409 target
->debug_reason
= DBG_REASON_NOTHALTED
;
411 /* registers are now invalid */
412 mips32_invalidate_core_regs(target
);
414 if (!debug_execution
)
416 target
->state
= TARGET_RUNNING
;
417 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
418 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
422 target
->state
= TARGET_DEBUG_RUNNING
;
423 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
424 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
430 int mips_m4k_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
432 /* get pointers to arch-specific information */
433 struct mips32_common
*mips32
= target
->arch_info
;
434 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
435 struct breakpoint
*breakpoint
= NULL
;
437 if (target
->state
!= TARGET_HALTED
)
439 LOG_WARNING("target not halted");
440 return ERROR_TARGET_NOT_HALTED
;
443 /* current = 1: continue on current pc, otherwise continue at <address> */
445 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
447 /* the front-end may request us not to handle breakpoints */
448 if (handle_breakpoints
)
449 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32))))
450 mips_m4k_unset_breakpoint(target
, breakpoint
);
452 /* restore context */
453 mips32_restore_context(target
);
455 /* configure single step mode */
456 mips_ejtag_config_step(ejtag_info
, 1);
458 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
460 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
462 /* disable interrupts while stepping */
463 mips32_enable_interrupts(target
, 0);
465 /* exit debug mode */
466 mips_ejtag_exit_debug(ejtag_info
);
468 /* registers are now invalid */
469 mips32_invalidate_core_regs(target
);
472 mips_m4k_set_breakpoint(target
, breakpoint
);
474 LOG_DEBUG("target stepped ");
476 mips_m4k_debug_entry(target
);
477 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
482 void mips_m4k_enable_breakpoints(struct target
*target
)
484 struct breakpoint
*breakpoint
= target
->breakpoints
;
486 /* set any pending breakpoints */
489 if (breakpoint
->set
== 0)
490 mips_m4k_set_breakpoint(target
, breakpoint
);
491 breakpoint
= breakpoint
->next
;
495 int mips_m4k_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
497 struct mips32_common
*mips32
= target
->arch_info
;
498 struct mips32_comparator
* comparator_list
= mips32
->inst_break_list
;
503 LOG_WARNING("breakpoint already set");
507 if (breakpoint
->type
== BKPT_HARD
)
511 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
513 if (bp_num
>= mips32
->num_inst_bpoints
)
515 LOG_DEBUG("ERROR Can not find free FP Comparator(bpid: %d)",
516 breakpoint
->unique_id
);
517 LOG_WARNING("ERROR Can not find free FP Comparator");
520 breakpoint
->set
= bp_num
+ 1;
521 comparator_list
[bp_num
].used
= 1;
522 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
523 target_write_u32(target
, comparator_list
[bp_num
].reg_address
, comparator_list
[bp_num
].bp_value
);
524 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x08, 0x00000000);
525 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 1);
526 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32
"",
527 breakpoint
->unique_id
,
528 bp_num
, comparator_list
[bp_num
].bp_value
);
530 else if (breakpoint
->type
== BKPT_SOFT
)
532 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
533 if (breakpoint
->length
== 4)
535 uint32_t verify
= 0xffffffff;
537 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
541 if ((retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP
)) != ERROR_OK
)
546 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
550 if (verify
!= MIPS32_SDBBP
)
552 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
558 uint16_t verify
= 0xffff;
560 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
564 if ((retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP
)) != ERROR_OK
)
569 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
573 if (verify
!= MIPS16_SDBBP
)
575 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
580 breakpoint
->set
= 20; /* Any nice value but 0 */
586 int mips_m4k_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
588 /* get pointers to arch-specific information */
589 struct mips32_common
*mips32
= target
->arch_info
;
590 struct mips32_comparator
* comparator_list
= mips32
->inst_break_list
;
593 if (!breakpoint
->set
)
595 LOG_WARNING("breakpoint not set");
599 if (breakpoint
->type
== BKPT_HARD
)
601 int bp_num
= breakpoint
->set
- 1;
602 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
))
604 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
605 breakpoint
->unique_id
);
608 LOG_DEBUG("bpid: %d - releasing hw: %d",
609 breakpoint
->unique_id
,
611 comparator_list
[bp_num
].used
= 0;
612 comparator_list
[bp_num
].bp_value
= 0;
613 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 0);
618 /* restore original instruction (kept in target endianness) */
619 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
620 if (breakpoint
->length
== 4)
622 uint32_t current_instr
;
624 /* check that user program has not modified breakpoint instruction */
625 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
629 if (current_instr
== MIPS32_SDBBP
)
631 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
639 uint16_t current_instr
;
641 /* check that user program has not modified breakpoint instruction */
642 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
647 if (current_instr
== MIPS16_SDBBP
)
649 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
661 int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
663 struct mips32_common
*mips32
= target
->arch_info
;
665 if (breakpoint
->type
== BKPT_HARD
)
667 if (mips32
->num_inst_bpoints_avail
< 1)
669 LOG_INFO("no hardware breakpoint available");
670 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
673 mips32
->num_inst_bpoints_avail
--;
676 mips_m4k_set_breakpoint(target
, breakpoint
);
681 int mips_m4k_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
683 /* get pointers to arch-specific information */
684 struct mips32_common
*mips32
= target
->arch_info
;
686 if (target
->state
!= TARGET_HALTED
)
688 LOG_WARNING("target not halted");
689 return ERROR_TARGET_NOT_HALTED
;
694 mips_m4k_unset_breakpoint(target
, breakpoint
);
697 if (breakpoint
->type
== BKPT_HARD
)
698 mips32
->num_inst_bpoints_avail
++;
703 int mips_m4k_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
705 struct mips32_common
*mips32
= target
->arch_info
;
706 struct mips32_comparator
* comparator_list
= mips32
->data_break_list
;
709 * watchpoint enabled, ignore all byte lanes in value register
710 * and exclude both load and store accesses from watchpoint
711 * condition evaluation
713 int enable
= EJTAG_DBCn_NOSB
| EJTAG_DBCn_NOLB
| EJTAG_DBCn_BE
|
714 (0xff << EJTAG_DBCn_BLM_SHIFT
);
718 LOG_WARNING("watchpoint already set");
722 while(comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
724 if (wp_num
>= mips32
->num_data_bpoints
)
726 LOG_DEBUG("ERROR Can not find free FP Comparator");
727 LOG_WARNING("ERROR Can not find free FP Comparator");
731 if (watchpoint
->length
!= 4)
733 LOG_ERROR("Only watchpoints of length 4 are supported");
734 return ERROR_TARGET_UNALIGNED_ACCESS
;
737 if (watchpoint
->address
% 4)
739 LOG_ERROR("Watchpoints address should be word aligned");
740 return ERROR_TARGET_UNALIGNED_ACCESS
;
743 switch (watchpoint
->rw
)
746 enable
&= ~EJTAG_DBCn_NOLB
;
749 enable
&= ~EJTAG_DBCn_NOSB
;
752 enable
&= ~(EJTAG_DBCn_NOLB
| EJTAG_DBCn_NOSB
);
755 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
758 watchpoint
->set
= wp_num
+ 1;
759 comparator_list
[wp_num
].used
= 1;
760 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
761 target_write_u32(target
, comparator_list
[wp_num
].reg_address
, comparator_list
[wp_num
].bp_value
);
762 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x08, 0x00000000);
763 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x10, 0x00000000);
764 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, enable
);
765 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x20, 0);
766 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
771 int mips_m4k_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
773 /* get pointers to arch-specific information */
774 struct mips32_common
*mips32
= target
->arch_info
;
775 struct mips32_comparator
* comparator_list
= mips32
->data_break_list
;
777 if (!watchpoint
->set
)
779 LOG_WARNING("watchpoint not set");
783 int wp_num
= watchpoint
->set
- 1;
784 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
))
786 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
789 comparator_list
[wp_num
].used
= 0;
790 comparator_list
[wp_num
].bp_value
= 0;
791 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, 0);
797 int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
799 struct mips32_common
*mips32
= target
->arch_info
;
801 if (mips32
->num_data_bpoints_avail
< 1)
803 LOG_INFO("no hardware watchpoints available");
804 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
807 mips32
->num_data_bpoints_avail
--;
809 mips_m4k_set_watchpoint(target
, watchpoint
);
813 int mips_m4k_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
815 /* get pointers to arch-specific information */
816 struct mips32_common
*mips32
= target
->arch_info
;
818 if (target
->state
!= TARGET_HALTED
)
820 LOG_WARNING("target not halted");
821 return ERROR_TARGET_NOT_HALTED
;
826 mips_m4k_unset_watchpoint(target
, watchpoint
);
829 mips32
->num_data_bpoints_avail
++;
834 void mips_m4k_enable_watchpoints(struct target
*target
)
836 struct watchpoint
*watchpoint
= target
->watchpoints
;
838 /* set any pending watchpoints */
841 if (watchpoint
->set
== 0)
842 mips_m4k_set_watchpoint(target
, watchpoint
);
843 watchpoint
= watchpoint
->next
;
847 int mips_m4k_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
849 struct mips32_common
*mips32
= target
->arch_info
;
850 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
852 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
854 if (target
->state
!= TARGET_HALTED
)
856 LOG_WARNING("target not halted");
857 return ERROR_TARGET_NOT_HALTED
;
860 /* sanitize arguments */
861 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
862 return ERROR_INVALID_ARGUMENTS
;
864 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
865 return ERROR_TARGET_UNALIGNED_ACCESS
;
867 /* if noDMA off, use DMAACC mode for memory read */
869 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
870 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
872 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
873 if (ERROR_OK
!= retval
)
879 int mips_m4k_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
881 struct mips32_common
*mips32
= target
->arch_info
;
882 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
884 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
886 if (target
->state
!= TARGET_HALTED
)
888 LOG_WARNING("target not halted");
889 return ERROR_TARGET_NOT_HALTED
;
892 /* sanitize arguments */
893 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
894 return ERROR_INVALID_ARGUMENTS
;
896 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
897 return ERROR_TARGET_UNALIGNED_ACCESS
;
899 /* if noDMA off, use DMAACC mode for memory write */
900 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
901 return mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
903 return mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
906 int mips_m4k_register_commands(struct command_context
*cmd_ctx
)
910 retval
= mips32_register_commands(cmd_ctx
);
914 int mips_m4k_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
916 mips32_build_reg_cache(target
);
921 int mips_m4k_init_arch_info(struct target
*target
, struct mips_m4k_common
*mips_m4k
, struct jtag_tap
*tap
)
923 struct mips32_common
*mips32
= &mips_m4k
->mips32_common
;
925 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
927 /* initialize mips4k specific info */
928 mips32_init_arch_info(target
, mips32
, tap
);
929 mips32
->arch_info
= mips_m4k
;
934 int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
936 struct mips_m4k_common
*mips_m4k
= calloc(1,sizeof(struct mips_m4k_common
));
938 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
943 int mips_m4k_examine(struct target
*target
)
946 struct mips32_common
*mips32
= target
->arch_info
;
947 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
950 if (!target_was_examined(target
))
952 mips_ejtag_get_idcode(ejtag_info
, &idcode
);
953 ejtag_info
->idcode
= idcode
;
955 if (((idcode
>> 1) & 0x7FF) == 0x29)
957 /* we are using a pic32mx so select ejtag port
958 * as it is not selected by default */
959 mips_ejtag_set_instr(ejtag_info
, 0x05, NULL
);
960 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
964 /* init rest of ejtag interface */
965 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
968 if ((retval
= mips32_examine(target
)) != ERROR_OK
)
974 int mips_m4k_bulk_write_memory(struct target
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
976 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
979 int mips_m4k_checksum_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t *checksum
)
981 return ERROR_FAIL
; /* use bulk read method */
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