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ARMv7-M: make DAP commands verify target is an ARMv7-M
[openocd.git] / src / target / mips_m4k.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include "breakpoints.h"
29 #include "mips32.h"
30 #include "mips_m4k.h"
31 #include "mips32_dmaacc.h"
32 #include "target_type.h"
33 #include "register.h"
34
35 /* cli handling */
36
37 /* forward declarations */
38 int mips_m4k_poll(struct target *target);
39 int mips_m4k_halt(struct target *target);
40 int mips_m4k_soft_reset_halt(struct target *target);
41 int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
42 int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints);
43 int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
44 int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
45 int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target);
46 int mips_m4k_target_create(struct target *target, Jim_Interp *interp);
47
48 int mips_m4k_examine(struct target *target);
49 int mips_m4k_assert_reset(struct target *target);
50 int mips_m4k_deassert_reset(struct target *target);
51 int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum);
52
53 struct target_type mips_m4k_target =
54 {
55 .name = "mips_m4k",
56
57 .poll = mips_m4k_poll,
58 .arch_state = mips32_arch_state,
59
60 .target_request_data = NULL,
61
62 .halt = mips_m4k_halt,
63 .resume = mips_m4k_resume,
64 .step = mips_m4k_step,
65
66 .assert_reset = mips_m4k_assert_reset,
67 .deassert_reset = mips_m4k_deassert_reset,
68 .soft_reset_halt = mips_m4k_soft_reset_halt,
69
70 .get_gdb_reg_list = mips32_get_gdb_reg_list,
71
72 .read_memory = mips_m4k_read_memory,
73 .write_memory = mips_m4k_write_memory,
74 .bulk_write_memory = mips_m4k_bulk_write_memory,
75 .checksum_memory = mips_m4k_checksum_memory,
76 .blank_check_memory = NULL,
77
78 .run_algorithm = mips32_run_algorithm,
79
80 .add_breakpoint = mips_m4k_add_breakpoint,
81 .remove_breakpoint = mips_m4k_remove_breakpoint,
82 .add_watchpoint = mips_m4k_add_watchpoint,
83 .remove_watchpoint = mips_m4k_remove_watchpoint,
84
85 .target_create = mips_m4k_target_create,
86 .init_target = mips_m4k_init_target,
87 .examine = mips_m4k_examine,
88 };
89
90 int mips_m4k_examine_debug_reason(struct target *target)
91 {
92 uint32_t break_status;
93 int retval;
94
95 if ((target->debug_reason != DBG_REASON_DBGRQ)
96 && (target->debug_reason != DBG_REASON_SINGLESTEP))
97 {
98 /* get info about inst breakpoint support */
99 if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
100 return retval;
101 if (break_status & 0x1f)
102 {
103 /* we have halted on a breakpoint */
104 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
105 return retval;
106 target->debug_reason = DBG_REASON_BREAKPOINT;
107 }
108
109 /* get info about data breakpoint support */
110 if ((retval = target_read_u32(target, EJTAG_DBS, &break_status)) != ERROR_OK)
111 return retval;
112 if (break_status & 0x1f)
113 {
114 /* we have halted on a breakpoint */
115 if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
116 return retval;
117 target->debug_reason = DBG_REASON_WATCHPOINT;
118 }
119 }
120
121 return ERROR_OK;
122 }
123
124 int mips_m4k_debug_entry(struct target *target)
125 {
126 struct mips32_common *mips32 = target_to_mips32(target);
127 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
128 uint32_t debug_reg;
129
130 /* read debug register */
131 mips_ejtag_read_debug(ejtag_info, &debug_reg);
132
133 /* make sure break unit configured */
134 mips32_configure_break_unit(target);
135
136 /* attempt to find halt reason */
137 mips_m4k_examine_debug_reason(target);
138
139 /* clear single step if active */
140 if (debug_reg & EJTAG_DEBUG_DSS)
141 {
142 /* stopped due to single step - clear step bit */
143 mips_ejtag_config_step(ejtag_info, 0);
144 }
145
146 mips32_save_context(target);
147
148 /* default to mips32 isa, it will be changed below if required */
149 mips32->isa_mode = MIPS32_ISA_MIPS32;
150
151 if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
152 {
153 if (buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32) & 0x01)
154 {
155 /* core is running mips16e isa */
156 mips32->isa_mode = MIPS32_ISA_MIPS16E;
157 }
158 }
159
160 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
161 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
162 target_state_name(target));
163
164 return ERROR_OK;
165 }
166
167 int mips_m4k_poll(struct target *target)
168 {
169 int retval;
170 struct mips32_common *mips32 = target_to_mips32(target);
171 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
172 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
173
174 /* read ejtag control reg */
175 jtag_set_end_state(TAP_IDLE);
176 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
177 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
178
179 /* clear this bit before handling polling
180 * as after reset registers will read zero */
181 if (ejtag_ctrl & EJTAG_CTRL_ROCC)
182 {
183 /* we have detected a reset, clear flag
184 * otherwise ejtag will not work */
185 jtag_set_end_state(TAP_IDLE);
186 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
187
188 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
189 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
190 LOG_DEBUG("Reset Detected");
191 }
192
193 /* check for processor halted */
194 if (ejtag_ctrl & EJTAG_CTRL_BRKST)
195 {
196 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
197 {
198 jtag_set_end_state(TAP_IDLE);
199 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
200
201 target->state = TARGET_HALTED;
202
203 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
204 return retval;
205
206 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
207 }
208 else if (target->state == TARGET_DEBUG_RUNNING)
209 {
210 target->state = TARGET_HALTED;
211
212 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
213 return retval;
214
215 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
216 }
217 }
218 else
219 {
220 target->state = TARGET_RUNNING;
221 }
222
223 // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
224
225 return ERROR_OK;
226 }
227
228 int mips_m4k_halt(struct target *target)
229 {
230 struct mips32_common *mips32 = target_to_mips32(target);
231 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
232
233 LOG_DEBUG("target->state: %s",
234 target_state_name(target));
235
236 if (target->state == TARGET_HALTED)
237 {
238 LOG_DEBUG("target was already halted");
239 return ERROR_OK;
240 }
241
242 if (target->state == TARGET_UNKNOWN)
243 {
244 LOG_WARNING("target was in unknown state when halt was requested");
245 }
246
247 if (target->state == TARGET_RESET)
248 {
249 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
250 {
251 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
252 return ERROR_TARGET_FAILURE;
253 }
254 else
255 {
256 /* we came here in a reset_halt or reset_init sequence
257 * debug entry was already prepared in mips32_prepare_reset_halt()
258 */
259 target->debug_reason = DBG_REASON_DBGRQ;
260
261 return ERROR_OK;
262 }
263 }
264
265 /* break processor */
266 mips_ejtag_enter_debug(ejtag_info);
267
268 target->debug_reason = DBG_REASON_DBGRQ;
269
270 return ERROR_OK;
271 }
272
273 int mips_m4k_assert_reset(struct target *target)
274 {
275 struct mips32_common *mips32 = target_to_mips32(target);
276 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
277
278 LOG_DEBUG("target->state: %s",
279 target_state_name(target));
280
281 enum reset_types jtag_reset_config = jtag_get_reset_config();
282 if (!(jtag_reset_config & RESET_HAS_SRST))
283 {
284 LOG_ERROR("Can't assert SRST");
285 return ERROR_FAIL;
286 }
287
288 if (target->reset_halt)
289 {
290 /* use hardware to catch reset */
291 jtag_set_end_state(TAP_IDLE);
292 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
293 }
294 else
295 {
296 jtag_set_end_state(TAP_IDLE);
297 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
298 }
299
300 if (strcmp(target->variant, "ejtag_srst") == 0)
301 {
302 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
303 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
304 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
305 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
306 }
307 else
308 {
309 /* here we should issue a srst only, but we may have to assert trst as well */
310 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
311 {
312 jtag_add_reset(1, 1);
313 }
314 else
315 {
316 jtag_add_reset(0, 1);
317 }
318 }
319
320 target->state = TARGET_RESET;
321 jtag_add_sleep(50000);
322
323 register_cache_invalidate(mips32->core_cache);
324
325 if (target->reset_halt)
326 {
327 int retval;
328 if ((retval = target_halt(target)) != ERROR_OK)
329 return retval;
330 }
331
332 return ERROR_OK;
333 }
334
335 int mips_m4k_deassert_reset(struct target *target)
336 {
337 LOG_DEBUG("target->state: %s",
338 target_state_name(target));
339
340 /* deassert reset lines */
341 jtag_add_reset(0, 0);
342
343 return ERROR_OK;
344 }
345
346 int mips_m4k_soft_reset_halt(struct target *target)
347 {
348 /* TODO */
349 return ERROR_OK;
350 }
351
352 int mips_m4k_single_step_core(struct target *target)
353 {
354 struct mips32_common *mips32 = target_to_mips32(target);
355 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
356
357 /* configure single step mode */
358 mips_ejtag_config_step(ejtag_info, 1);
359
360 /* disable interrupts while stepping */
361 mips32_enable_interrupts(target, 0);
362
363 /* exit debug mode */
364 mips_ejtag_exit_debug(ejtag_info);
365
366 mips_m4k_debug_entry(target);
367
368 return ERROR_OK;
369 }
370
371 int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
372 {
373 struct mips32_common *mips32 = target_to_mips32(target);
374 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
375 struct breakpoint *breakpoint = NULL;
376 uint32_t resume_pc;
377
378 if (target->state != TARGET_HALTED)
379 {
380 LOG_WARNING("target not halted");
381 return ERROR_TARGET_NOT_HALTED;
382 }
383
384 if (!debug_execution)
385 {
386 target_free_all_working_areas(target);
387 mips_m4k_enable_breakpoints(target);
388 mips_m4k_enable_watchpoints(target);
389 }
390
391 /* current = 1: continue on current pc, otherwise continue at <address> */
392 if (!current)
393 {
394 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
395 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
396 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
397 }
398
399 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
400
401 mips32_restore_context(target);
402
403 /* the front-end may request us not to handle breakpoints */
404 if (handle_breakpoints)
405 {
406 /* Single step past breakpoint at current address */
407 if ((breakpoint = breakpoint_find(target, resume_pc)))
408 {
409 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
410 mips_m4k_unset_breakpoint(target, breakpoint);
411 mips_m4k_single_step_core(target);
412 mips_m4k_set_breakpoint(target, breakpoint);
413 }
414 }
415
416 /* enable interrupts if we are running */
417 mips32_enable_interrupts(target, !debug_execution);
418
419 /* exit debug mode */
420 mips_ejtag_exit_debug(ejtag_info);
421 target->debug_reason = DBG_REASON_NOTHALTED;
422
423 /* registers are now invalid */
424 register_cache_invalidate(mips32->core_cache);
425
426 if (!debug_execution)
427 {
428 target->state = TARGET_RUNNING;
429 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
430 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
431 }
432 else
433 {
434 target->state = TARGET_DEBUG_RUNNING;
435 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
436 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
437 }
438
439 return ERROR_OK;
440 }
441
442 int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
443 {
444 /* get pointers to arch-specific information */
445 struct mips32_common *mips32 = target_to_mips32(target);
446 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
447 struct breakpoint *breakpoint = NULL;
448
449 if (target->state != TARGET_HALTED)
450 {
451 LOG_WARNING("target not halted");
452 return ERROR_TARGET_NOT_HALTED;
453 }
454
455 /* current = 1: continue on current pc, otherwise continue at <address> */
456 if (!current)
457 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
458
459 /* the front-end may request us not to handle breakpoints */
460 if (handle_breakpoints)
461 if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
462 mips_m4k_unset_breakpoint(target, breakpoint);
463
464 /* restore context */
465 mips32_restore_context(target);
466
467 /* configure single step mode */
468 mips_ejtag_config_step(ejtag_info, 1);
469
470 target->debug_reason = DBG_REASON_SINGLESTEP;
471
472 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
473
474 /* disable interrupts while stepping */
475 mips32_enable_interrupts(target, 0);
476
477 /* exit debug mode */
478 mips_ejtag_exit_debug(ejtag_info);
479
480 /* registers are now invalid */
481 register_cache_invalidate(mips32->core_cache);
482
483 if (breakpoint)
484 mips_m4k_set_breakpoint(target, breakpoint);
485
486 LOG_DEBUG("target stepped ");
487
488 mips_m4k_debug_entry(target);
489 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
490
491 return ERROR_OK;
492 }
493
494 void mips_m4k_enable_breakpoints(struct target *target)
495 {
496 struct breakpoint *breakpoint = target->breakpoints;
497
498 /* set any pending breakpoints */
499 while (breakpoint)
500 {
501 if (breakpoint->set == 0)
502 mips_m4k_set_breakpoint(target, breakpoint);
503 breakpoint = breakpoint->next;
504 }
505 }
506
507 int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
508 {
509 struct mips32_common *mips32 = target_to_mips32(target);
510 struct mips32_comparator * comparator_list = mips32->inst_break_list;
511 int retval;
512
513 if (breakpoint->set)
514 {
515 LOG_WARNING("breakpoint already set");
516 return ERROR_OK;
517 }
518
519 if (breakpoint->type == BKPT_HARD)
520 {
521 int bp_num = 0;
522
523 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
524 bp_num++;
525 if (bp_num >= mips32->num_inst_bpoints)
526 {
527 LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
528 breakpoint->unique_id );
529 return ERROR_FAIL;
530 }
531 breakpoint->set = bp_num + 1;
532 comparator_list[bp_num].used = 1;
533 comparator_list[bp_num].bp_value = breakpoint->address;
534 target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
535 target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
536 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
537 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
538 breakpoint->unique_id,
539 bp_num, comparator_list[bp_num].bp_value);
540 }
541 else if (breakpoint->type == BKPT_SOFT)
542 {
543 LOG_DEBUG("bpid: %d", breakpoint->unique_id );
544 if (breakpoint->length == 4)
545 {
546 uint32_t verify = 0xffffffff;
547
548 if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
549 {
550 return retval;
551 }
552 if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
553 {
554 return retval;
555 }
556
557 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
558 {
559 return retval;
560 }
561 if (verify != MIPS32_SDBBP)
562 {
563 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
564 return ERROR_OK;
565 }
566 }
567 else
568 {
569 uint16_t verify = 0xffff;
570
571 if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
572 {
573 return retval;
574 }
575 if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
576 {
577 return retval;
578 }
579
580 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
581 {
582 return retval;
583 }
584 if (verify != MIPS16_SDBBP)
585 {
586 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
587 return ERROR_OK;
588 }
589 }
590
591 breakpoint->set = 20; /* Any nice value but 0 */
592 }
593
594 return ERROR_OK;
595 }
596
597 int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
598 {
599 /* get pointers to arch-specific information */
600 struct mips32_common *mips32 = target_to_mips32(target);
601 struct mips32_comparator *comparator_list = mips32->inst_break_list;
602 int retval;
603
604 if (!breakpoint->set)
605 {
606 LOG_WARNING("breakpoint not set");
607 return ERROR_OK;
608 }
609
610 if (breakpoint->type == BKPT_HARD)
611 {
612 int bp_num = breakpoint->set - 1;
613 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
614 {
615 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
616 breakpoint->unique_id);
617 return ERROR_OK;
618 }
619 LOG_DEBUG("bpid: %d - releasing hw: %d",
620 breakpoint->unique_id,
621 bp_num );
622 comparator_list[bp_num].used = 0;
623 comparator_list[bp_num].bp_value = 0;
624 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
625
626 }
627 else
628 {
629 /* restore original instruction (kept in target endianness) */
630 LOG_DEBUG("bpid: %d", breakpoint->unique_id);
631 if (breakpoint->length == 4)
632 {
633 uint32_t current_instr;
634
635 /* check that user program has not modified breakpoint instruction */
636 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
637 {
638 return retval;
639 }
640 if (current_instr == MIPS32_SDBBP)
641 {
642 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
643 {
644 return retval;
645 }
646 }
647 }
648 else
649 {
650 uint16_t current_instr;
651
652 /* check that user program has not modified breakpoint instruction */
653 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
654 {
655 return retval;
656 }
657
658 if (current_instr == MIPS16_SDBBP)
659 {
660 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
661 {
662 return retval;
663 }
664 }
665 }
666 }
667 breakpoint->set = 0;
668
669 return ERROR_OK;
670 }
671
672 int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
673 {
674 struct mips32_common *mips32 = target_to_mips32(target);
675
676 if (breakpoint->type == BKPT_HARD)
677 {
678 if (mips32->num_inst_bpoints_avail < 1)
679 {
680 LOG_INFO("no hardware breakpoint available");
681 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
682 }
683
684 mips32->num_inst_bpoints_avail--;
685 }
686
687 mips_m4k_set_breakpoint(target, breakpoint);
688
689 return ERROR_OK;
690 }
691
692 int mips_m4k_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
693 {
694 /* get pointers to arch-specific information */
695 struct mips32_common *mips32 = target_to_mips32(target);
696
697 if (target->state != TARGET_HALTED)
698 {
699 LOG_WARNING("target not halted");
700 return ERROR_TARGET_NOT_HALTED;
701 }
702
703 if (breakpoint->set)
704 {
705 mips_m4k_unset_breakpoint(target, breakpoint);
706 }
707
708 if (breakpoint->type == BKPT_HARD)
709 mips32->num_inst_bpoints_avail++;
710
711 return ERROR_OK;
712 }
713
714 int mips_m4k_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
715 {
716 struct mips32_common *mips32 = target_to_mips32(target);
717 struct mips32_comparator *comparator_list = mips32->data_break_list;
718 int wp_num = 0;
719 /*
720 * watchpoint enabled, ignore all byte lanes in value register
721 * and exclude both load and store accesses from watchpoint
722 * condition evaluation
723 */
724 int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
725 (0xff << EJTAG_DBCn_BLM_SHIFT);
726
727 if (watchpoint->set)
728 {
729 LOG_WARNING("watchpoint already set");
730 return ERROR_OK;
731 }
732
733 while(comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
734 wp_num++;
735 if (wp_num >= mips32->num_data_bpoints)
736 {
737 LOG_ERROR("Can not find free FP Comparator");
738 return ERROR_FAIL;
739 }
740
741 if (watchpoint->length != 4)
742 {
743 LOG_ERROR("Only watchpoints of length 4 are supported");
744 return ERROR_TARGET_UNALIGNED_ACCESS;
745 }
746
747 if (watchpoint->address % 4)
748 {
749 LOG_ERROR("Watchpoints address should be word aligned");
750 return ERROR_TARGET_UNALIGNED_ACCESS;
751 }
752
753 switch (watchpoint->rw)
754 {
755 case WPT_READ:
756 enable &= ~EJTAG_DBCn_NOLB;
757 break;
758 case WPT_WRITE:
759 enable &= ~EJTAG_DBCn_NOSB;
760 break;
761 case WPT_ACCESS:
762 enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
763 break;
764 default:
765 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
766 }
767
768 watchpoint->set = wp_num + 1;
769 comparator_list[wp_num].used = 1;
770 comparator_list[wp_num].bp_value = watchpoint->address;
771 target_write_u32(target, comparator_list[wp_num].reg_address, comparator_list[wp_num].bp_value);
772 target_write_u32(target, comparator_list[wp_num].reg_address + 0x08, 0x00000000);
773 target_write_u32(target, comparator_list[wp_num].reg_address + 0x10, 0x00000000);
774 target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
775 target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
776 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
777
778 return ERROR_OK;
779 }
780
781 int mips_m4k_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
782 {
783 /* get pointers to arch-specific information */
784 struct mips32_common *mips32 = target_to_mips32(target);
785 struct mips32_comparator *comparator_list = mips32->data_break_list;
786
787 if (!watchpoint->set)
788 {
789 LOG_WARNING("watchpoint not set");
790 return ERROR_OK;
791 }
792
793 int wp_num = watchpoint->set - 1;
794 if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints))
795 {
796 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
797 return ERROR_OK;
798 }
799 comparator_list[wp_num].used = 0;
800 comparator_list[wp_num].bp_value = 0;
801 target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, 0);
802 watchpoint->set = 0;
803
804 return ERROR_OK;
805 }
806
807 int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
808 {
809 struct mips32_common *mips32 = target_to_mips32(target);
810
811 if (mips32->num_data_bpoints_avail < 1)
812 {
813 LOG_INFO("no hardware watchpoints available");
814 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
815 }
816
817 mips32->num_data_bpoints_avail--;
818
819 mips_m4k_set_watchpoint(target, watchpoint);
820 return ERROR_OK;
821 }
822
823 int mips_m4k_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
824 {
825 /* get pointers to arch-specific information */
826 struct mips32_common *mips32 = target_to_mips32(target);
827
828 if (target->state != TARGET_HALTED)
829 {
830 LOG_WARNING("target not halted");
831 return ERROR_TARGET_NOT_HALTED;
832 }
833
834 if (watchpoint->set)
835 {
836 mips_m4k_unset_watchpoint(target, watchpoint);
837 }
838
839 mips32->num_data_bpoints_avail++;
840
841 return ERROR_OK;
842 }
843
844 void mips_m4k_enable_watchpoints(struct target *target)
845 {
846 struct watchpoint *watchpoint = target->watchpoints;
847
848 /* set any pending watchpoints */
849 while (watchpoint)
850 {
851 if (watchpoint->set == 0)
852 mips_m4k_set_watchpoint(target, watchpoint);
853 watchpoint = watchpoint->next;
854 }
855 }
856
857 int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
858 {
859 struct mips32_common *mips32 = target_to_mips32(target);
860 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
861
862 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
863
864 if (target->state != TARGET_HALTED)
865 {
866 LOG_WARNING("target not halted");
867 return ERROR_TARGET_NOT_HALTED;
868 }
869
870 /* sanitize arguments */
871 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
872 return ERROR_INVALID_ARGUMENTS;
873
874 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
875 return ERROR_TARGET_UNALIGNED_ACCESS;
876
877 /* if noDMA off, use DMAACC mode for memory read */
878 int retval;
879 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
880 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
881 else
882 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
883 if (ERROR_OK != retval)
884 return retval;
885
886 return ERROR_OK;
887 }
888
889 int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
890 {
891 struct mips32_common *mips32 = target_to_mips32(target);
892 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
893
894 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
895
896 if (target->state != TARGET_HALTED)
897 {
898 LOG_WARNING("target not halted");
899 return ERROR_TARGET_NOT_HALTED;
900 }
901
902 /* sanitize arguments */
903 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
904 return ERROR_INVALID_ARGUMENTS;
905
906 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
907 return ERROR_TARGET_UNALIGNED_ACCESS;
908
909 /* if noDMA off, use DMAACC mode for memory write */
910 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
911 return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
912 else
913 return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
914 }
915
916 int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target)
917 {
918 mips32_build_reg_cache(target);
919
920 return ERROR_OK;
921 }
922
923 int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
924 {
925 struct mips32_common *mips32 = &mips_m4k->mips32_common;
926
927 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
928
929 /* initialize mips4k specific info */
930 mips32_init_arch_info(target, mips32, tap);
931 mips32->arch_info = mips_m4k;
932
933 return ERROR_OK;
934 }
935
936 int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
937 {
938 struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
939
940 mips_m4k_init_arch_info(target, mips_m4k, target->tap);
941
942 return ERROR_OK;
943 }
944
945 int mips_m4k_examine(struct target *target)
946 {
947 int retval;
948 struct mips32_common *mips32 = target_to_mips32(target);
949 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
950 uint32_t idcode = 0;
951
952 if (!target_was_examined(target))
953 {
954 mips_ejtag_get_idcode(ejtag_info, &idcode);
955 ejtag_info->idcode = idcode;
956
957 if (((idcode >> 1) & 0x7FF) == 0x29)
958 {
959 /* we are using a pic32mx so select ejtag port
960 * as it is not selected by default */
961 mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
962 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
963 }
964 }
965
966 /* init rest of ejtag interface */
967 if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
968 return retval;
969
970 if ((retval = mips32_examine(target)) != ERROR_OK)
971 return retval;
972
973 return ERROR_OK;
974 }
975
976 int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
977 {
978 struct mips32_common *mips32 = target_to_mips32(target);
979 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
980 struct working_area *source;
981 int retval;
982 int write = 1;
983
984 LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
985
986 if (target->state != TARGET_HALTED)
987 {
988 LOG_WARNING("target not halted");
989 return ERROR_TARGET_NOT_HALTED;
990 }
991
992 /* check alignment */
993 if (address & 0x3u)
994 return ERROR_TARGET_UNALIGNED_ACCESS;
995
996 /* Get memory for block write handler */
997 retval = target_alloc_working_area(target, MIPS32_FASTDATA_HANDLER_SIZE, &source);
998 if (retval != ERROR_OK)
999 {
1000 LOG_WARNING("No working area available, falling back to non-bulk write");
1001 return mips_m4k_write_memory(target, address, 4, count, buffer);
1002 }
1003
1004 /* TAP data register is loaded LSB first (little endian) */
1005 if (target->endianness == TARGET_BIG_ENDIAN)
1006 {
1007 uint32_t i, t32;
1008 for(i = 0; i < (count * 4); i += 4)
1009 {
1010 t32 = be_to_h_u32((uint8_t *) &buffer[i]);
1011 h_u32_to_le(&buffer[i], t32);
1012 }
1013 }
1014
1015 retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write, address, count, (uint32_t*) buffer);
1016 if (retval != ERROR_OK)
1017 {
1018 /* FASTDATA access failed, try normal memory write */
1019 LOG_DEBUG("Fastdata access Failed, falling back to non-bulk write");
1020 retval = mips_m4k_write_memory(target, address, 4, count, buffer);
1021 }
1022
1023 if (source)
1024 target_free_working_area(target, source);
1025
1026 return retval;
1027 }
1028
1029 int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum)
1030 {
1031 return ERROR_FAIL; /* use bulk read method */
1032 }
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