src/target/mips_ejtag.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2008 by Spencer Oliver                                  *
   5  *   spen@spen-soft.co.uk                                                  *
   6  *                                                                         *
   7  *   Copyright (C) 2008 by David T.L. Wong                                 *
   8  ***************************************************************************/
   9
  10 #ifndef OPENOCD_TARGET_MIPS_EJTAG_H
  11 #define OPENOCD_TARGET_MIPS_EJTAG_H
  12
  13 #include <jtag/jtag.h>
  14
  15 /* tap instructions */
  16 #define EJTAG_INST_IDCODE               0x01
  17 #define EJTAG_INST_IMPCODE              0x03
  18 #define EJTAG_INST_ADDRESS              0x08
  19 #define EJTAG_INST_DATA                 0x09
  20 #define EJTAG_INST_CONTROL              0x0A
  21 #define EJTAG_INST_ALL                  0x0B
  22 #define EJTAG_INST_EJTAGBOOT    0x0C
  23 #define EJTAG_INST_NORMALBOOT   0x0D
  24 #define EJTAG_INST_FASTDATA             0x0E
  25 #define EJTAG_INST_TCBCONTROLA  0x10
  26 #define EJTAG_INST_TCBCONTROLB  0x11
  27 #define EJTAG_INST_TCBDATA              0x12
  28 #define EJTAG_INST_TCBCONTROLC  0x13
  29 #define EJTAG_INST_PCSAMPLE             0x14
  30 #define EJTAG_INST_TCBCONTROLD  0x15
  31 #define EJTAG_INST_TCBCONTROLE  0x16
  32 #define EJTAG_INST_FDC                  0x17
  33 #define EJTAG_INST_BYPASS               0xFF
  34
  35 /* microchip PIC32MX specific instructions */
  36 #define MTAP_SW_MTAP                    0x04
  37 #define MTAP_SW_ETAP                    0x05
  38 #define MTAP_COMMAND                    0x07
  39
  40 /* microchip specific cmds */
  41 #define MCHP_ASERT_RST                  0xd1
  42 #define MCHP_DE_ASSERT_RST              0xd0
  43 #define MCHP_ERASE                              0xfc
  44 #define MCHP_STATUS                             0x00
  45
  46 /* ejtag control register bits ECR */
  47 #define EJTAG_CTRL_TOF                  (1 << 1)
  48 #define EJTAG_CTRL_TIF                  (1 << 2)
  49 #define EJTAG_CTRL_BRKST                (1 << 3)
  50 #define EJTAG_CTRL_DLOCK                (1 << 5)
  51 #define EJTAG_CTRL_DRWN                 (1 << 9)
  52 #define EJTAG_CTRL_DERR                 (1 << 10)
  53 #define EJTAG_CTRL_DSTRT                (1 << 11)
  54 #define EJTAG_CTRL_JTAGBRK              (1 << 12)
  55 #define EJTAG_CTRL_DBGISA               (1 << 13)
  56 #define EJTAG_CTRL_SETDEV               (1 << 14)
  57 #define EJTAG_CTRL_PROBEN               (1 << 15)
  58 #define EJTAG_CTRL_PRRST                (1 << 16)
  59 #define EJTAG_CTRL_DMAACC               (1 << 17)
  60 #define EJTAG_CTRL_PRACC                (1 << 18)
  61 #define EJTAG_CTRL_PRNW                 (1 << 19)
  62 #define EJTAG_CTRL_PERRST               (1 << 20)
  63 #define EJTAG_CTRL_SYNC                 (1 << 23)
  64 #define EJTAG_CTRL_DNM                  (1 << 28)
  65 #define EJTAG_CTRL_ROCC                 (1 << 31)
  66
  67 /* Debug Register (CP0 Register 23, Select 0) */
  68
  69 #define EJTAG_DEBUG_DSS                 (1 << 0)
  70 #define EJTAG_DEBUG_DBP                 (1 << 1)
  71 #define EJTAG_DEBUG_DDBL                (1 << 2)
  72 #define EJTAG_DEBUG_DDBS                (1 << 3)
  73 #define EJTAG_DEBUG_DIB                 (1 << 4)
  74 #define EJTAG_DEBUG_DINT                (1 << 5)
  75 #define EJTAG_DEBUG_OFFLINE             (1 << 7)
  76 #define EJTAG_DEBUG_SST                 (1 << 8)
  77 #define EJTAG_DEBUG_NOSST               (1 << 9)
  78 #define EJTAG_DEBUG_DDBLIMPR    (1 << 18)
  79 #define EJTAG_DEBUG_DDBSIMPR    (1 << 19)
  80 #define EJTAG_DEBUG_IEXI                (1 << 20)
  81 #define EJTAG_DEBUG_DBUSEP              (1 << 21)
  82 #define EJTAG_DEBUG_CACHEEP             (1 << 22)
  83 #define EJTAG_DEBUG_MCHECKP             (1 << 23)
  84 #define EJTAG_DEBUG_IBUSEP              (1 << 24)
  85 #define EJTAG_DEBUG_COUNTDM             (1 << 25)
  86 #define EJTAG_DEBUG_HALT                (1 << 26)
  87 #define EJTAG_DEBUG_DOZE                (1 << 27)
  88 #define EJTAG_DEBUG_LSNM                (1 << 28)
  89 #define EJTAG_DEBUG_NODCR               (1 << 29)
  90 #define EJTAG_DEBUG_DM                  (1 << 30)
  91 #define EJTAG_DEBUG_DBD                 (1 << 31)
  92
  93 /* implementation MIPS register bits.
  94  * Bits marked with V20 or v2.0 mean that, this registers supported only
  95  * by EJTAG v2.0. Bits marked with Lexra or BMIPS are different from the
  96  * official EJATG.
  97  * NOTE: Lexra or BMIPS use EJTAG v2.0 */
  98
  99 #define EJTAG_IMP_HAS(x)                        (ejtag_info->impcode & (x))
 100 /* v2.0(Lexra) 29 - 1’b1 - Lexra Internal Trace Buffer implemented. This bit
 101  * overlaps with version bit of MIPS EJTAG specification. */
 102 #define EJTAG_V26_IMP_R3K               (1 << 28)
 103 /* v2.0 - 24:25 - 2’b00- No profiling support */
 104 #define EJTAG_V26_IMP_DINT              (1 << 24)
 105 #define EJTAG_V20_IMP_SDBBP             (1 << 23) /* 1’b1 - sdbbp is Special2 Opcode */
 106 #define EJTAG_IMP_ASID8                 (1 << 22)
 107 #define EJTAG_IMP_ASID6                 (1 << 21)
 108 #define EJTAG_V20_IMP_COMPLEX_BREAK     (1 << 20) /* Complex Breaks supported*/
 109 #define EJTAG_V20_IMP_EADDR_NO32BIT     (1 << 19) /* EJTAG_ADDR > 32 bits wide */
 110 #define EJTAG_V20_IMP_DCACHE_COH        (1 << 18) /* DCache does keep DMA coherent */
 111 #define EJTAG_V20_IMP_ICACHE_COH        (1 << 17) /* DCache does keep DMA coherent */
 112 #define EJTAG_IMP_MIPS16                (1 << 16)
 113 #define EJTAG_IMP_NODMA                 (1 << 14)
 114 /* v2.0 - 11:13 external PC trace. Trace PC Width. */
 115 /* v2.0 - 8:10 external PC trace. PCST Width and DCLK Division Factor */
 116 #define EJTAG_V20_IMP_NOPB              (1 << 7) /* no processor breaks */
 117 #define EJTAG_V20_IMP_NODB              (1 << 6) /* no data breaks */
 118 #define EJTAG_V20_IMP_NOIB              (1 << 5) /* no instruction breaks implemented */
 119 /* v2.0 - 1:4 Number of Break Channels. */
 120 #define EJTAG_V20_IMP_BCHANNELS_MASK    0xf
 121 #define EJTAG_V20_IMP_BCHANNELS_SHIFT   1
 122 #define EJTAG_IMP_MIPS64                (1 << 0)
 123
 124 /* Debug Control Register DCR */
 125 #define EJTAG_DCR                               0xFF300000
 126 #define EJTAG_DCR_ENM                   BIT(29)
 127 #define EJTAG_DCR_FDC                   BIT(18)
 128 #define EJTAG_DCR_DB                    BIT(17)
 129 #define EJTAG_DCR_IB                    BIT(16)
 130 #define EJTAG_DCR_INTE                  BIT(4)
 131 #define EJTAG_DCR_MP                    BIT(2)
 132
 133 /* breakpoint support */
 134 /* EJTAG_V20_* was tested on Broadcom BCM7401
 135  * and may or will differ with other hardware. For example EZ4021-FC. */
 136 #define EJTAG_V20_IBS                   0xFF300004
 137 #define EJTAG_V20_IBA0                  0xFF300100
 138 #define EJTAG_V20_IBC_OFFS              0x4     /* IBC Offset */
 139 #define EJTAG_V20_IBM_OFFS              0x8
 140 #define EJTAG_V20_IBAN_STEP             0x10    /* Offset for next channel */
 141 #define EJTAG_V20_DBS                   0xFF300008
 142 #define EJTAG_V20_DBA0                  0xFF300200
 143 #define EJTAG_V20_DBC_OFFS              0x4
 144 #define EJTAG_V20_DBM_OFFS              0x8
 145 #define EJTAG_V20_DBV_OFFS              0xc
 146 #define EJTAG_V20_DBAN_STEP             0x10
 147
 148 #define EJTAG_V25_IBS                   0xFF301000
 149 #define EJTAG_V25_IBA0                  0xFF301100
 150 #define EJTAG_V25_IBM_OFFS              0x8
 151 #define EJTAG_V25_IBASID_OFFS           0x10
 152 #define EJTAG_V25_IBC_OFFS              0x18
 153 #define EJTAG_V25_IBAN_STEP             0x100
 154 #define EJTAG_V25_DBS                   0xFF302000
 155 #define EJTAG_V25_DBA0                  0xFF302100
 156 #define EJTAG_V25_DBM_OFFS              0x8
 157 #define EJTAG_V25_DBASID_OFFS           0x10
 158 #define EJTAG_V25_DBC_OFFS              0x18
 159 #define EJTAG_V25_DBV_OFFS              0x20
 160 #define EJTAG_V25_DBAN_STEP             0x100
 161
 162 #define EJTAG_DBCN_NOSB                 (1 << 13)
 163 #define EJTAG_DBCN_NOLB                 (1 << 12)
 164 #define EJTAG_DBCN_BLM_MASK             0xff
 165 #define EJTAG_DBCN_BLM_SHIFT    4
 166 #define EJTAG_DBCN_BE                   (1 << 0)
 167
 168 #define EJTAG_VERSION_20                0
 169 #define EJTAG_VERSION_25                1
 170 #define EJTAG_VERSION_26                2
 171 #define EJTAG_VERSION_31                3
 172 #define EJTAG_VERSION_41                4
 173 #define EJTAG_VERSION_51                5
 174
 175 /*
 176  * Additional defines for MIPS64 EJTAG
 177  */
 178 #define EJTAG64_DCR                     0xFFFFFFFFFF300000ull
 179 #define EJTAG64_DCR_ENM                 (1llu << 29)
 180 #define EJTAG64_DCR_DB                  (1llu << 17)
 181 #define EJTAG64_DCR_IB                  (1llu << 16)
 182 #define EJTAG64_DCR_INTE                (1llu << 4)
 183 #define EJTAG64_DCR_MP                  (1llu << 2)
 184 #define EJTAG64_V25_DBA0                0xFFFFFFFFFF302100ull
 185 #define EJTAG64_V25_DBS                 0xFFFFFFFFFF302000ull
 186 #define EJTAG64_V25_IBA0                0xFFFFFFFFFF301100ull
 187 #define EJTAG64_V25_IBS                 0xFFFFFFFFFF301000ull
 188
 189 static const struct dcr_feature {
 190         int bit;
 191         const char *name;
 192 } dcr_features[] = {
 193         {22, "DAS"},
 194         {18, "FDC"},
 195         {17, "DataBrk"},
 196         {16, "InstBrk"},
 197         {15, "Inverted Data value"},
 198         {14, "Data value stored"},
 199         {10, "Complex Breakpoints"},
 200         { 9, "PC Sampling"},
 201 };
 202
 203 #define EJTAG_DCR_ENTRIES (ARRAY_SIZE(dcr_features))
 204
 205 struct mips_ejtag {
 206         struct jtag_tap *tap;
 207         uint32_t impcode;
 208         uint32_t idcode;
 209         uint32_t prid;
 210         uint32_t ejtag_ctrl;
 211         int fast_access_save;
 212         uint32_t config_regs;   /* number of config registers read */
 213         uint32_t config[4];     /* cp0 config to config3 */
 214
 215         uint32_t reg8;
 216         uint32_t reg9;
 217         unsigned scan_delay;
 218         int mode;
 219         uint32_t pa_ctrl;
 220         uint32_t pa_addr;
 221         unsigned int ejtag_version;
 222         uint32_t isa;
 223         uint32_t endianness;
 224
 225         /* Memory-Mapped Registers. This addresses are not same on different
 226          * EJTAG versions. */
 227         uint32_t debug_caps;
 228         uint32_t ejtag_ibs_addr;        /* Instruction Address Break Status */
 229         uint32_t ejtag_iba0_addr;       /* IAB channel 0 */
 230         uint32_t ejtag_ibc_offs;        /* IAB Control offset */
 231         uint32_t ejtag_ibm_offs;        /* IAB Mask offset */
 232         uint32_t ejtag_ibasid_offs;     /* IAB ASID (4Kc) */
 233
 234         uint32_t ejtag_dbs_addr;        /* Data Address Break Status Register */
 235         uint32_t ejtag_dba0_addr;       /* DAB channel 0 */
 236         uint32_t ejtag_dbc_offs;        /* DAB Control offset */
 237         uint32_t ejtag_dbm_offs;        /* DAB Mask offset */
 238         uint32_t ejtag_dbv_offs;        /* DAB Value offset */
 239         uint32_t ejtag_dbasid_offs;     /* DAB ASID (4Kc) */
 240
 241         uint32_t ejtag_iba_step_size;
 242         uint32_t ejtag_dba_step_size;   /* size of step till next *DBAn register. */
 243 };
 244
 245 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr);
 246 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
 247 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
 248 int mips64_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
 249 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info);
 250 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info,
 251                             uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf);
 252 int mips_ejtag_drscan_64(struct mips_ejtag *ejtag_info, uint64_t *data);
 253 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
 254 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
 255 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
 256 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data);
 257 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
 258 int mips64_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, bool write_t, uint64_t *data);
 259
 260 int mips_ejtag_init(struct mips_ejtag *ejtag_info);
 261 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);
 262 int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step);
 263
 264 void ejtag_main_print_imp(struct mips_ejtag *ejtag_info);
 265 int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info);
 266
 267 static inline void mips_le_to_h_u32(jtag_callback_data_t arg)
 268 {
 269         uint8_t *in = (uint8_t *)arg;
 270         *((uint32_t *)arg) = le_to_h_u32(in);
 271 }
 272
 273 static inline void mips_le_to_h_u64(jtag_callback_data_t arg)
 274 {
 275         uint8_t *in = (uint8_t *)arg;
 276         *((uint64_t *)arg) = le_to_h_u64(in);
 277 }
 278
 279 #endif /* OPENOCD_TARGET_MIPS_EJTAG_H */