- add support for hardware breakpoints to mips32 target
[openocd.git] / src / target / mips_ejtag.h
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 #ifndef MIPS_EJTAG
24 #define MIPS_EJTAG
25
26 #include "types.h"
27 #include "jtag.h"
28
29 /* tap instructions */
30 #define EJTAG_INST_IDCODE 0x01
31 #define EJTAG_INST_IMPCODE 0x03
32 #define EJTAG_INST_ADDRESS 0x08
33 #define EJTAG_INST_DATA 0x09
34 #define EJTAG_INST_CONTROL 0x0A
35 #define EJTAG_INST_ALL 0x0B
36 #define EJTAG_INST_EJTAGBOOT 0x0C
37 #define EJTAG_INST_NORMALBOOT 0x0D
38 #define EJTAG_INST_FASTDATA 0x0E
39 #define EJTAG_INST_TCBCONTROLA 0x10
40 #define EJTAG_INST_TCBCONTROLB 0x11
41 #define EJTAG_INST_TCBDATA 0x12
42 #define EJTAG_INST_BYPASS 0xFF
43
44 /* debug control register bits ECR */
45 #define EJTAG_CTRL_TOF (1 << 1)
46 #define EJTAG_CTRL_TIF (1 << 2)
47 #define EJTAG_CTRL_BRKST (1 << 3)
48 #define EJTAG_CTRL_DLOCK (1 << 5)
49 #define EJTAG_CTRL_DRWN (1 << 9)
50 #define EJTAG_CTRL_DERR (1 << 10)
51 #define EJTAG_CTRL_DSTRT (1 << 11)
52 #define EJTAG_CTRL_JTAGBRK (1 << 12)
53 #define EJTAG_CTRL_SETDEV (1 << 14)
54 #define EJTAG_CTRL_PROBEN (1 << 15)
55 #define EJTAG_CTRL_PRRST (1 << 16)
56 #define EJTAG_CTRL_DMAACC (1 << 17)
57 #define EJTAG_CTRL_PRACC (1 << 18)
58 #define EJTAG_CTRL_PRNW (1 << 19)
59 #define EJTAG_CTRL_PERRST (1 << 20)
60 #define EJTAG_CTRL_SYNC (1 << 23)
61 #define EJTAG_CTRL_DNM (1 << 28)
62 #define EJTAG_CTRL_ROCC (1 << 31)
63
64 /* Debug Register (CP0 Register 23, Select 0) */
65
66 #define EJTAG_DEBUG_DSS (1 << 0)
67 #define EJTAG_DEBUG_DBP (1 << 1)
68 #define EJTAG_DEBUG_DDBL (1 << 2)
69 #define EJTAG_DEBUG_DDBS (1 << 3)
70 #define EJTAG_DEBUG_DIB (1 << 4)
71 #define EJTAG_DEBUG_DINT (1 << 5)
72 #define EJTAG_DEBUG_OFFLINE (1 << 7)
73 #define EJTAG_DEBUG_SST (1 << 8)
74 #define EJTAG_DEBUG_NOSST (1 << 9)
75 #define EJTAG_DEBUG_DDBLIMPR (1 << 18)
76 #define EJTAG_DEBUG_DDBSIMPR (1 << 19)
77 #define EJTAG_DEBUG_IEXI (1 << 20)
78 #define EJTAG_DEBUG_DBUSEP (1 << 21)
79 #define EJTAG_DEBUG_CACHEEP (1 << 22)
80 #define EJTAG_DEBUG_MCHECKP (1 << 23)
81 #define EJTAG_DEBUG_IBUSEP (1 << 24)
82 #define EJTAG_DEBUG_COUNTDM (1 << 25)
83 #define EJTAG_DEBUG_HALT (1 << 26)
84 #define EJTAG_DEBUG_DOZE (1 << 27)
85 #define EJTAG_DEBUG_LSNM (1 << 28)
86 #define EJTAG_DEBUG_NODCR (1 << 29)
87 #define EJTAG_DEBUG_DM (1 << 30)
88 #define EJTAG_DEBUG_DBD (1 << 31)
89
90 /* implementaion register bits */
91 #define EJTAG_IMP_NODMA (1 << 14)
92 #define EJTAG_IMP_MIPS16 (1 << 16)
93
94 /* breakpoint support */
95 #define EJTAG_DCR 0xFF300000
96 #define EJTAG_IBS 0xFF301000
97 #define EJTAG_IBA1 0xFF301100
98 #define EJTAG_DBS 0xFF302000
99 #define EJTAG_DBA1 0xFF302100
100
101 typedef struct mips_ejtag_s
102 {
103 int chain_pos;
104 u32 impcode;
105 /*int use_dma;*/
106 u32 ejtag_ctrl;
107 } mips_ejtag_t;
108
109 extern int mips_ejtag_set_instr(mips_ejtag_t *ejtag_info, int new_instr, in_handler_t handler);
110 extern int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info);
111 extern int mips_ejtag_exit_debug(mips_ejtag_t *ejtag_info, int enable_interrupts);
112 extern int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode, in_handler_t handler);
113 extern int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode, in_handler_t handler);
114 extern int mips_ejtag_drscan_32(mips_ejtag_t *ejtag_info, u32 *data);
115
116 extern int mips_ejtag_init(mips_ejtag_t *ejtag_info);
117 extern int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step);
118 extern int mips_ejtag_read_debug(mips_ejtag_t *ejtag_info, u32* debug_reg);
119
120 #endif /* MIPS_EJTAG */

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