mips: m4k alternate pracc code. Patch 1
[openocd.git] / src / target / mips_ejtag.h
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 #ifndef MIPS_EJTAG
24 #define MIPS_EJTAG
25
26 #include <jtag/jtag.h>
27
28 /* tap instructions */
29 #define EJTAG_INST_IDCODE 0x01
30 #define EJTAG_INST_IMPCODE 0x03
31 #define EJTAG_INST_ADDRESS 0x08
32 #define EJTAG_INST_DATA 0x09
33 #define EJTAG_INST_CONTROL 0x0A
34 #define EJTAG_INST_ALL 0x0B
35 #define EJTAG_INST_EJTAGBOOT 0x0C
36 #define EJTAG_INST_NORMALBOOT 0x0D
37 #define EJTAG_INST_FASTDATA 0x0E
38 #define EJTAG_INST_TCBCONTROLA 0x10
39 #define EJTAG_INST_TCBCONTROLB 0x11
40 #define EJTAG_INST_TCBDATA 0x12
41 #define EJTAG_INST_BYPASS 0xFF
42
43 /* microchip PIC32MX specific instructions */
44 #define MTAP_SW_MTAP 0x04
45 #define MTAP_SW_ETAP 0x05
46 #define MTAP_COMMAND 0x07
47
48 /* microchip specific cmds */
49 #define MCHP_ASERT_RST 0xd1
50 #define MCHP_DE_ASSERT_RST 0xd0
51 #define MCHP_ERASE 0xfc
52 #define MCHP_STATUS 0x00
53
54 /* ejtag control register bits ECR */
55 #define EJTAG_CTRL_TOF (1 << 1)
56 #define EJTAG_CTRL_TIF (1 << 2)
57 #define EJTAG_CTRL_BRKST (1 << 3)
58 #define EJTAG_CTRL_DLOCK (1 << 5)
59 #define EJTAG_CTRL_DRWN (1 << 9)
60 #define EJTAG_CTRL_DERR (1 << 10)
61 #define EJTAG_CTRL_DSTRT (1 << 11)
62 #define EJTAG_CTRL_JTAGBRK (1 << 12)
63 #define EJTAG_CTRL_SETDEV (1 << 14)
64 #define EJTAG_CTRL_PROBEN (1 << 15)
65 #define EJTAG_CTRL_PRRST (1 << 16)
66 #define EJTAG_CTRL_DMAACC (1 << 17)
67 #define EJTAG_CTRL_PRACC (1 << 18)
68 #define EJTAG_CTRL_PRNW (1 << 19)
69 #define EJTAG_CTRL_PERRST (1 << 20)
70 #define EJTAG_CTRL_SYNC (1 << 23)
71 #define EJTAG_CTRL_DNM (1 << 28)
72 #define EJTAG_CTRL_ROCC (1 << 31)
73
74 /* Debug Register (CP0 Register 23, Select 0) */
75
76 #define EJTAG_DEBUG_DSS (1 << 0)
77 #define EJTAG_DEBUG_DBP (1 << 1)
78 #define EJTAG_DEBUG_DDBL (1 << 2)
79 #define EJTAG_DEBUG_DDBS (1 << 3)
80 #define EJTAG_DEBUG_DIB (1 << 4)
81 #define EJTAG_DEBUG_DINT (1 << 5)
82 #define EJTAG_DEBUG_OFFLINE (1 << 7)
83 #define EJTAG_DEBUG_SST (1 << 8)
84 #define EJTAG_DEBUG_NOSST (1 << 9)
85 #define EJTAG_DEBUG_DDBLIMPR (1 << 18)
86 #define EJTAG_DEBUG_DDBSIMPR (1 << 19)
87 #define EJTAG_DEBUG_IEXI (1 << 20)
88 #define EJTAG_DEBUG_DBUSEP (1 << 21)
89 #define EJTAG_DEBUG_CACHEEP (1 << 22)
90 #define EJTAG_DEBUG_MCHECKP (1 << 23)
91 #define EJTAG_DEBUG_IBUSEP (1 << 24)
92 #define EJTAG_DEBUG_COUNTDM (1 << 25)
93 #define EJTAG_DEBUG_HALT (1 << 26)
94 #define EJTAG_DEBUG_DOZE (1 << 27)
95 #define EJTAG_DEBUG_LSNM (1 << 28)
96 #define EJTAG_DEBUG_NODCR (1 << 29)
97 #define EJTAG_DEBUG_DM (1 << 30)
98 #define EJTAG_DEBUG_DBD (1 << 31)
99
100 /* implementaion register bits */
101 #define EJTAG_IMP_R3K (1 << 28)
102 #define EJTAG_IMP_DINT (1 << 24)
103 #define EJTAG_IMP_NODMA (1 << 14)
104 #define EJTAG_IMP_MIPS16 (1 << 16)
105 #define EJTAG_DCR_MIPS64 (1 << 0)
106
107 /* Debug Control Register DCR */
108 #define EJTAG_DCR 0xFF300000
109 #define EJTAG_DCR_ENM (1 << 29)
110 #define EJTAG_DCR_DB (1 << 17)
111 #define EJTAG_DCR_IB (1 << 16)
112 #define EJTAG_DCR_INTE (1 << 4)
113
114 /* breakpoint support */
115 #define EJTAG_IBS 0xFF301000
116 #define EJTAG_IBA1 0xFF301100
117 #define EJTAG_DBS 0xFF302000
118 #define EJTAG_DBA1 0xFF302100
119 #define EJTAG_DBCn_NOSB (1 << 13)
120 #define EJTAG_DBCn_NOLB (1 << 12)
121 #define EJTAG_DBCn_BLM_MASK 0xff
122 #define EJTAG_DBCn_BLM_SHIFT 4
123 #define EJTAG_DBCn_BE (1 << 0)
124
125 struct mips_ejtag {
126 struct jtag_tap *tap;
127 uint32_t impcode;
128 uint32_t idcode;
129 uint32_t ejtag_ctrl;
130 int fast_access_save;
131 uint32_t reg8;
132 uint32_t reg9;
133 unsigned scan_delay;
134 int mode;
135 };
136
137 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
138 int new_instr);
139 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
140 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
141 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode);
142 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info,
143 uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf);
144 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
145 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
146 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
147 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data);
148 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
149
150 int mips_ejtag_init(struct mips_ejtag *ejtag_info);
151 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);
152
153 static inline void mips_le_to_h_u32(jtag_callback_data_t arg)
154 {
155 uint8_t *in = (uint8_t *)arg;
156 *((uint32_t *)arg) = le_to_h_u32(in);
157 }
158
159 #endif /* MIPS_EJTAG */