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mips32, add generic scan 32 function
[openocd.git] / src / target / mips_ejtag.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
21 ***************************************************************************/
22
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "mips32.h"
28 #include "mips_ejtag.h"
29 #include "mips32_dmaacc.h"
30
31 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
32 {
33 struct jtag_tap *tap;
34
35 tap = ejtag_info->tap;
36 assert(tap != NULL);
37
38 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) {
39 struct scan_field field;
40 uint8_t t[4];
41
42 field.num_bits = tap->ir_length;
43 field.out_value = t;
44 buf_set_u32(t, 0, field.num_bits, new_instr);
45 field.in_value = NULL;
46
47 jtag_add_ir_scan(tap, &field, TAP_IDLE);
48 }
49 }
50
51 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
52 {
53 struct scan_field field;
54 uint8_t r[4];
55
56 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
57
58 field.num_bits = 32;
59 field.out_value = NULL;
60 field.in_value = r;
61
62 jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
63
64 int retval;
65 retval = jtag_execute_queue();
66 if (retval != ERROR_OK) {
67 LOG_ERROR("register read failed");
68 return retval;
69 }
70
71 *idcode = buf_get_u32(field.in_value, 0, 32);
72
73 return ERROR_OK;
74 }
75
76 static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
77 {
78 struct scan_field field;
79 uint8_t r[4];
80
81 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
82
83 field.num_bits = 32;
84 field.out_value = NULL;
85 field.in_value = r;
86
87 jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
88
89 int retval;
90 retval = jtag_execute_queue();
91 if (retval != ERROR_OK) {
92 LOG_ERROR("register read failed");
93 return retval;
94 }
95
96 *impcode = buf_get_u32(field.in_value, 0, 32);
97
98 return ERROR_OK;
99 }
100
101 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
102 {
103 assert(ejtag_info->tap != NULL);
104 struct jtag_tap *tap = ejtag_info->tap;
105
106 struct scan_field field;
107 uint8_t out_scan[12];
108
109 /* processor access "all" register 96 bit */
110 field.num_bits = 96;
111
112 field.out_value = out_scan;
113 buf_set_u32(out_scan, 0, 32, ctrl);
114 buf_set_u32(out_scan + 4, 0, 32, data);
115 buf_set_u32(out_scan + 8, 0, 32, 0);
116
117 field.in_value = in_scan_buf;
118
119 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
120
121 keep_alive();
122 }
123
124 void mips_ejtag_drscan_32_queued(struct mips_ejtag *ejtag_info, uint32_t data_out, uint8_t *data_in)
125 {
126 assert(ejtag_info->tap != NULL);
127 struct jtag_tap *tap = ejtag_info->tap;
128
129 struct scan_field field;
130 field.num_bits = 32;
131
132 uint8_t scan_out[4];
133 field.out_value = scan_out;
134 buf_set_u32(scan_out, 0, field.num_bits, data_out);
135
136 field.in_value = data_in;
137 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
138
139 keep_alive();
140 }
141
142 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
143 {
144 uint8_t scan_in[4];
145 mips_ejtag_drscan_32_queued(ejtag_info, *data, scan_in);
146
147 int retval = jtag_execute_queue();
148 if (retval != ERROR_OK) {
149 LOG_ERROR("register read failed");
150 return retval;
151 }
152
153 *data = buf_get_u32(scan_in, 0, 32);
154 return ERROR_OK;
155 }
156
157 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
158 {
159 mips_ejtag_drscan_32_queued(ejtag_info, data, NULL);
160 }
161
162 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data)
163 {
164 assert(ejtag_info->tap != NULL);
165 struct jtag_tap *tap = ejtag_info->tap;
166
167 struct scan_field field;
168 field.num_bits = 8;
169
170 field.out_value = data;
171 field.in_value = data;
172
173 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
174
175 int retval = jtag_execute_queue();
176 if (retval != ERROR_OK) {
177 LOG_ERROR("register read failed");
178 return retval;
179 }
180 return ERROR_OK;
181 }
182
183 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
184 {
185 struct jtag_tap *tap;
186 tap = ejtag_info->tap;
187 assert(tap != NULL);
188
189 struct scan_field field;
190
191 field.num_bits = 8;
192 field.out_value = &data;
193 field.in_value = NULL;
194
195 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
196 }
197
198 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
199 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
200 {
201 struct pracc_queue_info ctx = {.max_code = 7};
202 pracc_queue_init(&ctx);
203 if (ctx.retval != ERROR_OK)
204 goto exit;
205
206 pracc_add(&ctx, 0, MIPS32_MFC0(8, 23, 0)); /* move COP0 Debug to $8 */
207 pracc_add(&ctx, 0, MIPS32_ORI(8, 8, 0x0100)); /* set SSt bit in debug reg */
208 if (!enable_step)
209 pracc_add(&ctx, 0, MIPS32_XORI(8, 8, 0x0100)); /* clear SSt bit in debug reg */
210
211 pracc_add(&ctx, 0, MIPS32_MTC0(8, 23, 0)); /* move $8 to COP0 Debug */
212 pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
213 pracc_add(&ctx, 0, MIPS32_B(NEG16((ctx.code_count + 1)))); /* jump to start */
214 pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
215
216 ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
217 exit:
218 pracc_queue_free(&ctx);
219 return ctx.retval;
220 }
221
222 /*
223 * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
224 * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
225 * For example bcm7401 and others. At leas on some
226 * CPUs, DebugMode wont start if this bit is not removed.
227 */
228 static int disable_dcr_mp(struct mips_ejtag *ejtag_info)
229 {
230 uint32_t dcr;
231 int retval;
232
233 retval = mips32_dmaacc_read_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
234 if (retval != ERROR_OK)
235 goto error;
236
237 dcr &= ~EJTAG_DCR_MP;
238 retval = mips32_dmaacc_write_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
239 if (retval != ERROR_OK)
240 goto error;
241 return ERROR_OK;
242 error:
243 LOG_ERROR("Failed to remove DCR MPbit!");
244 return retval;
245 }
246
247 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
248 {
249 uint32_t ejtag_ctrl;
250 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
251
252 if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
253 if (disable_dcr_mp(ejtag_info) != ERROR_OK)
254 goto error;
255 }
256
257 /* set debug break bit */
258 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
259 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
260
261 /* break bit will be cleared by hardware */
262 ejtag_ctrl = ejtag_info->ejtag_ctrl;
263 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
264 LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
265 if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
266 goto error;
267
268 return ERROR_OK;
269 error:
270 LOG_ERROR("Failed to enter Debug Mode!");
271 return ERROR_FAIL;
272 }
273
274 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
275 {
276 uint32_t pracc_list[] = {MIPS32_DRET, 0};
277 struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = pracc_list, .code_count = 1, .store_count = 0};
278
279 /* execute our dret instruction */
280 ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
281
282 /* pic32mx workaround, false pending at low core clock */
283 jtag_add_sleep(1000);
284 return ctx.retval;
285 }
286
287 /* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending
288 * on EJTAG version.
289 */
290 static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
291 {
292 if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
293 ejtag_info->ejtag_ibs_addr = EJTAG_V20_IBS;
294 ejtag_info->ejtag_iba0_addr = EJTAG_V20_IBA0;
295 ejtag_info->ejtag_ibc_offs = EJTAG_V20_IBC_OFFS;
296 ejtag_info->ejtag_ibm_offs = EJTAG_V20_IBM_OFFS;
297
298 ejtag_info->ejtag_dbs_addr = EJTAG_V20_DBS;
299 ejtag_info->ejtag_dba0_addr = EJTAG_V20_DBA0;
300 ejtag_info->ejtag_dbc_offs = EJTAG_V20_DBC_OFFS;
301 ejtag_info->ejtag_dbm_offs = EJTAG_V20_DBM_OFFS;
302 ejtag_info->ejtag_dbv_offs = EJTAG_V20_DBV_OFFS;
303
304 ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAn_STEP;
305 ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAn_STEP;
306 } else {
307 ejtag_info->ejtag_ibs_addr = EJTAG_V25_IBS;
308 ejtag_info->ejtag_iba0_addr = EJTAG_V25_IBA0;
309 ejtag_info->ejtag_ibm_offs = EJTAG_V25_IBM_OFFS;
310 ejtag_info->ejtag_ibasid_offs = EJTAG_V25_IBASID_OFFS;
311 ejtag_info->ejtag_ibc_offs = EJTAG_V25_IBC_OFFS;
312
313 ejtag_info->ejtag_dbs_addr = EJTAG_V25_DBS;
314 ejtag_info->ejtag_dba0_addr = EJTAG_V25_DBA0;
315 ejtag_info->ejtag_dbm_offs = EJTAG_V25_DBM_OFFS;
316 ejtag_info->ejtag_dbasid_offs = EJTAG_V25_DBASID_OFFS;
317 ejtag_info->ejtag_dbc_offs = EJTAG_V25_DBC_OFFS;
318 ejtag_info->ejtag_dbv_offs = EJTAG_V25_DBV_OFFS;
319
320 ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAn_STEP;
321 ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAn_STEP;
322 }
323 }
324
325 static void ejtag_v20_print_imp(struct mips_ejtag *ejtag_info)
326 {
327 LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
328 EJTAG_IMP_HAS(EJTAG_V20_IMP_SDBBP) ? " SDBBP_SPECIAL2" : " SDBBP",
329 EJTAG_IMP_HAS(EJTAG_V20_IMP_EADDR_NO32BIT) ? " EADDR>32bit" : " EADDR=32bit",
330 EJTAG_IMP_HAS(EJTAG_V20_IMP_COMPLEX_BREAK) ? " COMPLEX_BREAK" : "",
331 EJTAG_IMP_HAS(EJTAG_V20_IMP_DCACHE_COH) ? " DCACHE_COH" : " DCACHE_NOT_COH",
332 EJTAG_IMP_HAS(EJTAG_V20_IMP_ICACHE_COH) ? " ICACHE_COH" : " ICACHE_NOT_COH",
333 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB) ? " noPB" : " PB",
334 EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB) ? " noDB" : " DB",
335 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB) ? " noIB" : " IB");
336 LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8,
337 (uint8_t)((ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) &
338 EJTAG_V20_IMP_BCHANNELS_MASK));
339 }
340
341 static void ejtag_v26_print_imp(struct mips_ejtag *ejtag_info)
342 {
343 LOG_DEBUG("EJTAG v2.6: features:%s%s",
344 EJTAG_IMP_HAS(EJTAG_V26_IMP_R3K) ? " R3k" : " R4k",
345 EJTAG_IMP_HAS(EJTAG_V26_IMP_DINT) ? " DINT" : "");
346 }
347
348 static void ejtag_main_print_imp(struct mips_ejtag *ejtag_info)
349 {
350 LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
351 EJTAG_IMP_HAS(EJTAG_IMP_ASID8) ? " ASID_8" : "",
352 EJTAG_IMP_HAS(EJTAG_IMP_ASID6) ? " ASID_6" : "",
353 EJTAG_IMP_HAS(EJTAG_IMP_MIPS16) ? " MIPS16" : "",
354 EJTAG_IMP_HAS(EJTAG_IMP_NODMA) ? " noDMA" : " DMA",
355 EJTAG_IMP_HAS(EJTAG_DCR_MIPS64) ? " MIPS64" : " MIPS32");
356
357 switch (ejtag_info->ejtag_version) {
358 case EJTAG_VERSION_20:
359 ejtag_v20_print_imp(ejtag_info);
360 break;
361 case EJTAG_VERSION_25:
362 case EJTAG_VERSION_26:
363 case EJTAG_VERSION_31:
364 case EJTAG_VERSION_41:
365 case EJTAG_VERSION_51:
366 ejtag_v26_print_imp(ejtag_info);
367 break;
368 default:
369 break;
370 }
371 }
372
373 int mips_ejtag_init(struct mips_ejtag *ejtag_info)
374 {
375 int retval;
376
377 retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
378 if (retval != ERROR_OK)
379 return retval;
380 LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
381
382 /* get ejtag version */
383 ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
384
385 switch (ejtag_info->ejtag_version) {
386 case EJTAG_VERSION_20:
387 LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
388 break;
389 case EJTAG_VERSION_25:
390 LOG_DEBUG("EJTAG: Version 2.5 Detected");
391 break;
392 case EJTAG_VERSION_26:
393 LOG_DEBUG("EJTAG: Version 2.6 Detected");
394 break;
395 case EJTAG_VERSION_31:
396 LOG_DEBUG("EJTAG: Version 3.1 Detected");
397 break;
398 case EJTAG_VERSION_41:
399 LOG_DEBUG("EJTAG: Version 4.1 Detected");
400 break;
401 case EJTAG_VERSION_51:
402 LOG_DEBUG("EJTAG: Version 5.1 Detected");
403 break;
404 default:
405 LOG_DEBUG("EJTAG: Unknown Version Detected");
406 break;
407 }
408 ejtag_main_print_imp(ejtag_info);
409
410 if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0) {
411 LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
412 "workaround current broken code.");
413 ejtag_info->impcode |= EJTAG_IMP_NODMA;
414 }
415
416 ejtag_info->ejtag_ctrl = EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN;
417
418 if (ejtag_info->ejtag_version != EJTAG_VERSION_20)
419 ejtag_info->ejtag_ctrl |= EJTAG_CTRL_ROCC | EJTAG_CTRL_SETDEV;
420
421 ejtag_info->fast_access_save = -1;
422
423 mips_ejtag_init_mmr(ejtag_info);
424
425 return ERROR_OK;
426 }
427
428 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
429 {
430 struct jtag_tap *tap;
431
432 tap = ejtag_info->tap;
433 assert(tap != NULL);
434
435 struct scan_field fields[2];
436 uint8_t spracc = 0;
437 uint8_t t[4] = {0, 0, 0, 0};
438
439 /* fastdata 1-bit register */
440 fields[0].num_bits = 1;
441 fields[0].out_value = &spracc;
442 fields[0].in_value = NULL;
443
444 /* processor access data register 32 bit */
445 fields[1].num_bits = 32;
446 fields[1].out_value = t;
447
448 if (write_t) {
449 fields[1].in_value = NULL;
450 buf_set_u32(t, 0, 32, *data);
451 } else
452 fields[1].in_value = (uint8_t *) data;
453
454 jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
455
456 if (!write_t && data)
457 jtag_add_callback(mips_le_to_h_u32,
458 (jtag_callback_data_t) data);
459
460 keep_alive();
461
462 return ERROR_OK;
463 }
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